Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

Micron has said it will invest up to $3 billion in the U.S. semiconductor supply chain, with $500 million of that going to GlobalWafers as strategic financing for its 300 mm raw silicon wafer plant in Sherman, Texas, alongside a 10-year agreement giving Micron access to that plant's wafer output. In a separate announcement, the memory maker raised its planned U.S. spending to more than $250 billion through 2035, up from $200 billion, and confirmed the first concrete pour at its Clay, New York campus more than a quarter ahead of schedule.

Sherman is the sole operating facility in the U.S. capable of producing advanced 300 mm raw silicon wafers, the substrate on which every leading-edge DRAM, NAND, and logic die is built. GlobalWafers opened the plant in May last year and holds a $406 million CHIPS Act award covering the site and a silicon-on-insulator facility in St. Peters, Missouri. The 142-acre campus is designed for up to six phases, one of which is running. Micron's other American sites draw their wafers from Japan, Taiwan, Germany, and South Korea; Shin-Etsu, SUMCO, GlobalWafers, Siltronic, and SK Siltron together control the overwhelming majority of global 300 mm supply, making raw silicon the most concentrated layer in the chip space.

Doris Hsu, chairperson and CEO of GlobalWafers, set out her terms for building phase two at Sherman during the plant's opening last year, telling Reuters the company needed profitability at the first two phases, customers willing to sign long-term contracts, reasonable pricing, prepayments, and government support. Thursday's announcement supplies most of that list in a single transaction.

Wafer suppliers spent the 2023-2024 downcycle protecting margins rather than adding capacity, and SUMCO is winding down 200mm production at Miyazaki this year while holding the line on new 300mm expansion. Customers, not suppliers, are therefore now underwriting the capacity. The last time the industry did this, during the 2017-2018 megacycle, chipmakers signed prepaid long-term agreements that turned into liabilities when pricing rolled over.

Silicon wafer shipments reached 3,275 million square inches in Q1 2026, up 13.1% year over year, with SEMI.org attributing the growth to AI data center demand across advanced logic, memory, and power devices. Micron's first new Idaho fab, ID1, is expected to begin wafer output in mid-2027, and production at Clay isn't expected until around 2030. The company began making 1-alpha DRAM at its Manassas, Virginia fab in May.

Micron told investors last December that it can serve only half to two-thirds of customer demand, and nothing announced Thursday changes the supply position of DRAM this year or next.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

Samsung, SK hynix, and Micron were sued on June 25th in the U.S. District Court for the Northern District of California, where 17 plaintiffs accuse the three memory makers of illegally coordinating to restrict DRAM supply and inflate prices that the complaint says have risen roughly 700% over four years. The class action, filed as Garciaguirre v. Samsung Electronics and assigned to Judge Noel Wise, invokes Section 1 of the Sherman Act and targets companies that together hold around 90% of the global DRAM market. Samsung and SK hynix have pleaded guilty to criminal DRAM price fixing once before, with the latter paying a $185 million fine in April 2005.

The complaint argues that the three companies used a coordinated shift toward high-bandwidth memory (HBM), the stacked DRAM that feeds AI accelerators, as a cover to curtail production of older DDR3 and DDR4 modules. That contraction in commodity DRAM, the plaintiffs argue, pushed prices to record highs while no rival could step in: building a new DRAM fab costs tens of billions and takes years, leaving the incumbents free to cut output without fear of being undercut.

The named plaintiffs include 14 individuals and three small PC businesses, among them Troy's Computers and Florida repair outfit My Florida PC, and they cite Apple's recent iPad and Mac price increases as evidence of the squeeze. They’re seeking class status, an injunction, and treble damages as a result.

However, this case revisits a precedent that was already established in the same courthouse. A 2018 class action brought by law firm Hagens Berman made similar claims about parallel production cuts, and the district court dismissed it in 2020. The Ninth Circuit upheld that dismissal in 2022, ruling the trio's conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by an illegal agreement.

It was held at the time that the plaintiffs’ eight “plus factors” didn’t clear Section 1’s threshold, which demands evidence of an actual agreement rather than the conscious parallelism common in a three-supplier market. The new complaint leans on the pivot to HBM as the additional evidence that this earlier lawsuit lacked.

The three memory makers have publicly stated they’re operating independently while redirecting capacity to HBM, and senior executives have warned the shortage could run for years. Investment bank Jefferies expects DRAM prices to rise another 40% to 50% in the third quarter and a further 30% to 40% in the fourth, with no meaningful relief before 2028. The allegations remain unproven, and the defendants have not yet responded in court.

Micron announced this week that it has begun manufacturing 1α (1-alpha) DRAM at its Manassas, Virginia, facility. This action brings the company's most advanced DDR4-compatible process technology to U.S. soil for the first time. The expansion, which Micron says will quadruple DDR4 wafer output at the site, represents a $2 billion-plus investment supported by $275 million in finalized CHIPS and Science Act funding, and production is expected by the end of the year.

The company is the only manufacturer of memory in the United States, and the Manassas fab specifically serves long-lifecycle customers in the automotive, defense, aerospace, industrial, networking, and medical device sectors.

Micron is scaling up DDR4 production as the supply of the older memory standard has become unexpectedly tight. All three major DRAM producers are reallocating fab capacity toward DDR5, LPDDR5X, and high bandwidth memory (HBM) to meet AI-driven demand from hyperscalers and data center operators. Micron itself issued end-of-life notices for mainstream DDR4 and LPDDR4 products in high-volume consumer and data center segments last year, with final shipments to those customers expected to wrap up in early 2026.

That decision has left industries with long product cycles exposed, and S&P Global Mobility estimated that automotive DRAM contract prices could rise 70% to 100% in 2026 compared with 2025 levels, warning that the supply of older-generation automotive DRAM will begin to dry up sharply by 2028. DDR4 inventory buffers for automotive and industrial buyers have reportedly contracted from over 31 weeks to as few as six to eight weeks.

The 1α process node, which Micron first brought to volume production at its Taiwan fabs in late 2020, delivers roughly 40% higher bit density than the preceding 1z node and was the first DRAM technology to achieve sub-15nm cell dimensions. It uses DUV lithography rather than the more expensive EUV tools that Samsung has adopted for its advanced DRAM nodes. Micron's newer 1β and 1γ nodes are dedicated to DDR5, LPDDR5, and HBM.

Onshoring 1α to Virginia effectively creates a dedicated domestic production line for DDR4 and LP4 memory that won't compete for wafer starts with Micron's leading-edge AI-focused products. The Manassas site will also support more than 3,100 direct manufacturing and community jobs.

The Virginia fab is part of Micron's broader $200 billion U.S. investment plan. The company broke ground on a new memory manufacturing complex in Clay, New York, in January, and initial wafer output at its first new Idaho fab is expected in mid-2027. Micron has also committed to eventually adding HBM advanced packaging capabilities at the Virginia site once sufficient DRAM wafer capacity is established at its other U.S. facilities.

Across all three sites, Micron says the investments will create an estimated 90,000 direct and indirect jobs.

Micron’s planned $24 billion NAND flash expansion in Singapore will require 400 to 500 power transformers, which is more than double the 100 to 150 units a standard wafer fab typically needs, according to industry sources as reported by DigiTimes. The scale exceeds the annual output capacity of any single Taiwanese transformer manufacturer, turning heavy electrical equipment into a bottleneck for AI-driven semiconductor buildouts.

This level of demand from Micron reflects the power intensity of modern memory fabs tied to AI. HBM production for AI servers has driven every major memory maker into simultaneous expansion, and the electrical infrastructure required to support those fabs is now outpacing the supply chain built to serve it.

Micron's Singapore project, where production is targeted for late 2028, is one piece of a broader global buildout. The company has acquired PSMC's Miaoli Tongluo fab in Taiwan for $1.8 billion, with that facility slated for 2026, while new plants in Idaho and New York are underway, and a Hiroshima facility is expected to begin operations in the second half of 2026.

Samsung Electronics and SK hynix have also announced their own capacity expansions, all driven by the same demand curve: AI server deployments consuming HBM at volumes that existing production lines cannot satisfy. We’re now seeing a synchronized wave of fab construction across three continents as a result, with each project competing for the same pool of heavy electrical equipment and raw materials.

The toll this is taking is already visible in pricing and availability, with major heavy electrical equipment suppliers Fortune Electric and Allis Electric both having implemented price increases of 20% to 30%, driven by the surge in orders and rising costs of copper and other raw materials. Meanwhile, some transformer manufacturers have declined to quote on large-scale semiconductor projects entirely, citing an inability to meet the tight timelines and volume requirements. Industry sources say no single maker can absorb the scale of orders now flowing from the AI and semiconductor sectors.

International transformer brands, despite commanding higher prices, are gaining ground because their larger overseas factories can push out more units. Domestic Taiwanese manufacturers have responded by collaborating with secondary suppliers, dividing specifications and capacity across multiple firms to meet individual customer demands.

Transformers are also shared infrastructure, and, beyond fabs, the same equipment is needed for AI data center construction, utility-scale energy storage, and grid expansion projects. A supply chain that was already stretched before the AI buildout wave is now absorbing orders measured in the hundreds of units per project.

Unfortunately, delayed transformer deliveries will likely translate into delayed fabs, which in turn will push back the timelines for memory production that AI buyers are counting on. Data center operators planning new facilities are in the same queue, competing with semiconductor companies for equipment that takes months to manufacture and deliver.

Micron CEO Sanjay Mehrotra said that cars will eventually require more than 300GB of RAM as automakers introduce vehicles that have L4 autonomy. According to The Register, Mehrotra said this after Micron released its quarterly earnings report, with the company reporting $23.86 billion in revenue for the second quarter of this year — a huge 200% jump from the $8.03 billion it posted in 2Q25. This massive jump is still driven by the incredible demand for premium HBM chips from AI hyperscalers combined with “structural supply constraints and Micron’s strong execution across the board.”

As the company is raking cash from the AI infrastructure build out, it’s also expanding its output with several planned fabs in Japan, Singapore, and even a “megafab” in New York. These projects are expected to come online between 2028 and 2029, and the Micron CEO said that it’s looking to boost output by 20% in 2026, which could help alleviate some of the pressure on the supply side. However, even as these new factories start production, Mehrotra predicts that there will be a new market that demands massive amounts of high-speed memory — self-driving cars.

There are six levels of vehicle autonomy, starting at L0 for cars that have no driving automation whatsoever. A vehicle with a single automated system (such as cruise control) counts as L1, while those equipped with advanced driver assistance systems (ADAS) that both control steering and acceleration, such as Tesla’s Autopilot and Cadillac’s Super Cruise, are considered as L2. On the other hand, vehicles with L4 autonomy basically do not need human intervention in any task, like overtaking or deciding when to cross a busy intersection. However, it still gives the driver the option to take control and manually drive the vehicle.

Nvidia announced that it’s working with Chinese carmakers BYD and Geely and Japanese marques Isuzu and Nissan to adopt the Nvidia Drive Hyperion platform. This is the AI chip maker’s end-to-end autonomous vehicle platform meant to deliver an L4 system to car manufacturers. Since this is an AI system, it will likely demand a lot of high-speed memory to be able to run effectively.

Most modern vehicles require at least 16GB of memory, but if car makers introduce L4 autonomy, it will definitely need a lot more RAM. We’ve seen this with the shortage of high-end Macs with up to 512GB of Unified Memory as many users have become interested in running the likes of OpenClaw on their own systems. It has even gotten to the point that Apple pulled the $4,000 512GB Mac Studio from its online store and raised the 256GB version to $2,000. So, if carmakers started churning out hundreds of thousands, if not millions of vehicles with AI-powered driverless features, Micron expects demand for automotive memory to pick up as well.

This might take some time to happen, though, especially as vehicles with these features are quite expensive and regulations haven’t quite caught up with L4 autonomy just yet. But if and when people start buying cars like these, we hope that memory chip makers have excess capacity to absorb the increase in demand. Otherwise, we might be seeing another round of memory chip shortages, this time driven by AI supercomputers on wheels.

Micron has announced that it has entered high-volume production of its HBM4 36GB 12-Hi memory, designed for Nvidia's Vera Rubin GPU platform. Making the announcement at GTC 2026, the memory giant simultaneously confirmed high-volume production of the industry's first PCIe 6.0 data center SSD and a new SOCAMM2 module, making it the first memory supplier to bring all three products to volume shipment for the Vera Rubin ecosystem at the same time.

The HBM4 36GB 12H stack runs at over 11 Gb/s pin speeds, delivering bandwidth greater than 2.8 TB/s. Compared to Micron's HBM3E at the same 36GB 12H configuration, that represents a 2.3 times bandwidth increase alongside more than 20% improvement in power efficiency, according to Micron's internal power calculator data.

"The next era of AI will be defined by tightly integrated platforms developed through joint engineering innovations across the ecosystem. Our close collaboration with NVIDIA ensures that compute and memory are designed to scale together from day one," said Sumit Sadana, executive vice president and chief business officer at Micron Technology, in a press release. "With HBM4 36GB 12H, alongside the industry's first SOCAMM2 and Gen6 SSD now in high-volume production, Micron's memory and storage form a core foundation that unlocks the full potential of next-generation AI."

Micron has also shipped samples of a 48GB 16H HBM4 stack to customers. The additional four die layers give the 16H configuration a 33% capacity increase per HBM placement over the 36GB 12H product, a milestone that points toward denser configurations in future AI accelerator generations.

Last month, the company announced that the 9650 SSD had entered mass production, marking the first time that a PCIe 6.0 SSD had entered that stage of production. The drive supports up to 28 GB/s sequential read throughput and 5.5 million random read IOPS, doubling PCIe 5.0 read performance at 100% higher performance per watt. Unsurprisingly, it targets AI inference, training, and agentic workloads in liquid-cooled environments and is optimized for Nvidia's BlueField-4 STX reference architecture.

Meanwhile, the 192GB SOCAMM2 module is designed for Nvidia Vera Rubin NVL72 systems and standalone Vera CPU platforms, with Micron's SOCAMM2 portfolio spanning 48GB to 256GB capacities. The Vera Rubin platform supports up to 2TB of memory and 1.2 TB/s of bandwidth per CPU using the module.

SK Hynix has announced the successful development of its first LPDDR6 DRAM, touting 33% greater speed and 20% better power efficiency compared to previous generation LPDDR5X memory. The memory manufacturer also announced that it has developed its LPDDR6 memory on its leading-edge 10nm-class (1c) process node that it announced in 2024.

The new modules have a base operating speed of "over" 10.7 Gbps — which exceeds the fastest outgoing LPDDR5X memory modules on the market today — and a memory capacity of 16Gb per chip. To help with power consumption, SK Hynix implemented a new sub-channel structure and DVFS, or Dynamic Voltage and Frequency Scaling, which it says reduces power consumption by more than 20% compared to previous generation LPDDR memory products. The sub-channel structure accomplishes power reductions by powering only the data paths that are in use, while DVFS reduces clock speed and voltage when memory demands are light.

SK Hynix has announced its LPDDR6 eight months after JEDEC finalized and published the LPDDR6 standard last July. However, SK Hynix is not the first manufacturer to make LPDDR6; Samsung already announced its first LPDDR6 product and showcased it at CES 2026, with speeds up to 10.7Gbps.

SK Hynix has confirmed that its 1c LPDDR6 will be used in smartphones and tablets, but we can also expect LPDDR6 to be a huge boon in the datacenter market. LPDDRX has been very popular in AI servers that take advantage of SOCAMM/SOCAMM2 memory modules that only support LPDDR memory. For instance, Nvidia's GB300 Grace Blackwell Ultra Superchip uses SOCAMM, and Nvidia's latest Vera Rubin Superchip uses SOCAMM2 memory modules. Late last year, SK Hynix stated that it expects post-Vera Rubin Nvidia AI chip designs to take advantage of LPDDR6.

This is just the beginning for LPDDR6; speeds well beyond 10.7Gbps are expected to become the norm as memory makers get to grips with optimizing and improving on their LPDDR6 designs. The JEDEC group believes that LPDDR6 will have data rates of up to 14,400 MT/s, which is well beyond what the fastest DDR5 overclocking record holds.

Most of the conversation about speed in AI datacenters revolves around the accelerators themselves, discussing tokens per second and the like. However, the battle for AI performance is fought on multiple fronts, and one of them is in memory capacity and power efficiency. Today, Micron unveiled what look to be the industry's first 256 GB SOCAMM2 units, a sizable step up from the last-best 192 GB modules released just six months ago.

The company says it's now shipping samples to customers, who will most definitely be happy at the notion of having 2TB of memory wired to each CPU. For just one major example, the typical Nvidia NVL72 rack can now carry 72 TB of RAM for its 36 CPUs.

The 33% improved density over previous-generation SOCAMM2 is excellent news on its own, but that's not the only advantage of this form factor. The new modules ought to offer 66% better power efficiency compared to bog-standard RDIMMs, and they're compatible with increasingly popular (and necessary) liquid cooling for AI servers.

According to Micron, the new sticks are the first to employ its 32 Gb (4 GB) LPDDR5X monolithic dies, where "monolithic" means all the memory and relevant circuitry are part of a single die.

Given the target market for these large SOCAMM2s, the firm touts the real-world performance improvements beyond just density and power efficiency. Having this much RAM available to a single processor lets AI models use much larger context windows. Consequently, it helps reduce the all-important TTFT (Time To First Token), meaning bots start answering your questions quicker.

In an AI future where context is literally everything, every gigabyte of memory closer to the xPUs in a system matters, and Micron's advancement today will doubtless be found in massive AI server installations worldwide as companies allocate hundreds of billions of dollars of capex in the race toward AI supremacy.

The SOCAMM2 form factor is the result of a partnership between Nvidia and memory makers Micron, Samsung, and SK hynix. The SOCAMM standard was originally designed by Nvidia, but the accelerator mogul reportedly had trouble getting the modules to operate without overheating on high-density servers. CEO Jensen Huang wisely teamed up with the folks who make computer memory for a living, resulting in SOCAMM2s with growing density and lower power consumption.

Micron has finally joined the 3GB GDDR7 party and has officially introduced 3GB modules to compete with Samsung and SK Hynix's 3GB variants. The memory maker officially announced its larger GDDR7 version in a blog post, revealing that its new 3GB ICs operate at 36 Gbps.

The new modules are 12.5% faster than the first GDDR7 modules that hit the market, which achieved 32 Gbps of bandwidth. However, Micron's new modules are noticeably slower than Samsung's competing solutions, which can run at up to 42.5 Gbps. SK Hynix similarly has outgoing GDDR7 modules that can scale up to 40 Gbps, and is working on future models that can reach 48 Gbps.

However, in Micron's favor, there are no outgoing Nvidia graphics cards that take advantage of GDDR7 speeds anywhere near 40 Gbps or faster. The highest GDDR7 transfer speeds on outgoing GDDR7 GPUs include the RTX 5080, which has its memory modules running at 30 Gbps. Other cards, such as the RTX 5090, use even lower memory speeds of 28 Gbps. That said, we have seen memory overclocks on the RTX 5070 Ti and RTX 5090D of up to 34 Gbps on SK Hynix and Samsung GDDR7.

As a result, there's not much reason for Micron to introduce new GDDR7 memory modules with blisteringly fast speeds of 40 Gbps or newer. The next generation RTX 60 series or next generation AMD Radeon GPUs might take advantage of higher memory speeds, but it's not required right now on existing GDDR7 GPUs.

Beyond speeds, having a third manufacturer for 3GB GDDR7 will be highly beneficial for Nvidia and other GPU makers. Nvidia is already taking 3GB GDDR7 chips from both Samsung and SK Hynix, and likely will start introducing Micron 3GB GDDR7 to help compensate for the outgoing NAND flash/memory shortage. Currently, the only Nvidia GPUs that use 3GB GDDR7 are the laptop-variant of the RTX 5090 and the RTX Pro 6000 Blackwell workstation GPU. If Nvidia ever decides to launch the RTX 50 Super series, it is expected that all rumored GPUs in that lineup, the RTX 5080 Super, 5070 Super, and 5060 Super, will use 3GB modules.

The artificial intelligence supercycle is reshaping the semiconductor and electronics industries, as the scale of the AI infrastructure buildout strains the entire supply chain. While developers of AI accelerators like Nvidia are cashing in on the AI boom, it's memory makers that will earn the most cash, according to estimates from TrendForce. Arguably, this is a result of the different business models and expansion strategies memory makers use compared to foundries, in addition to the behavior of the commodity market.

Demand outstrips supply

The company projects that while global foundry revenue is expected to total $218.7 billion, 3D NAND and DRAM revenue will reach $551.6 billion, which means that the total market for memory is more than twice as large as contract chip production. TrendForce attributes this to structural market changes caused by AI buildouts. The latter creates elevated demand for specific types of memory, creating shortages of all types of memory, and therefore affecting prices across the industry. As a consequence, while the AI industry does not need low-capacity commodity memory devices, they also become substantially more expensive amid tight supply. This creates the perfect conditions for memory makers to capitalize upon.

Indeed, the spot price of a 16 Gb DDR5 chip at DRAMeXchange was $38 on average, with a daily high of $53 and a daily low of $25. By contrast, the very same chip used to cost $4.75 on average just one year ago ($3.70 session low, $6.60 session high). Similar changes occurred to the prices of 3D NAND memory in recent quarters.

Fundamental differences

Just like some other analyst firms, TrendForce calls the AI megatrend a 'supercycle,' indicating its overwhelming ubiquity, which affects multiple industries, and its potential length.

There were two periods in the last few decades when revenue of memory makers grew significantly year-over-year for two years in a row: in 2017 – 2018, when hyperscalers built their vast data centers (+62% in 2017 and +27% in 2018), and in 2020 – 2021, when people increased purchases of PCs amid the COVID-19 pandemic. In both cases, memory makers increased capacity to meet demand and maintain their market share, which caused sharp drops in revenue back in 2019 and 2022.

The foundry industry — which is much more capital-intensive than the 3D NAND or DRAM industries — uses fabs that are harder and longer to build, and only suffered a year-over-year revenue decline in 2023.

The situation today is vastly different. On the one hand, leading developers of frontier AI models need the most powerful clusters to train their models, therefore creating demand for leading-edge hardware with expensive HBM3E memory and plenty of storage. On the other hand, these companies and their clients need more powerful inference systems to use those models. Therefore, demand for CPUs, AI accelerators, memory, and storage does not decline over time. Meanwhile, buyers like cloud service providers (CSPs) tend to be less sensitive to price increases, which is why 3D NAND and DRAM suppliers are expected to raise average selling prices more aggressively than in the past cycles.

Foundry vs. Commodity

3D NAND and DRAM are commodities, so their prices behave like prices of commodities, almost immediately reacting to tightening supply, increasing demand, or sentiment among buyers. While large PC makers purchase their memory at prices agreed upon every six months, a significant portion of memory is sold on the spot market.

This dynamic is reflected in TrendForce's projections that show memory revenue growth accelerating after the downturn of 2022 – 2023, including an expected 80% increase in 2024, followed by 46% growth in 2025, and a projected 134% surge in 2026.

By contrast, foundries tend to operate under long-term agreements that smooth price fluctuations, which prevents sharp swings that characterize memory markets. Even during periods of strong demand, foundry pricing adjustments occur gradually, which means slower revenue growth compared to memory vendors.

TrendForce models that following a 19% year-over-year revenue increase in 2024, the foundry market grew 25% in 2025 and will grow another 25% this year.

As a result, boosted by the AI supercycle and not constrained by long-term agreements, memory vendors will earn more than two times more this year alone compared to producers of logic, which have to adhere to their long-term contracts.

The biggest question

With HBM4 memory devices using four times more silicon than typical DRAM ICs, it is obvious that memory makers cannot meet all the demand that exists because of insufficient capacity, which results in price adjustments. However, the biggest question is how significantly current commodity 3D NAND and DRAM prices are influenced by insufficient supply, and how significantly they are influenced by typical commodity memory market behavior that dictates that customers buy more memory when it is getting more expensive, as it may get even more expensive in the future?

In one of the most hotly competitive and profitable tech industries, the three major memory makers, Samsung, SK Hynix, and Micron, are individually investigating their customers to prevent memory hoarding, according to Nikkei Asia. They’re asking customers to disclose their own customers and order volumes to ensure that no one is hoarding more memory than they need, exacerbating memory supply problems.

The immediate impact of this may well be to accelerate price increases for consumer devices. After all, if a company can’t buy cheaper memory now, it could be more expensive to buy it later. But this may help give memory makers the confidence they need to effectively invest in increased production, and it might just give smaller customers a chance to compete fairly.

Fool me twice… you can’t fool me again

Since memory demand started skyrocketing in 2025, memory makers have been inundated with calls to increase supply while brands panic-bought what was available. Ramping up production lines and retooling fabs is required, but it’s not that easy. NAND flash, particularly the newest and most capable chips, uses cutting-edge facilities, and those manufacturing lines take years to bring online.

Production can and is being increased, but the required investment for such an endeavour is enormous. Though the potential upsides are excellent – increased supply should mean the memory makers can sell more in turn – the potential downsides are there too. Most notably, if supply and demand equalize, any industry changes could swing the ratio in the other direction, leaving the memory companies oversupplied and competing with each other to sell what they have.

This isn’t some theorized scenario, either. It’s already happened, which is why Samsung, SK Hynix, and Micron are twice shy about increasing production.

During the pandemic, as everyone rushed to buy desktops and laptops to work from home, memory was once again in short supply, and the memory makers scrambled to catch up. They invested in new facilities, taped out new production lines, and pivoted the enterprise to adjust to a new world where memory wasn’t plentiful.

But it wasn’t to last. Just a few years later, as demand started to fall, problems arose. Because during those pandemic months and years, customers of the major memory manufacturers overbooked and built up stockpiles of their own, they didn’t continue to replace them when their own orders dwindled. By the end of 2022, memory sales had dropped by almost a third, and revenue was crashing right behind it as the going price for memory cratered.

This led to companies like Samsung actually cutting production of its 3D NAND and DRAM products. Although it claimed to be continuing R&D expansion and infrastructure building, it wasn't on the same scale as it would have been had orders remained strong. SK Hynix followed suit several months later, and those cuts continued throughout 2023 across a range of companies.

Which brings us back to 2026. This time, the memory makers are looking to ensure that the memory hoarding doesn’t happen, so that if and when demand and supply are realigned, there’s less chance of the swing continuing into oversupply, under-demand territory.

That’s good for them, because it means demand should remain stable even if there are wobbles in the AI industry, or even an eventual bubble burst and collapse. If memory customers don’t have their own stockpiles, they’ll still need at least some memory, even if demand falls dramatically.

But won’t this just keep memory prices permanently high? Won’t it help prevent a big pricing correction if and when that bubble bursts, just keeping us all paying over the odds for memory forever?

Perhaps.

A boon to consumers

In the near term, it might actually stop memory prices from rising as quickly. If customers of Micron, Samsung, and SK Hynix have been overbuying – and why wouldn’t they, if they can afford it – then preventing that immediately should curb demand. That could help slow the current parabolic price rises for memory specifically. While that might mean the major customers who had planned on stockpiling cheaper memory end up raising their prices sooner than they had planned, the overall effect should see a slowdown.

Similarly, cutting the overbooked orders should make it easier for smaller memory customers to gain access to orders. If they aren’t trying to compete with not only major companies but also major companies overbuying, they should find it easier to get stock of memory at fairer prices. That has the potential to stabilize industries and prevent smaller brands from being pushed out of markets entirely, keeping competition healthier, which is always good for customers.

It could also help give the memory manufacturers the confidence they seek to build out production faster and more effectively. Whereas previously their efforts in boosting supply ended up with them having to reduce supply down the line, this way they can be more confident of a longer tail for their business.

We just had a flurry of new investment announcements from Micron, SK Hynix, and Samsung, all of which are building new fabrication lines and packaging facilities. They won’t really come online until 2027-2028, but that at least gives us some time frame for when memory supply and demand could stabilize, with or without an AI bubble collapse.

Here’s hoping

What Micron, SK Hynix, and Samsung are doing in looking over the books of their customers feels like them expanding their influence even beyond being one of the most important technological bottlenecks facing the world right now. It feels intrusive, and even a little oppressive. They’re looking to control not only this limited supply of incredibly important hardware, but what their customers do with it, too.

But what’s good for them may be better for us, too. Demand policing doesn’t create new chips, but in reducing the phantom demand, they do lower overall demand, and bring back a little more predictability to an industry that has been racing ahead of everyone’s best guesses as the world panic bought what was available in a rush against one another.

Now, maybe the smaller buyers can compete because they aren’t trying to compete against capital and stockpiles. The memory makers can commit to capacity expansion without fearing a post-AI cliff face, as they did with the pandemic aftermath.

None of that is guaranteed, and the bigger buyers will continue to outweigh their smaller contemporaries and garner the priority they seek. But if it can slow things down just a little, it might make the next hard year ahead a little softer while we wait for that new capacity to come online in the years to come. Cutting that overbuying now is one of the few levers the industry can pull to prevent this cycle from getting far worse before it may get better.

Update 17/02/2026 9:30am PT: Article introduction amended to reflect that the memory makers are operating independently of one another.

ASML this week posted its highest yearly result ever as demand for its chipmaking tools set records. The company's revenue for the fiscal year 2025 totaled €32.7 billion ($39 billion USD), up 15% from the previous year. As expected, sales of lithography and other wafer fab equipment to China-based entities decreased in 2025 due to export rules imposed by the U.S. and the Netherlands. When it comes to sales of lithography systems, EUV tools became the leading source of ASML's revenue.

Fewer sales in China

Driven by the Made in China 2025 program and the buildout of the Chinese semiconductor industry amid tightening export curbs by the U.S. in recent years, ASML's sales to the People's Republic set records and culminated with 41% of the company's system unit share in 2024. Last year, sales of ASML's fab tools to China dropped, but 33% of ASML's tools (in terms of units) were sold to the PRC, meaning that Chinese chipmakers kept buying dozens of lithography and other machines for their fabs that use trailing nodes. Some of those older DUV systems are reportedly being upgraded by grey-market means.

China is followed by sales of wafer fab equipment to customers in South Korea (25%) and Taiwan (22%). By contrast, only 12% of ASML-produced tools (by unit count) were shipped to the U.S.

High-end EUV

U.S.-based Intel bought the world's first High-NA EUV Twinscan EXE:5200B lithography tool with 0.55 numerical aperture optics, designed for mass production of chips using next-generation process technologies, such as Intel's 14A (1.4nm-class). Another system was assembled at SK hynix's fab M16 in Icheon, South Korea. Meanwhile, ASML has supplied eight High-NA EUV tools (including six EXE:5000 and two EXE:5200B machines) to additional partners so far.

Speaking of EUV lithography systems, it's important to note that both current-generation Low-NA EUV scanners and next-generation High-NA EUV machines accounted for 48% of ASML's system revenue in 2025 (or €11.6 billion / $13.8 billion USD), up from 38% a year earlier. For the whole year, the company shipped 48 EUV systems and 131 immersion DUV tools, up from 44 EUV scanners and 129 immersion DUV machines in 2024.

Sales of EUV and sophisticated DUV tools are primarily driven by leading-edge logic fabs that build chips for AI infrastructure as well as smartphones and PCs. In fact, logic fabs accounted for 66% of ASML's system sales, whereas memory accounted for 34%. Although both logic and memory makers strive to increase their output and procure new tools, logic producers buy more expensive EUV systems.

"In advanced Logic, our foundry customers have become more positive on the long-term sustainability of demand on a number of fronts," said Fouquet. "AI accelerators are migrating from the 4nm node to the more litho-intensive 3nm node. At the same time, customers continue to ramp the 2nm node in support of next-generation HPC and mobile applications."

However, as DRAM vendors adopt more sophisticated fabrication processes that rely on EUV, they will also intensify procuring EUV scanners, which will significantly increase demand for this type of equipment as memory makers tend to operate very large fleets to fab commodity products in the most cost-efficient way.

"In memory, our customers are reporting very strong demand for both HBM and DDR products with supply remaining very tight through at least 2026 as they ramp both their 1b and 1c nodes in support of the demand," Fouquet added. "In addition, DRAM customers continue to adopt more EUV layers on these nodes. This is expected to continue on their future nodes as they migrate more multi-patterning DUV to single-exposure EUV, resulting in an increase in litho intensity."

Record results

ASML closed 2025 with a record fourth quarter and its strongest year ever. In Q4 2025, the company's revenue totaled €9.7 billion ($11.5 billion USD), its gross margin reached 52.2%, and net income hit €2.8 billion ($3.3 billion USD).

For the full year, the company generated €32.7 billion ($39 billion USD) in net sales, up from €28.3 billion ($33.8 billion USD) in 2024, with a 52.8% gross margin and €9.6 billion ($11.4 billion) in net income.

ASML's net bookings reached €28.0 billion ($33.4 billion USD), whereas their year-end backlog grew to €38.8 billion ($46.3 billion USD), another record for the company.

During the final quarter of 2025, the company supplied 94 new photolithography systems as well as eight used lithography machines. For the whole year, ASML sold 300 new lithography tools and 27 used lithography systems.

For the first quarter of 2026, ASML expects revenue of €8.2 billion – €8.9 billion ($9.7 - $10.6 billion USD), which is up year-over-year but down sequentially. Full-year 2026 revenue is projected to be between €34 billion and €39 billion ($40 billion - 46 billion USD), this reflects growing demand for lithography tools and EUV scanners, primarily due to the wide AI infrastructure buildout. Gross margins at ASML are projected to be between 51% and 53%.

"In the last months, many of our customers have shared a notably more positive assessment of the medium-term market situation, primarily based on more robust expectations of the sustainability of AI-related demand," said Christophe Fouquet, chief executive of ASML. "This is reflected in a marked step-up in their medium-term capacity plans and in our record order intake. Therefore, we expect 2026 to be another growth year for ASML's business, largely driven by a significant increase in EUV sales and growth in our installed base business sales. We continue to invest in people and footprint to support that growth in 2026 and beyond."

Looking ahead

Being the only supplier of EUV and advanced DUV tools on the planet, ASML has every reason to expect sales of these scanners to increase in the coming years. The number of EUV layers increases with the upcoming process technologies, driving its revenue all the way to €44 billion - €60 billion ($52 billion - 71 billion USD) in 2030. Indeed, EUV tools accounted for 65% of ASML's backlog in late 2025, up from 62% a year before. If the demand for their tools continues apace, then ASML will be sitting as one of the most important companies in the ongoing AI boom, right alongside Nvidia.

Micron this week announced that it had begun construction of a new advanced wafer fabrication facility in Singapore, which will take over 10 years to completely build and will cost about $24 billion. The new fab will produce 3D NAND memory with initial wafer output sometimes in the second half of 2028.

The new Fab 10B is being built at Micron's existing 3D NAND manufacturing campus in North Coast Wafer Fab Park in Singapore and is designed to deliver up to 700,000 square feet of cleanroom space once it's fully built out. To put the number into context, Micron's Fab 10A and Fab 10X have a cleanroom space of around 500,000 square feet, so the new Fab 10B will more than double Micron's 3D NAND capacity in Singapore.

"This investment underscores Micron’s long-term commitment to Singapore as an important hub in our global manufacturing network, enhancing supply chain resiliency and fostering a vibrant ecosystem for innovation," said Manish Bhatia, executive vice president of global operations at Micron Technology.

The new facility will be Singapore's first double-story wafer fab, which will enable Micron to build it out in iterations and without increasing actual footprint of the fab, which greatly simplifies building out the facility, albeit at the cost of more complex architecture.

The new Fab 10B will be configured in a way to support multiple next-generation 3D NAND manufacturing technologies, including nodes with over 500 active layers, so expect it to be equipped with the latest fabrication tools. In addition to volume production of 3D NAND, the new facility will also be used for R&D purposes, which will greatly simplify process integration and product ramps up. As an added bonus, the new facility will enable Micron to deepen its collaboration with academic and industrial research partners in the region.

Micron says that the new fab will focus on production of high-capacity 3D NAND devices for AI and data center applications, as the company considers these applications its major growth engines going forward. Still, it is necessary to note that the fab will be capable of making all types of 3D NAND devices if Micron needs to in response to future market changes. The current AI boom may or may not last beyond the 10-year timeframe it'll take for Fab 10B to become fully operational, so that versatility is welcome in the face of the typically cyclical nature of silicon demand.

In addition to producing 3D NAND in Singapore, Micron is also constructing an HBM assembly plant in the country. That HBM packaging operation remains on track to contribute materially to Micron's HBM output in calendar 2027.

From an employment standpoint, the new 3D NAND wafer fab is expected to create around 1,600 jobs, largely focused on fab engineering and manufacturing operations. Combined with the approximately 1,400 roles associated with the HBM packaging facility, Micron's current expansion plans in Singapore amount to about 3,000 new positions.

In an unexpected turn of events, Micron announced plans to buy Powerchip Semiconductor Manufacturing Corporation's (PSMC) P5 fabrication site in Tongluo, Miaoli County, Taiwan, for a total cash consideration of $1.8 billion. To a large degree, the transaction would evolve Micron's long-term 'technology-for-capacity' strategy, which it has used for decades. This also signals that DRAM fabs are now so capital-intensive that it is no longer viable for companies like PSMC to build them and get process technologies from companies like Micron. The purchase is also set against the backdrop of the ongoing DRAM supply squeeze, as data centers are set to consumer 70% of all memory chips made in 2026.

"This strategic acquisition of an existing cleanroom complements our current Taiwan operations and will enable Micron to increase production and better serve our customers in a market where demand continues to outpace supply," said Manish Bhatia, executive vice president of global operations at Micron Technology. "The Tongluo fab's close proximity to Micron's Taichung site will enable synergies across our Taiwan operations."

Deal expected to close in Q2 2026

The deal between Micron and PSMC includes 300,000 square feet of existing 300mm cleanroom space, which will greatly expand Micron's production footprint in Taiwan. By today's standards, a 300,000 square foot cleanroom is a relatively large one, but it will be dwarfed by Micron's next-generation DRAM campus in New York, which will feature four cleanrooms of 600,000 square feet each. However, the first of those fabs will only come online in the late 2020s or in the early 2030s.

The transaction is expected to close by Q2 2026, pending receipt of all necessary approvals. After closing, Micron will gradually equip and ramp the site for DRAM production, with meaningful wafer output starting in the second half of 2027.

The agreement also establishes a long-term strategic partnership under which PSMC will support Micron with assembly services, while Micron will assist PSMC's legacy DRAM portfolio.

The end of a tried and true model?

While the P5 site in Tongluo isn't producing memory in high volumes today, the change of ownership and inevitable upgrade of the fab itself will have an impact on global DRAM supply, which is good news for a segment that is experiencing unprecedented demand. While it is important that Micron is set to buy a production facility in Taiwan, it is even more important that the transaction marks an end to its technology-for-capacity approach to making memory on the island. In the past, instead of building large amounts of new greenfield fabs in Taiwan, Micron partnered with local foundries (most notably PSMC, but also with Inotera and Nanya) and provided advanced DRAM process technology in exchange for wafer capacity, manufacturing services, or fab access.

This approach allowed Micron to expand output faster and with less capital risk, leveraged Taiwan's mature 300mm manufacturing ecosystem, and avoided duplicating the front-end infrastructure, which was already in place.

However, it looks like the traditional technology-for-capacity model — which worked well in the 90nm – 20nm-class node era — no longer works. It worked well when DRAM fabs cost a few billion dollars, when process ramps were straightforward, and when partners could justify their capital risks in exchange for technologies (which cost billions in R&D investments) and stable wafer demand.

Today’s advanced DRAM fabs require $15 – $25 billion or more of upfront investment. This would go into equipment like pricey EUV scanners, as well as longer and riskier yield ramps. In that environment, a partner running someone else's IP absorbs massive CapEx and execution risk while getting limited advantages, which makes the economics increasingly unattractive: after all, if you can invest over $20 billion in a fab, you can certainly invest $2 billion in R&D.

The end of an era

In recent years, Micron's behavior has reflected this shift in thinking. Early technology-for-capacity deals helped it scale quickly, but once fabs crossed a certain cost and complexity threshold, Micron had to move on and own fabs instead of renting capacity. This is reflected in moves like its Elpida acquisition in 2013, where the company purchased a bankrupt memory maker to secure the company's capacity. This was followed up in 2016 with the Inotera acquisition, and now with PSMC.

What remains of the model is essentially pushed to legacy nodes, which are almost all fully depreciated, or to specialty DRAM, which does not require leading-edge process nodes. Other remnants of the model may be found in additional backend services, where capital intensity and strategic risks are also lower.

For leading-edge DRAM, ownership and control now outweigh the benefits of partnership, which marks the end of an era as modern fabs are now too expensive, too strategic, and too tightly integrated with product roadmaps. The acquisition of the P5 site was preceded by perhaps the last technology for a capacity partnership for Micron in Taiwan. Now, the American company will own the site and invest in its transition to its latest process technologies.

For the first time since announcing its seismic decision to kill its consumer SSD and memory brand Crucial, Micron has addressed the notion that it is leaving consumers behind in a new interview. The company also warned that despite breaking ground on new memory fabs, we shouldn't expect to see meaningful output impacting memory supply until at least 2028.

Micron's push back against the criticism of its decision to shutter Crucial comes by way of a WCCFTech interview with Christopher Moore, Micron's VP of Marketing, Mobile and Client Business Unit. The outlet wasted no time pressing Moore in Micron's controversial, but not entirely unexpected, decision to shutter the Crucial brand late last year. In early December, the company said that it plans to wind down its consumer business by the end of next month (January), reallocating its output and time to enterprise-grade DRAM and SSDs for AI buildouts.

Moore was asked if memory suppliers were inclined towards catering to the AI sector, "leaving consumers behind" as a result. "Well, first I would want to try to help everybody understand that the perception may not be exactly correct, at least from our point of view," Moore said. He stated that while he would "never want to tell someone what to think or that they're wrong... our viewpoint is that we are trying to help consumers around the world." Moore then cited Micron's sizeable businesses in the client and mobile market. Moore hinted that Micron is still technically serving consumers by supplying LPDDR5 to OEMs like Dell and Asus for inclusion in laptops, amongst other things. While this is technically correct, the news will be of little comfort to the DIY community and enthusiasts facing colossal price increases.

While the report claims Micron is in contact with "every single PC brand out there", the company simply cannot afford to ignore AI demand.

Some hope on the horizon for PC builders and the consumer sector is increased DRAM capacity in the supply chain. Micron recently announced it would begin work on a $100 billion New York 'megafab', where it plans to produce 40% of the company's overall DRAM output by the 2040s. Moore also noted its upcoming ID1 facility in Idaho, which is scheduled to come online in mid-2027. However, he warned that it will be 2028 before we see "real output, meaningful output," in its DRAM supply chain. Don't forget that Micron can't even keep up with current demand. Its CEO said in December that it can only meet half to two-thirds of demand, meaning that even the upcoming new capacity will initially go towards making up shortfalls for existing demand. As such, while 2028 might mark the first meaningful dent Micron makes in DRAM supply, it could be months more before consumers start to see any shift in pricing for PC builds.

Sandisk is on track to double the price of its high-capacity 3D NAND memory devices for enterprise-grade solid-state drives this quarter in anticipation of strong demand for server-class storage in the coming quarters, reports Nomura Securities (via @jukan05). It is unclear to what degree the price increase of high-capacity 3D NAND will affect quotes on mainstream flash memory used in client devices, but normally, 3D NAND for smartphones and PCs follows enterprise-grade chips as they are made at the same fabs.

"Channel checks indicate that several memory suppliers continued to push prices higher, with enterprise-grade NAND facing especially aggressive increases," a note to clients by Nomura Securities reads. "SanDisk’s NAND used in enterprise SSDs is cited as potentially rising by more than 100% quarter over quarter in the March period."

Nomura Securities, which is among the prominent financial analyst firms with good contacts in the high-tech industry, attributes plans of memory suppliers to increase prices of enterprise-grade 3D NAND both to short-term shortages and to mid-term growth of demand driven by AI in general and changes to AI storage in particular.

Nomura names Nvidia's Inference Context Memory Storage Platform (ICMSP) — which is based on the BlueField-4 DPU equipped with a 512 GB SSD that carries KV cache — among the demand drivers for enterprise storage this year. Every compute tray in the VR NVL144 rack is equipped with a BlueField-4 data processing unit with a 512 GB drive, making it 18 DPUs with 9.216 TB of 3D NAND per rack. Assuming that Nvidia ships 50,000 VR NVL144 racks per annum, the company will have to get roughly 0.439 EB of 3D NAND somewhere. Its partners supplying their versions of VR NVL144 racks with BlueField-4 DPUs will also increase their consumption of 3D NAND memory this year with the Vera Rubin platform.

While Nvidia's ICMSP can consume around an exabyte of 3D NAND per annum in 2026 ~ 2027 in the best case scenario, it cannot really be a reason for 3D NAND price doubling overnight, as the industry produces over 800 EB of NAND every year. Meanwhile, we still do not know how much 3D NAND a typical VR NVL144 machine carries, so we cannot estimate storage demands for Rubin-based platforms in general.

Nonetheless, as demand for AI systems for storage is skyrocketing in general, they will inevitably drive up demand, and once it outpaces supply, prices will get higher, which is exactly what we are seeing today.

Micron this week announced that it would formally break ground on its fab site in Onondaga County, New York, on January 16. When fully built, the new site will house four fab modules and will cost around $100 billion in total. All four fab phases are scheduled to be completed by 2041, according to the company. The site will be an instrumental part of Micron's plan to build 40% of its DRAM output in the U.S. by the 2040s, up from virtually 0% today.

Five years of reviews and approvals

Micron's fab complex near Clay, New York, will be the largest semiconductor production facility in the state, as well as one of the largest fab complexes in the U.S., which will also outpace the company's site in Idaho when fully operational. In addition, $100 billion represents the largest private investment in the state ever, and one of the most expensive semiconductor manufacturing operations in America.

The groundbreaking ceremony to be held next Friday follows rigorous environmental review and necessary permit approvals, which has taken Micron around five years, something that delayed the whole project by around half a decade. Surprisingly, the groundbreaking ceremony precedes ground preparation, which is a rather unique situation. Normally, groundbreaking follows ground preparation, not preceding it. Yet, ground preparation will start more or less in-line with the schedule that the company outlined in 2025.

Micron's Environmental Impact Statement (EIS) filing, published in November 2025, indicates that Fab 1 site preparation was set to start in late 2025, but was obviously delayed by several weeks. The construction of the first facility is now set to begin in late 2026, and will run through Q2 2028. Given that equipping a fab typically takes nine to 24 months (depending on how you count), Micron expects the fab to start operations as early as Q1 2029. However, it will still take some time before the fab is fully equipped and ramped, so expect tangible DRAM output from Micron's New York Fab 1 by 2030, around five years later than originally planned.

The same documents schedule Fab 2 to break ground in the second half of 2028, Fab 3 in the second half of 2033, and Fab 4 in the first half of 2039. As a result, Micron's fab site near Clay, New York, will reach its full build-out and volume production by 2045, again, roughly five years behind the original timeline.

A long road ahead

Micron's new campus in New York will manufacture DRAM using advanced process technologies and is ultimately planned to feature four fabs with four cleanrooms of 600,000 square feet (55,700 m²) each, constructed in four major build-out phases.

To put the 600,000 square feet number into context, GlobalFoundries Fab 8, located in Malta, New York, has a cleanroom space of approximately 460,000 square feet (though this is set to expand). The initial fab will cost around $20 billion, with successors expected to cost more, as Micron adopts more Low-NA EUV tools (priced around $235 million per unit) and eventually High-NA EUV tools (circa $400 million per unit) for its process technologies.

The New York complex will complement Micron's new site near Boise, Idaho. Last year, construction of the first new fab in Idaho (ID1) was completed, and the facility is now projected to begin wafer output in the second half of 2027. The company is also hard at work in its efforts to speed up the completion of its fab ID2, which will be built adjacent to ID1, benefiting from shared infrastructure and R&D co-location. It is projected that ID2 will start mass production of DRAM ahead of New York's Fab 1, though no further details are known.

Micron's wafer fabrication facilities near Boise, Idaho, will be adjacent to the company's R&D center, so will adopt the latest process technologies and will benefit from short feedback loops between the fab's process-integration teams and R&D personnel nearby. Such close collaboration will likely enable faster time-to-yield, which will improve Micron's profitability.

The close collaboration between process-integration and R&D teams will be particularly instrumental given Micron's current focus on high-capacity enterprise-grade DDR5 for servers and high-bandwidth memory (HBM) for AI accelerators. Both types of products tend to consume large DRAM dies, so rapid yield improvement is particularly important for these kinds of applications, as larger DRAM dies are expensive to make.

The grand plan

Right now, Micron has five wafer production facilities globally: two 3D NAND fabs in Singapore, a DRAM fab in Japan near Hiroshima, and two DRAM fabs in Taiwan (near Taichung and near Taoyuan). In addition, the company has an HBM packaging facility in Singapore, plans to build another fab module in Japan, as well as an HBM assembly plant in the U.S.

Given that the HBM packaging facility in Virginia is expected to come online after Micron ramps up production of HBM memory devices in Idaho, expect it to begin assembling HBM5 or HBM6 stacks towards the end of the decade.

Micron's grand designs include building 40% of its DRAM output in the U.S. by sometime in the 2040s. To achieve this, Micron plans to invest around $150 billion in six fab modules in America through 2045, as well as spending an additional $50 billion on R&D over the same period. However, it is unclear whether $50 billion will be spent exclusively in the U.S. (which will be a major boost for the American semiconductor industry) or whether it will be spread across Micron's R&D facilities across the world.

In any case, Micron's groundbreaking ceremony in New York next week will mark a key landmark in the company's expansion in the U.S. as well as a major milestone in the broad return of DRAM production to America.

Micron just announced the 3610 SSD, which offers PCIe 5.0 speeds with the higher density of Quad-Level Cell (QLC) chips. According to the company’s press release, this chip uses its G9 NAND that lets it achieve competitive PCIe 5.0 performance while offering more storage space in the same footprint. Because of this, Micron says that this is the first SSD in the world to offer 4TB in a compact single-side M.2 2230 form factor, allowing manufacturers to pack in so much more memory in thin-and-light laptops and handheld devices. Aside from the greater storage density, it’s also touted to have 43% better performance per watt for better power efficiency and battery life.

“The 3610 SSD combines cutting-edge PCIe Gen5 technology, Micron’s most-advanced G9 QLC NAND, and a sleek, single-sided design to deliver premium performance, capacity, and power efficiency,” Micron Mobile and Client Business Unit senior vice president Mark Montierth said. “The 3610 will enable ultra-thin devices that meet the growing demands of on-device AI, immersive streaming, and performance-intensive workloads.”

The memory and storage chip maker has previously used G9 TLC NAND on its high-end 4600 PCIe 5.0 NVMe client SSDs, which deliver a blistering 2.1M IOPS random read and write speeds, and up to 14,500 MB/s and 12,000 MB/s sequential read and write speeds in a 2280 form factor. While these are the best speeds that you can get from the company, it’s only available in 512GB, 1TB, 2TB, and 4TB capacities. While the brand-new 3610 SSD offers relatively lower speeds, Micron says that they’re still good enough for AI applications, capable of loading a 20-billion-parameter model in under three seconds.

More importantly, using QLC technology on the 3610 SSD means that Micron can cram more chips in a single wafer, cutting production costs and making PCIe 5.0 SSDs more accessible. And even though the denser design of this chip means that it likely runs hotter than previous generations, it comes with host-controlled thermal management, allowing it to run under for extended periods without compromising reliability.

Even though the company markets this for productivity devices and AI applications, handheld gaming enthusiasts will likely be excited for this chip to hit store shelves, too, as it effectively doubles the largest available M.2 2230 SSD on the market. This means that users can install several AAA titles on their devices without having to worry about running out of space. We don’t have pricing and availability information for these chips yet, especially as they’re still under OEM evaluation. Furthermore, we hope that this technology alleviates the ongoing storage crisis a bit, especially as it allows Micron to eke out larger storage capacity from the same wafer size.

Micron has secured another major vote of confidence from the Taiwanese government, winning approval for an additional NT$4.7 billion (approximately $149 million) in subsidies to expand HBM research and development in Taiwan. Combined with an earlier grant awarded in 2021, the total public support now approaches NT$10 billion, or roughly $318 million, making Micron the largest single recipient of Taiwan’s flagship industrial R&D subsidies to date.

The funding, approved by Taiwan’s Ministry of Economic Affairs under its A+ Corporate Innovation and R&D Enhancement program, supports a three-year project running from November 2025 through October 2028. Micron’s total budget for the effort is NT$11.75 billion, with the company covering close to 60% of the cost itself.

The goal is to develop and industrialize leading-edge, high-performance, and HBM technologies in Taiwan at a time when HBM has become one of the most strategically constrained components in the global semiconductor supply chain, driven by surging demand from AI accelerators, data center GPUs, and high-performance computing systems.

HBM as strategic infrastructure

HBM has shifted from a niche technology used in a handful of HPC accelerators into a foundational element of modern AI hardware. Unlike conventional DDR or GDDR memory, HBM stacks multiple DRAM dies vertically and connects them through an ultra-wide interface, delivering orders of magnitude more bandwidth per watt.

Current HBM3E stacks already provide several terabytes per second of bandwidth, feeding GPUs such as Nvidia’s H200 and AMD’s MI300X without becoming a performance bottleneck. Next-gen HBM4 pushes this further by doubling the interface width to 2048 bits and supporting taller stacks with higher-density dies. In doing so, HBM4-class memory enables larger models, faster training, and more efficient inference without relying solely on brute-force compute scaling.

This, unfortunately, has also turned HBM into a choke point. AI accelerators cannot ship without it, and the ability to produce advanced HBM at scale now directly limits how many high-end GPUs can reach the market. As a result, memory suppliers have found themselves graduating from being interchangeable commodity vendors to fully-fledged semiconductor industry behemoths whose roadmaps influence the entire AI hardware ecosystem.

That explains why governments are increasingly willing to subsidize HBM development, and Taiwan’s Ministry of Economic Affairs has been explicit that memory is the missing pillar in its semiconductor ecosystem. The island already dominates advanced logic manufacturing and chip design, but has historically relied on foreign suppliers for cutting-edge memory technology. Supporting Micron’s HBM R&D is a way to anchor that capability locally.

Micron’s position

Micron is the smallest of the three major HBM suppliers by volume, behind SK hynix and Samsung, but it has rapidly closed the tech gap over the past two product generations. Micron’s HBM3E has already been qualified by major accelerator vendors, and the company has publicly stated that its HBM capacity for 2026 is fully booked. The company recently made headlines when it axed its Crucial consumer business to enable the company to focus more on producing HBM and storage devices to feed the AI beast.

SK hynix, meanwhile, currently holds a dominant share of the HBM market and has reportedly committed much of its near-term output to Nvidia, while Samsung is investing aggressively to regain momentum, pushing 12-layer HBM3E and preparing for HBM4 transitions. In that environment, Micron’s ability to accelerate development, improve yields, and bring new stacks to volume production earlier than rivals could materially affect market share.

Taiwan also offers Micron more than just money. The subsidy requires R&D to be conducted locally and encourages collaboration with Taiwanese companies, particularly in equipment, materials, and advanced packaging. That’s key because HBM development is not just about DRAM cell design but also involves through-silicon vias, wafer bonding, thermal management, and increasingly complex interposer and advanced packaging technologies.

Taiwan’s semiconductor supply chain is exceptionally strong in these areas. Locating HBM R&D there shortens feedback loops between design, process development, and manufacturing equipment vendors, which can translate into faster iteration cycles and more predictable ramp-ups.

Implications for Taiwan’s semiconductor industry

From Taiwan’s perspective, this deal is about long-term positioning, with the government estimating that Micron’s DRAM and HBM investments could generate more than NT$800 billion in domestic output value and create over 20,000 direct and indirect jobs. Those numbers are ambitious, but they underscore the scale of economic activity tied to advanced memory manufacturing.

More importantly, HBM development reinforces Taiwan’s role as a system-level semiconductor hub rather than a single-node manufacturing center. As AI hardware becomes more tightly integrated across logic, memory, and packaging, geographic clusters that can support all three gain an advantage. Taiwan already hosts the world’s most advanced logic fabs and a dense network of OSAT and materials suppliers. Adding leading-edge memory R&D to that mix strengthens the entire ecosystem.

There are also the obvious geopolitical elements. Memory supply has become a major concern for both the United States and its allies, particularly as AI hardware increasingly underpins economic and military capabilities. Micron is the only major U.S.-headquartered DRAM manufacturer, so supporting its advanced R&D footprint in Taiwan aligns with broader efforts to diversify and secure critical semiconductor supply chains without concentrating all leading-edge development in a single country.

Ultimately, this subsidy reinforces the broader industry consensus that the HBM shortage is not a transient problem that’s going to resolve itself or be resolved through incremental capacity additions. There’s a serious, structural deficit driven by sustained AI demand and increasing technical complexity — moving from HBM3E to HBM4 brings all new architectures and closer integration with advanced packaging — and the only way to solve it is through solid, calculated R&D; government-backed funding can meaningfully influence how quickly the necessary transitions occur.

By offsetting some of the risk and cost, Taiwan is effectively saying that it thinks HBM will remain a bottleneck well into the second half of the decade, and that it’s a bottleneck worth solving.

The competition to calculate digits of Pi was initially an informal pursuit but grew more serious over time. Our server-oriented colleagues at StorageReview have proven that storage performance can make or break a Pi run, setting their latest record at a whopping 314 million digits with a single server that ran for four months.

Calculating Pi quickly became a way to benchmark the floating-point performance of CPUs. As the calculations grew ever larger, however, the task became more complicated, as RAM, I/O architectures, and storage systems came into play. That's a point StorageReview clearly illustrated by achieving a record with a single 2U server over a four-month calculation run.

The said machine is a Dell PowerEdge R7725 unit fitted with two AMD Epyc 192-core chips, for a total of 384 cores, along with 1.5 TB of DDR5 memory, an amount that could probably buy a small country at today's prices. The storage array is where this setup shines, though, with 2.5 petabytes of storage thanks to a 40-drive array of Micron 6550 Ion SSDs at 61.44 TB each.

It's long been the case that calculating Pi to such long extents requires a significant amount of bytes to store intermediate computations. After all, you're dealing with factors that are trillions of digits long. Past approaches, such as Google's 100-trillion record in 2022, used cloud server instances, and Linus Media Group and Kioxia's 300-trillion-digit run earlier this year used a Weka cluster with shared storage. But StorageReview opted to prove a point by using plain ol' simple fast local SSDs.

It's worth noting that one key factor enabling the 314-trillion-digit run is that, unlike the previous generation, the 17th-generation Dell servers used don't have a PCIe switch in their storage backplane; instead, they use a direct connection to the CPUs' PCIe lanes. With 40 bays, that works out to 2 to 4 lanes per SSD, but that still worked out to a meaty 280 GB/s of read/write performance, much higher figures than StorageReview's own past experiments.

There were additional relevant optimizations as well. The team tweaked the machine's scratch array for the patterns generated by the y-cruncher software at large digit counts. It also changed the server's standard air-cooling configuration to a CoolIT AHx10 setup, resulting in higher steady-state load clocks for the Epyc chips.

The power consumption was only 1,600W, a high number on its own but actually a pretty impressive figure as far as efficiency is concerned. Last but not least, the OS was changed from Windows Server to Ubuntu 24.04.2, a simple switch that resulted in better I/O performance on its own. We can't help but wonder if using the latest Windows Server release with native NVMe support would have been comparable. If you're curious about more details, go ahead and read the entirety of StorageReview's write-up.

As we detailed in October, the memory and storage markets were expected to face significant supply constraints. In the months following, DDR5 prices have skyrocketed. Kits that had sold comfortably below $100 months earlier were surging into the hundreds by early December. CyberPowerPC, one of the largest system builders in North America, warned in November that contract DRAM prices had jumped 500% since early October, while another report indicated that they had risen 171.8% year over year.

The disruption is being driven not by demand from gamers or device makers, but by artificial intelligence. Specifically, by the way hyperscalers are soaking up wafer starts and advanced packaging lines for high-bandwidth memory (HBM) used in AI accelerators.

The consequence is that anyone or anything that’s not part of that ecosystem — PC builders, laptop OEMs, and even phone makers — is fighting over the scraps of a shrinking pool of commodity DRAM. And with new fabs still years from coming online, the shortage is expected to last well into the second half of the decade.

RAM kits up 2-4x in a quarter

The most visible impact can be seen with retailers. A Corsair Vengeance DDR5-6000 32GB (2x16GB) cost $134.99 in September before reaching more than $420 in early December. G.Skill, TeamGroup, and Kingston all adjusted channel pricing by double digits across Q3, citing tightening availability.

That translated to a whopping 2-4x price swing for enthusiasts buying RAM, depending on capacity and bin. The G. Skill Trident Z5 Neo RGB DDR5-6000, our tried-and-tested best RAM for gaming, is now only available via third-party sellers through Amazon, with 64GB kits attracting prices beyond $500, with one seller listing them for a whopping $881.87 as of December 18.

Suppliers and distributors have sharply tightened allocation of DDR5 memory, with some channel partners reporting severely limited quotes and rollovers on orders as capacity is diverted to AI-driven demand. Reports from Taiwan and broader market tracking show memory modules selling out or being bundled to secure placement, indicating that mainstream buyers are being deprioritized.

That squeeze quickly filtered into GPUs, where memory is a major cost driver. AMD board partners raised card prices by around $10 per 8GB of VRAM starting in November. A rumor suggests AMD could increase Radeon RX graphics card prices with 8 GB models up by about $20 and 16 GB models up by about $40 in response to climbing GDDR6 spot prices and memory costs. SSD pricing has also reversed direction. 2TB Gen 4 NVMe drives that had been available for $80 in the summer were back at $130 by November. Contract pricing on NAND rose 60% in November, and module-level spot prices followed.

Framework was forced to increase its pricing on the DDR5 memory configurable in Framework Laptop DIY Edition orders by 50% in response to “substantially higher costs” they are facing from suppliers and distributors. Meanwhile, Dell and HP have both flagged component pricing, with HP’s CEO stating that memory costs in particular were affecting margin on consumer systems and Dell COO Jeff Clarke saying he’s “never seen memory-chip costs rise this fast.” Raspberry Pi also raised prices on its 4GB and 8GB boards, citing supply constraints on LPDDR4X.

Starving the market

All this is not being caused by insufficient demand for DDR5, but by wafer and packaging capacity being redirected to high-margin, high-volume AI parts. High Bandwidth Memory (HBM) is the main pressure point.

HBM differs from conventional DRAM in both structure and cost. Instead of planar dies mounted on PCBs, HBM stacks multiple DRAM dies vertically, linked with through-silicon vias (TSVs), and mounts them on an interposer alongside compute logic. These stacks offer enormous bandwidth and proximity advantages for AI accelerators, but they are incredibly expensive in terms of materials, tooling requirements, and especially wafer area.

Each gigabyte of HBM consumes roughly three times the wafer capacity of DDR5. That reflects both yield loss from stacking and the fact that many DRAM dies in HBM stacks are smaller or binned lower than equivalent RAM sticks. The TSV process and wafer thinning introduce additional steps that lengthen production cycles, leading to a catch-22 situation that, even when yields are strong, means the vertical integration of HBM requires advanced packaging lines that remain globally scarce.

SK hynix, the largest supplier of HBM to Nvidia, has told investors that its advanced packaging lines are at capacity through 2026. Micron, which supplies HBM3E to Nvidia and other U.S. clients, is in a similar position. Samsung has HBM capacity reserved through its Foundry and Memory business lines for tier-1 cloud clients. These lines are not interchangeable with conventional DRAM; tools, masks, and equipment for HBM production occupy space that would otherwise produce DDR5 or LPDDR5.

With wafer starts flat and packaging lines locked, every wafer pushed into HBM removes capacity from commodity DRAM and NAND. And the volume committed to AI is enormous.

The Stargate effect

In July, OpenAI and Microsoft finalized plans for Project Stargate, a multi-site hyperscale AI infrastructure program, with Samsung and SK hynix together committing to up to 900,000 DRAM wafer starts per month to support the buildout “at an accelerated capacity,” according to OpenAI.

That deal alone represents roughly 35-40% of global DRAM wafer capacity. The wafers will be used not just for HBM stacks, but for LPDDR and ECC DRAM used in adjacent server memory. Nvidia has its own multi-year agreements in place, reportedly accounting for the majority of SK hynix's HBM output through 2026. These allocations are inflexible, with contracts fixed, volumes tiered, and, in many cases, wafers fronted at favorable prices in exchange for capacity guarantees.

Naturally, memory vendors are reaping the rewards. Micron posted a record $11.3 billion quarter in Q4 2025, driven by HBM and enterprise DRAM margins. It subsequently announced plans to exit the Crucial consumer brand by early 2026. Executives stated that winding down Crucial would free up wafer supply for strategic accounts. “The AI-driven growth in the data center has led to a surge in demand for memory and storage. Micron has made the difficult decision to exit the Crucial consumer business... to improve supply and support for our larger, strategic customers in faster-growing segments,” said Sumit Sadana, EVP and Chief Business Officer.

Meanwhile, Samsung has raised its memory chip prices by up to 60% since September, driven almost entirely by the high demand for building new AI-focused data centers.

No new fabs until 2027

Memory makers are responding to surging demand by building new fabs, but the leadtime on greenfield facilities is long, and — of course — virtually all capex is going to go to HBM lines first, because that’s where the money is. Among the most notable investments is Micron’s $9.6 billion Hiroshima HBM facility, announced in partnership with the Japanese government. Construction of this fab is expected to begin around May 2026, with its first output expected in 2028.

Samsung is also committing billions in investments to new DRAM capacity in Pyeongtaek and Taylor, Texas. These sites will include HBM packaging and DRAM wafer lines, but company executives have cautioned that HBM and high-margin enterprise DRAM will receive priority through 2027. The company recently accelerated Phase 4 of its Pyeongtaek expansion in a renewed effort to reclaim leadership in the AI memory space. As for SK hynix, it’s expanding in Icheon — where it was the first memory maker to assemble ASML’s High-NA EUV lithography system — and Cheongju, with new DRAM output slated for 2026-2027.

Unfortunately, there’s no sign of the DRAM supply shortfall easing up before 2027. TrendForce has cautioned time and time again that capacity growth is limited relative to demand as AI and server requirements absorb a disproportionate share of wafer starts and production resources, and its pricing outlook shows DRAM contract rates continuing to rise through 2026 with constrained supply conditions. A leaked SK hynix internal analysis forecasts PC DRAM supply trailing demand until at least late 2028, and general industry consensus is that meaningful relief for DDR5 and LPDDR5 supply — at prices suitable for consumer SKUs — will not come until 2028 or 2029 at the earliest.

The situation is similar for NAND, with wafer investment having lagged since the 2022 price collapse. Most new NAND lines being built now are intended for enterprise SSDs or embedded memory for AI accelerators; client SSDs will see higher costs and tighter supply through 2026.

Consumers are now an afterthought

The effects of this reallocation are already locked into the next generation of consumer hardware, because memory decisions are made years in advance. Laptop platforms shipping in 2026 and 2027 are being finalized now, at a moment when DRAM and NAND supply are both constrained and volatile. That will have consequences that go beyond pricing.

Memory configurations that require large, predictable allocations of DRAM are riskier in a market where suppliers are prioritizing AI contracts and spot pricing can move sharply month to month. These conditions favor fewer SKUs and longer reuse of validated configurations rather than aggressive spec increases. Meanwhile, DDR4, which was expected to fade out quickly after DDR5 adoption ramped, is now likely to persist far longer in entry-level and midrange systems simply because its supply chain is more stable.

GPUs are in a similar bind. GDDR6 and GDDR6X, while not interchangeable with HBM, compete for wafer capacity and backend resources at the same suppliers. That makes large VRAM increases expensive at exactly the moment when software requirements are rising. This won’t necessarily mean fewer GPUs, but it could lead to slower movement at the top end of memory configurations, with vendors prioritizing yield and availability over aggressive capacity scaling.

NAND is under comparable pressure as investment in new client-focused capacity slowed down after oversupply and subsequent pricing collapse in 2022. What capacity is coming online is disproportionately aimed at enterprise SSDs and embedded storage tied to accelerators, where margins are higher, and contracts are longer. That leaves consumer SSDs exposed to price swings and supply tightening, particularly at higher capacities, even as PCIe generations continue to advance.

The problem is that none of these pressures are transient shocks that can clear in a quarter or two. The fabs that would meaningfully expand DRAM and NAND supply are not scheduled to come online until 2027 at the earliest, and even then, priority will remain with HBM and enterprise products. Consumer markets are now an afterthought among memory makers and, given the current state of AI, it’s difficult to see that changing.

Micron’s plans to shutter its Crucial consumer business next year did not stop the brand from appearing on the show floor at Delhi Comic Con over the weekend. A visitor took to X to share images of the Micron and Crucial branded booth, only days after the company told investors it would wind down consumer products by February 2026.

Micron’s presence was likely planned months in advance in collaboration with Indian partners and doesn’t represent a sudden U-turn on the decision to shutter its consumer business. Neither Micron nor Crucial is listed among the event’s headline exhibitors, and while Micron’s presence might seem unusual following last week’s announcement, it’s entirely understandable that the company wants to shift existing inventory ahead of February as the company reallocates its wafer supply to HBM and enterprise DRAM.

Ultimately, distributors and retailers still have stock to move, and partner booths at events and gaming shows remain one of the most effective ways to reach buyers in India’s growing PC market. Micron’s timeline gives those partners ample time to clear their shelves of soon-to-be-retired stock.

Micron’s December 3 announcement described a consumer exit shaped by AI demand rather than short-term performance in the retail channel. The company said it would retire Crucial as a consumer-facing business and concentrate investment on HBM memory lines feeding enterprise customers. The shift is intended to support advanced data-center products during a period of constrained supply and rising AI requirements.

HBM’s engineering is nothing like the consumer memory Micron is stepping away from. The technology stacks multiple dies into a single package and links them through dense vertical interconnects, producing far higher bandwidth per watt than conventional DDR and turning memory into a performance enabler rather than a bottleneck.

That is important at a time when hyperscalers are racing to stand up ever-larger AI clusters and where each new generation of GPUs pushes memory throughput harder than capacity. For Micron, the growth prospects and margins attached to HBM outstrip anything available in the price-sensitive retail channel, and the company’s decision places its wafer supply squarely behind the memory technologies that now define competitiveness in AI infrastructure.

In the meantime, consumer inventory remains, and resellers need to continue to promote it to shift inventory. The Delhi Comic Con booth is simply a reflection of that fact; a snapshot of a brand still active in public even as its parent company prepares to abandon consumers and concentrate on more lucrative memory technologies.

In keeping with the spirit of times, Micron on Wednesday announced plans to wind down its Crucial consumer business worldwide by the end of February 2026. The company is reallocating its output and investments to enterprise-grade DRAM and SSD products amid growing demand from the AI sector.

Micron will continue shipping Crucial-badged consumer products through retailers, online stores, and distributors until the end of its fiscal second quarter, which concludes in late February 2026. After that point, Micron will no longer supply the consumer channel with products under the Crucial name, but will continue to ship its Micron-branded enterprise portfolio, which will remain available through commercial and server-focused partners.

After Micron ceases to ship its Crucial devices, it will continue honoring warranty obligations and technical support for existing Crucial products. Customers who already own Crucial-branded memory modules, SSDs, and other products will continue to receive service coverage well after shipments stop, so the decision will not leave installed hardware unsupported.

As expected, Micron is abandoning its consumer business due to reallocation of its 3D NAND and DRAM output and production capacity to enterprise-grade SSDs, high-bandwidth memory (HBM) for AI accelerators, and server-grade memory modules.

"The AI-driven growth in the data center has led to a surge in demand for memory and storage," said Sumit Sadana, EVP and Chief Business Officer at Micron Technology. "Micron has made the difficult decision to exit the Crucial consumer business in order to improve supply and support for our larger, strategic customers in faster-growing segments."

Micron established its Crucial brand some 29 years ago, in 1996, when the enthusiast-grade hardware market began its rapid growth. Over time, Crucial got particularly successful in retail, where its name became synonymous "with technical leadership, quality and reliability," as Micron puts it. However, the current market situation is by far not favorable for these types of products, so instead of shrinking its Crucial portfolio, the company decided to wind it down entirely, albeit without selling off the Crucial brand (at least for now).

There are several reasons behind Micron's decision.

Firstly, client memory modules and SSDs sit at the lowest-margin end of Micron's portfolio as they compete in highly volatile, price-competitive, and promotion-driven market. Even though the Crucial and Ballistix brands still matter, they are squeezed between high-end enthusiast brands and low-end consumer brands, which makes their evolution difficult. By contrast, data center and enterprise products lock in long-term contracts, higher ASPs, and more predictable demand.

Secondly, the supply environment has changed permanently. AI infrastructure requires every single wafer with memory it can consume, something that has never happened with any industry megatrend previously. This means that every wafer Micron assigns to consumer parts is a wafer not going to a hyperscaler or enterprise contract. As a result, keeping a consumer line would directly limit Micron's ability to fulfill orders from its largest customers, which is a risk for profits and strategic relationships.

Thirdly, even a small consumer business would still require a minimum viable supply chain, including product development, firmware validation, compliance testing, sales teams, retail relationships, and global warranty operations. Such fixed costs barely shrink when volume shrinks, so a reduced consumer business would still burn resources while losing the economies of scale that make the segment viable.

As a result, it strategically makes far more sense to wind down consumer operations entirely and free production capacity, R&D, and product engineering resources for premium products like HBM4/HBM4E/C-HBM4E, enterprise drives, and high-density server memory modules.

Micron indicated it will try to reduce the impact of the decision on employees through internal reassignments into existing vacancies elsewhere in the company.

The ongoing structural change of the DRAM market caused by the shift of manufacturing capacities to production of high bandwidth memory (HBM) for AI accelerators has already caused a massive price hike of commodity DDR and LPDDR memory — but the worst is yet to come.

According to the general manager of Chinese memory giant TeamGroup, contract prices of DRAM and NAND products have almost doubled recently. Supply of commodity memory is set to worsen in early 2026, and normalization is unlikely before 2027 – 2028 when more production capacity emerges, reports DigiTimes.

December contract prices of some categories of DRAM and 3D NAND increased 80% to 100% month-on-month, according to Gerry Chen, general manager of TeamGroup, a prominent maker of memory modules, solid-state drives, and products based on 3D NAND. Spot prices tell a similar story. A 16Gb DDR5 chip was priced at $6.84 on average at DRAMeXchange on September 20. On November 19 average spot price was $24.83, but on December 1 average spot price of a 16 Gb DDR5 IC increased to $27.2 (session low was $19, session high was $37).

Essentially, memory alone for a 16 GB memory module costs around $217.6. A PCB, assembly, and testing, additional parts like PMIC will add $8 – $10, so a 16 GB memory module now costs $225 – $228 without manufacturer premiums, logistics, and taxes.

Chen expects availability of DRAM and NAND to worsen in the first and second quarters of 2026 once distribution stockpiles are exhausted. At that point, he cautions, obtaining allocation could become difficult regardless of willingness to pay. In his view, relief would not come quickly: he projects the current shortages to extend into late 2027 and potentially beyond.

The reason for shortages of commodity memory is well known: DRAM makers reallocate their production capacities to HBM (which uses larger DRAM dies than commodity types of memory) that is consumed by AI accelerators, like Nvidia's B300 or custom accelerators by large cloud service providers, such as AWS, Google, and Microsoft. These companies tend to book supply years in advance, so at some point, DRAM makers will not have enough capacity to meet demand for commodity DRAMs.

Building a new greenfield fab takes at least three years, so even if companies like Micron, Samsung, or SK hynix made a decision to build a memory fab today, it would come online in late 2028 at the earliest and would be fully ramped only sometime in 2029.

When it comes to NAND, NAND suppliers also prioritize large customers, which happen to be makers of AI servers. Chen does not expect capacity to swing back to PCs, smartphones, and other consumer devices in 2026, which will affect the prices of these devices.

The effects are clear to see. Enthusiasts are seeing RAM prices for custom-built PCs increase by orders of magnitude week on week, with 64GB of DDR5 RAM now costing more than a PS5 in some cases. This week's Black Friday and Cyber Monday RAM deals might be the last chance to buy RAM before prices skyrocket even further.

Micron is preparing a major expansion of its Hiroshima operations to build a dedicated high-bandwidth memory (HBM) facility, according to a report by Nikkei Asia. The report says the company intends to invest 1.5 trillion yen — US$9.6 billion — in a new plant on its existing site, with construction scheduled to begin in May next year. Shipments would follow around 2028. Japan’s Ministry of Economy, Trade and Industry (METI) is expected to contribute up to 500 billion yen in subsidies to support the project, though neither Micron nor METI has confirmed the report.

HBM has arguably become the most constrained component in the AI supply chain, giving the project some real weight in terms of government subsidies. SK hynix currently leads the market and has committed most of its HBM, DRAM and NAND output to Nvidia through 2026. Samsung is working to catch up with its 12-layer HBM3E stacks, while Micron has pushed hard to grow its own presence through HBM3E supply deals with Nvidia and AMD. TrendForce data shows Micron moving toward roughly a quarter of the HBM market with 20% of shipments as production increases; a dedicated Hiroshima expansion could shift that balance further once it comes online.

Japan has been aggressive in courting this kind of investment, offering substantial government incentives to foreign chipmakers as part of a wider effort to rebuild domestic semiconductor capacity. TSMC’s Kumamoto fabs and the state-backed Rapidus project are already part of this strategy.

Micron itself has been a significant beneficiary. Last year, Micron announced plans to introduce EUV-based DRAM production on the same Hiroshima campus, investing 500 billion yen of its own cash and supported by nearly 200 billion yen in subsidies. The first LPDDR5X memory devices produced on its 1γ process at this facility then began sampling in May of this year.

The scale of the planned plant aligns with expectations for the next generation of AI accelerators. Nvidia and AMD are both shifting towards HBM4 and HBM4E, both of which require tighter process control and higher layer counts. Capacity has been thin throughout the current GPU cycle, with long lead times and allocation limits driven by the mismatch between demand and available wafer starts. If Micron’s new plant reaches volume production in 2028, it will arrive just as those next-generation GPUs are.

For Micron, Hiroshima offers political and financial stability at a moment when both geopolitics and the market cause increasing uncertainty, and Tokyo’s willingness to fund a third of the project removes some of the risk from a multiyear build. The long runway to 2028 also gives Micron a clear path to expand its role

Micron has published the final draft Environmental Impact Statement (EIS) for its fabs near Clay, New York, which reveals the final schedules for construction of four fabs starting late 2025 through 2041. Meanwhile, a report from Syracuse indicates that the company is accelerating its Idaho fabs and reallocating CHIPS Act funding to that facility.

"Micron remains focused on bringing leading-edge memory manufacturing to New York, and we appreciate the strong partnership with federal, state, and local authorities," a Micron statement supplied to Tom's Hardware reads.

According to Micron's official draft EIS document released back in June and the latest draft EIS published in November, the construction phase for the first fab (Fab 1) would start from late 2026 (after a year of preparations that start in late 2025, according to the company's U.S. expansion plan unveiled on July 1, 2025) and will last till the second half of 2028, or early 2029. It usually takes 12 to 24 months to fully equip a fab, depending on various factors; hence, it is reasonable to expect the first fab to start DRAM production sometime in 2030, five years later than initially expected. Yet, Micron believes it can partly equip its Fab 1 in three quarters and begin operations in Q1 2029.

The same environmental documentation pins Fab 2's construction start to the second half of 2028, Fab 3's construction start to the second half of 2033, and Fab 4's construction start to the first half of 2039. This way, the Micron Clay campus will be fully built and ramped to full production by 2045, which is five years behind schedule.

"Micron would mobilize for initial site preparation for the Proposed Project beginning in the fourth quarter of 2025, with the first two DRAM manufacturing facilities (Fabs 1 and 2) estimated to be operational by 2029 and 2030, respectively, and the remaining fabs (Fabs 3 and 4) estimated to be operational by 2035 and 2041," a statement by Micron from the EIS submitted in June reads.

Micron reportedly acknowledged an amendment to its $6.1 billion CHIPS Act funding agreement with the U.S. Department of Commerce, as the company is reportedly bringing forward its ID2 facility in Idaho. The two Idaho facilities — one existing and one newly planned — will be completed ahead of those in Clay, which means that there is a strategic reshuffling of project priorities in place.

As part of the alleged realignment, Micron redirected about $1.2 billion of its federal grant from New York to Idaho, reducing Clay's share from $4.6 billion to $3.4 billion. The company reportedly indicated that the update was consistent with evolving project requirements under the federal agreement. Local authorities, including Onondaga County Executive Ryan McMahon, reportedly attributed the delay of Micron's New York campus to widespread labor shortages and the longer construction cycles that have become.

The realignment of the projects in America probably does not affect Micron's ultimate goal to produce 40% of its DRAM output in the U.S. as the company prioritizes one project after another, not delaying new fabs altogether. Meanwhile, prioritization of the fab ID2 will have a positive effect on Micron's output of HBM memory in the U.S., as the company also intends to build an advanced packaging facility for HBM and other types of memory that require stacking and advanced packaging in Idaho.

The DRAM supply chain is choking, and server memory is taking the first hit. According to DigiTimes, major U.S. and Chinese hyperscalers are now receiving just 70% of the server DRAM they order. That’s despite agreeing to contract price increases of up to 50% for Q4, well above the 30% hike many buyers had budgeted for earlier this year.

Naturally, AI sits at the core of all this. While it’s HBM that gets the headlines, demand for conventional DDR5 RDIMMs is also outpacing supply, particularly at advanced nodes where Samsung and SK hynix have diverted capacity toward parts bound for AI acceleration. Samsung’s recent pricing adjustments confirm the reprioritization, with the company having raised server SSD prices by up to 35% and RDIMM contract rates by as much as 50%, citing sustained demand from enterprise and cloud customers.

What’s left is a market where even the largest buyers can’t secure enough memory. Spot prices have surged since late September, and several top-tier suppliers are reportedly refusing to quote for October allocations. DDR5 16 GB modules that traded at $7 to $8 last month are now hovering around $13, with availability tightening further into November. Module makers are bracing for out-of-stock situations by the end of the quarter.

The rest of the market fares worse. Channel players and smaller OEMs are seeing order fulfillment rates closer to 35% to 40%. With hyperscalers locking in fixed allocations, lower-priority customers are pushed to the spot market or told to wait until capacity opens up in 2026.

Micron warned of this in its most recent earnings call, telling investors that DRAM is a “tight industry” and that bit supply growth will lag demand through the end of next year. TrendForce also flagged a potential quote freeze across certain modules, as suppliers shift to day-to-day pricing in China and avoid locking themselves into bad deals.

This is causing retail DDR5 prices to creep upward, with no sign of stabilization before year’s end. DDR4, meanwhile, is in slow decline. China's Nanya Technology recently said standard DDR4 makes up just 20% of the total DRAM market, and it’s no longer being prioritized for volume production. Unless demand unexpectedly cools or yields improve sharply, DRAM allocation for everyone outside the top buyers will be constrained into 2026.

Micron is reportedly preparing to halt sales of server memory chips to data centers in mainland China, after its business there failed to recover from a 2023 cybersecurity ban. The move, reported by Reuters citing unnamed internal sources, has not been confirmed by Micron, but would mark a significant retrenchment from the world’s fastest-growing data center market.

According to the report, citing people familiar with the matter, Micron intends to cease shipments of its DRAM and other server-grade memory products to Chinese data centers, while continuing to supply the country’s automotive and smartphone sectors. The company would also continue to serve certain Chinese clients that operate data centers abroad, including Lenovo, the sources said. Micron declined to comment on the rumors but did acknowledge that the 2023 ban had impacted the division and that it “abides by applicable regulations where it does business.”

If true, the decision would highlight how little ground Micron has regained since Beijing’s 2023 ban on its products in “critical information infrastructure” — a policy the Cyberspace Administration of China justified on national security grounds. The ban effectively locked Micron out of many state-backed data center projects, forcing domestic and Korean suppliers to fill the void. At the time, the ruling was widely seen as a countermeasure against US export restrictions on advanced chips.

If the reports are true, Micron’s withdrawal from China’s data-center segment may allow Samsung and SK Hynix to further solidify their position in the Chinese server DRAM market, but recent US restrictions could make that difficult. Local players such as YMTC and CXMT have also expanded production under Beijing’s push for semiconductor self-sufficiency, though their technologies still lag in performance and yield. China’s data center investment linked to artificial intelligence surged to roughly 24.7 billion yuan ($3.4 billion) last year, according to Reuters.

Mainland China accounted for around 12% of Micron’s revenue last fiscal year, and most of its recent growth has come from AI infrastructure demand elsewhere. Micron has recently broken revenue records due largely in part due to a rebound in memory pricing and booming demand for HBM used in AI accelerators.

US export controls have already restricted Nvidia, Intel, and AMD from selling their most advanced processors into China, prompting each to develop scaled-back local variants. Micron’s apparent withdrawal would remove one more Western supplier from China’s high-end compute ecosystem, leaving the field increasingly dominated by South Korean and domestic vendors.

Last week, U.S. Commerce Secretary Howard Lutnick attempted to urge Taiwan to agree to a 50% - 50% arrangement, under which chips used in devices for the American market would be produced equally in both countries. The ultimate plan of the current administration is to boost domestic semiconductor production to more than 40% by the end of President Donald Trump's current term.

As observed by officials in Taiwan and analysts, the proposal lacks a workable definition, overstates Taiwan's influence on supply constraints, overlooks the current state of the U.S. semiconductor industry, and ignores peculiarities of the global supply chain.

The proposal

Lutnick said in an interview that the U.S. government has held preliminary talks with Taipei about rebalancing chip output to ensure that half of America's consumption comes from domestic facilities. Even if successful, he acknowledged, the country would remain reliant on Taiwan but would gain the ability to act independently if a crisis arises. Lutnick links his proposal to Taiwan's security, suggesting that a stronger U.S. production base would enable America to safeguard the island more easily, as it would have the means to do so, and would not be dependent on chip supply from the country.

He rejects the idea that Taiwan's (or rather TSMC's) advanced logic dominance — the so-called Silicon Shield — inherently deters conflict. To a large degree, his remarks echo Trump's past claims that Taipei benefits from U.S. protection without adequate compensation.

The Trump administration's stance stems from a long-standing concern: Taiwan manufactures more than 90% of the world's most advanced logic chips, which all happen to be developed in the U.S., which is a vulnerability for American companies like Apple, AMD, Broadcom, Intel, or Nvidia, given the island's proximity to China.

The current U.S. government believes that if the U.S. shares the manufacturing load, it can better defend Taiwan because critical components would not be trapped offshore. In addition, the U.S. Government also tied the cooperation to continued defense commitments. Furthermore, the administration has also paired this message with economic pressure. It proposed 100% tariffs on imported semiconductors but offered exemptions to companies investing in U.S. fabs, such as TSMC and Samsung, to encourage them to build capacities in the U.S. In all likelihood, the proposed 100% tariff would hurt smaller manufacturers.

American semiconductor industry today

Lutnick's '50% – 50%' idea focuses on geography instead of capacity. The real issue is not that too many chips are made in Taiwan: it is that the U.S. does not have enough advanced-node capacity or packaging infrastructure to meet its own demand, particularly to make chips equipped for techologies like 5G or AI.

The United States already manufactures a large number of chips domestically — Analog Devices, GlobalFoundries, Texas Instruments, SkyWater, and onsemi produce vast quantities of mature-node semiconductors used in cars, power systems, and industrial gear. These often represent the majority of chips in terms of unit count and revenue. Meanwhile, Intel produces plenty of advanced logic chips in the USA, whereas Samsung Foundry and TSMC aim to significantly expand their advanced fabs in America.

So, the U.S. already makes millions of chips, but lags in cutting-edge logic used in AI accelerators, CPUs, smartphones, and servers. Rebalancing the total chip production 50% – 50% is meaningless if the categories are mixed or not defined: the bottleneck lies in EUV-era logic and advanced packaging, not in chips produced on trailing nodes, which represent the lion's share of all chip supply.

"The '50% – 50%' lacks a workable definition, hindering substantive discussion," wrote Ming-Chi Kuo, an analyst with TF International Securities. "For example, does it refer only to advanced nodes, or also include mature nodes or advanced packaging? Does it apply to chips used domestically within the U.S., or those required by the U.S. government and companies? Without a clear definition, meaningful discussions cannot proceed. This also helps explain why Cheng Li-Chun, Taiwan’s Vice Premier of the Executive Yuan, said there have been no '50% – 50%' discussions with the U.S."

Taiwan views its cooperation with the United States as mutually beneficial, rather than delivering on a fixed quota. TSMC's management has expressed commitment to its U.S. sites but remains cautious about overextending resources abroad, highlighting that complex production chains cannot be duplicated overnight.

For years, the United States has been attempting to reclaim lost ground in leading-edge microelectronics. While Intel continues to produce its latest products on its most advanced nodes in America, its arch-rival AMD has long become a fabless semiconductor designer, and Nvidia has always been one. However, GlobalFoundries has ceased to develop leading-edge process technologies. As a result, Taiwan-based TSMC and UMC have gradually absorbed production of advanced chips, which were developed in the U.S., due to costs and logistical reasons. Since the majority of PCs and smartphones are assembled in Asia, it makes sense to make chips there as well.

Is 50% - 50% possible at all?

Lutnick's 50% - 50% proposal looks bold, but it remains aspirational because the gap between American and Taiwanese capabilities is vast. TSMC alone produces more advanced chips than the rest of the world combined. Catching up would require multiple new fabs, tens of thousands of advanced tools from Europe and the U.S., in addition to tens of thousands of skilled workers that the United States currently lacks.

Industry leaders have repeatedly warned that the U.S. labor pipeline for advanced manufacturing remains limited, which makes constructing news fabs longer and running them difficult.

TSMC's ongoing expansion in the United States already represents the largest foreign semiconductor investment in history. The plan includes six fabs for advanced nodes, two advanced packaging facilities, and one research center. The first facility in Arizona — Fab 21 phase 1 — started mass production in late 2024, while the second — Fab 21 phase 2 — was initially expected to use the N3 process by 2028, but has been accelerated to the second half of 2027 and upgraded to include N2 (and possibly A16) technology at the request of the U.S. government, according to Kuo.

The analyst expects the first three fabs to reach full utilization between 2028 and 2030. TSMC itself says that 30% of its N2/16 capacity will be located in the USA, whereas Kuo suggests that its U.S. output will account for roughly 10% to 15% of the foundry's global capacity by 2030, and once all six phases of Fab 21 are operational around 2032, the share could reach 25% to 30%. By some definitions, this level would already fulfil the intent of producing half of America's advanced-node demand domestically at TSMC's Fab 21 in Arizona alone, not to mention Intel's fabs in Arizona and Ohio as well as Samsung's fab in Texas.

Kuo argues that the real constraint on American self-reliance is not the willingness or unwillingness of chipmakers to invest in U.S. capacities, but the actual semiconductor industry ecosystem that supports chip manufacturing.

The upstream network supplying materials such as ultra-pure photoresists, underfills, and liquid monomer coatings is heavily concentrated in Japan. Companies like JSR, Namics, and Nagase currently ship to Arizona to support TSMC's Fab 21 phase 1, but as capacity grows, they would need to establish local production or logistics centers in America to avoid tariffs and add flexibility. Building such infrastructure will take years and may not be commercially attractive straight away, given the relatively small demand outside Asia as of today.

Neither Intel, nor TSMC, nor Samsung has been able to persuade JSR to build a photoresist or CMP factory outside of Japan, South Korea, Taiwan, or the U.S., where it serves plenty of customers.

However, if GlobalFoundries, Intel, Micron, Samsung, and TSMC build the necessary EUV-based capacity in the U.S., JSR may be more inclined to build its own plant on American soil. At the end of the day, the global photoresist market is expected to grow to $5.3 billion by 2028, and the U.S. may stand to represent a significant share.

This dependence on Japanese materials undercuts the assumption that relocating fabs automatically guarantees security. If geopolitical tensions were to disrupt East Asian trade routes, it is unclear whether Japanese firms could continue supplying chemicals to American customers. Thus, moving chip fabrication to the United States without parallel supply-chain localization would just shift vulnerabilities from one region to another.

The same applies to equipment vendors from Europe and the Netherlands, whose lithography tools remain irreplaceable. Semiconductor resilience depends on the entire global ecosystem: from raw materials to chipmaking equipment and packaging facilities, not just the geographical placement of wafer fabs.

Does it make financial sense?

Perhaps a fundamental question is whether it even makes sense to produce half of chips for the U.S. in America, considering the fact that they are more expensive than chips made in Asia.

From a cost standpoint, producing half of the chips used in the U.S. on domestic soil is inefficient. Even chips made on TSMC's proven N4/N4P/N5/N5P technologies in the U.S. are said to carry a 30% higher markup than the same chips produced in Taiwan, and while companies like AMD, Apple, and Nvidia can absorb that extra cost, not all companies are that rich.

Furthermore, Asian hubs benefit from dense industrial ecosystems that span from raw materials to fab tool suppliers, enabling fast maintenance and low logistics costs. New U.S. fabs must recreate that web from scratch, and their output will take years to match that of long-established facilities abroad.

Overall, end-users in America will have to pay more for chips produced in the U.S. The difference might seem small per component, but it scales significantly across industries. Everything that relies on silicon — cars, medical devices, PCs, smartphones — absorbs a fraction of the added cost, and becomes more expensive. The price inflation is something that remains to be seen, but ultimately, Americans will have to pay for the onshoring of semiconductor production.

Of course, the logic changes when viewed through the lens of security and resilience. The United States consumes roughly 25% - 33% of the world's semiconductor supply. But it manufactures only about 10% - 12%, and its leading-edge capacity is limited. Meanwhile, Taiwan alone accounts for approximately 90% of leading-edge logic output. Any disruption — whether from conflict, blockade, or earthquake — would affect everything from cloud infrastructure of AWS and Microsoft Azure, to defense electronics.

Truth be told, not many sensitive microelectronics are produced outside the U.S., but the economic harm caused by disruptions may be comparable to actual military harm. Therefore, the proposed '50% to 50%' plan may be considered an insurance policy that guarantees the U.S. and its allies' economic and military continuity, if Asian production faltered.

As a bonus, each fab attracts satellite suppliers, boosts local innovation, and rebuilds technical skills that generate far greater downstream value. However, though the immediate financial return looks weak, the long-term industrial payoff may be substantial. Making half of America's chips domestically may be inefficient, but strategically important.

Political symbolism

The implications of Lutnick's proposal extend beyond economics, defense, and supply chains. For the Trump administration, the political symbolism of semiconductor self-reliance is a big deal. Expanding domestic chip production aligns with his economic nationalism and industrial revival, and big announcements by Intel, Samsung, and TSMC enable the government to talk about tangible progress toward that goal.

The proposed total commitment of $165 billion from TSMC, and substantial plans from other chipmakers reinforce that narrative, even if many commitments were made when Joe Biden was in the White House, and full capacity remains years away.

Meanwhile, trade talks between Washington and Taipei continue, and future tariff structures for companies getting chips in Taiwan and supplying them to the U.S. will depend on those negotiations.

Achieving a balance in semiconductor supply will depend on tackling bottlenecks that span across regulators, workforce development, and supplier localization. TSMC's U.S. build-out is already advancing faster than expected, and by the early 2030s, American fabs could meet a significant portion of local demand.

However, transforming the global semiconductor supply chain into a model, equipped with multiple major vertically-integrated semiconductor manufacturing hubs, led by America and Taiwan, would require changes that are outside the U.S. government's control.

What's next?

Micron has confirmed it will partner with TSMC to manufacture the base logic die for its next-generation HBM4E memory, with production targeted for 2027. The announcement, made during the company’s fiscal Q4 earnings call on September 23, adds yet more detail to an already busy roadmap.

Micron is shipping early HBM4 samples at speeds above 11 Gbps per pin, providing up to 2.8TB/s of bandwidth, and it has already locked down most of its 2026 HBM3E supply agreements. But the big takeaway is that Micron will hand TSMC the task of fabricating both standard and custom HBM4E logic dies, opening the door to tailored memory solutions for AI workloads.

The decision also places Micron squarely in the middle of the next wave of AI system design, aligning with previous reporting on HBM roadmaps across Micron, SK hynix, and Samsung, and with earlier analysis of how Micron views HBM4E as a platform for customization.

A semi-configurable subsystem

The industry is already familiar with the HBM cadence: HBM3E today, HBM4 in 2025–2026, and HBM4E around 2027, and each new generation brings higher per-pin data rates and taller stacks. SK hynix has already confirmed 12-Hi HBM4 with a full 2048-bit interface running at 10 GT/s, while Samsung is plotting similar capacities with its own logic processes. Micron is shipping its own HBM4 stacks and claims more than 20% better efficiency than HBM3E.

HBM4E is the extension of that roadmap, but Micron is treating it as something more. The company highlighted that the base die will be fabricated at TSMC, not in-house, and that custom logic-die designs will be offered to customers willing to pay a premium. By opening the base die to customization, Micron is effectively turning HBM into a semi-configurable subsystem. Instead of a one-size-fits-all interface layer, GPU vendors could request additional SRAM, dedicated compression engines, or tuned signal paths.

That approach mirrors what we have seen from SK hynix, which has already described customizable base dies as part of its HBM4 strategy. Given that customized memory is stickier, more profitable, and more important for customers trying to squeeze every watt and every cycle out of an AI accelerator, this is likely to become a lucrative segment of the market.

The importance of AI

DDR4 memory is outdated, but there are plenty of PCs with this type of SDRAM — some of which were built as recently as 2023 — waiting for an upgrade. Due to reports about the end of DDR4 production at leading DRAM makers, pricing skyrocketed in the global market.

That leaves owners of DDR4 systems wondering whether they should upgrade their rigs now, as it was due to vanish from shelves soon. Thankfully, it appears that DDR4's lifespan has been extended, according to multiple industry sources.

The transition to a new type of consumer PC memory usually takes around seven to eight years. The decline of the previous generation DRAM standard usually happens within two to three years of the new standard's release.

Cut-throat competition between memory manufacturers means that they are keen to wind down production of previous generation products, to cut down costs. It also means that companies don't have to use aging technology with the latest nodes. Therefore, there will be no DDR4 and LPDDR4 devices made on 6th Generation 10nm-class nodes, such as 1c/1γ (1-gamma).

As a result, while there are plenty of entry-level platforms that support DDR4 today — including rather decent 13/14 Generation Core or Core 2-series based on the Raptor Lake silicon or all-new Bartlett Lake silicon — and can take advantage of lower-cost memory, they will not have a lot of time to do so.

Samsung and SK hynix will maintain production of DDR4 memory until the end of 2025 and Q1–Q2 2026, respectively. So DDR4 products are not going to vanish overnight, and will remain widely available well into 2026. After that period, it's safe to assume that DDR4 will become niche memory for applications with a very long lifecycle. Even after that, smaller players will keep producing DDR4 for those who need it.

Micron to ship final DDR4 chips in early 2026

Micron issued end-of-life notices for DDR4 and LPDDR4 products several months ago to customers in multiple high-volume segments, like consumer PCs, data centers, and mobile devices. Micron notified them that final shipments of mainstream DDR4 and LPDDR4 devices will occur within the next two to three quarters. Or in other words, early 2026.

"Micron's leading-edge DRAM nodes such as 1ß and 1γ are focused on the latest-generation products such as DDR5, LPDDR5, and HBM, and are not utilized to produce DDR4 and LPDDR4," said Sanjay Mehrotra, chief executive of Micron, during the company's latest conference call. "DDR4 and LPDDR4 products are largely produced in our 1α (1-alpha) DRAM node."

As with previous memory transitions, Micron will continue to support long-term, lower-volume customers in the automotive, defense, industrial, and telecom sectors, with 1α DRAM for several more years, at appropriate prices. As a result, expect shortages of DDR4 and LPDDR4 memory from Micron to occur in the coming quarters. But the good news is that there are plenty of DDR4 memory modules available now from Micron's Crucial brand.

Samsung to sustain DDR4 production until December 2025

Samsung uses its 3^rd Generation 10nm-class (1z) process technology to produce its inexpensive DDR4 devices. Due to strong demand and increasing prices of DDR4, the company is postponing the shutdown of its DDR4 1z DRAM production lines until the end of 2025, according to TheElec.

Samsung initially informed clients that it would end DDR4 1z DRAM production by late 2025, the report claims. However, to meet demand for previous-generation memory and grab some extra cash, the company decided to keep its 1z DRAM manufacturing line running for several more weeks, which equals millions of dollars. These lines are already fully depreciated, so the cost of keeping them up is low.

Normally, Samsung needs to install new production lines as soon as possible to meet demand for more advanced and popular products. However, just like Micron, Samsung is obliged to support its long-term clients from the automotive, industrial, and telecommunications sectors with low volumes of DDR4 for years to come. So mass-producing DDR4 for just a little longer makes sense for the company. Samsung's revised plan may also provide short-term relief for module makers and device manufacturers that do not have a long-term supply contract with the company.

Samsung is poised to sell DDR4 chips for several months (if not quarters) into 2026, assuming that the final mass-produced DDR4 device will be made in December 2025.

SK hynix to keep DDR4 production till Q2

SK hynix's transition away from DDR4 is expected to proceed as planned. According to a source with knowledge of the matter speaking to Tom's Hardware, SK hynix's production is winding down between the first and second quarters of 2026. This will likely make SK hynix the last high-volume producer of DDR4 memory. However, it remains to be seen whether it will prolong volume production.

Of course, the company will also keep supporting its clients with long-term contracts and niche applications with DDR4 chips for years to come. But, by 2027, it'll be hard to come by unbuffered DDR4 memory modules made by SK hynix.

The outlook on DDR4

High Bandwidth Memory (HBM) is the unsung hero behind the AI revolution. As the industry seeks to extract the most performance from frontier AI models, HBM powers the world's fastest GPUs and AI accelerators by keeping the intense computational engines fed with data at breakneck speed. This critical technology has rapidly matured over the past several years, and lately the pace of innovation has quickened, as industry behemoths like Nvidia and AMD look to facilitate the creation of more advanced artificial intelligence models.

All three major DRAM makers (Micron, Samsung, and SK hynix) have started volume production of 8-Hi HBM3E stacks, the newest form of the technology. And more robust and powerful forms of HBM memory are already in development.

Unfortunately, shortages of sophisticated HBM memory have hampered the supply of AI GPUs, which has manufacturers racing to add more production capacity to address any shortfalls. Meanwhile, the development of next-gen HBM products continues apace, hand-in-hand with new performance-enhancing technologies, which will power the next wave of AI accelerators.

Let's take a look at what's next on the HBM roadmaps for Micron, Samsung, and SK hynix based on official information and other sources.

Speeds and feeds

Memory bandwidth is a critical bottleneck in AI systems — AI models, particularly deep learning models, ingest tremendous amounts of data as they chew through workloads. But most forms of modern memory can't satiate AI's ravenous appetite for more data. That's where HBM steps in.

Traditional memory based on DDR, LPDDR, or GDDR uses 128–bit to 512-bit wide interfaces and employs high data transfer rates to provide bandwidth from 100 GB/s to 2 TB/s.

Unlike traditional memory, high-bandwidth memory (HBM) uses a very wide interface—1024 bits in the case of HBM2 and HBM3, or 2048 bits with HBM4—which multiplies bandwidth up to 4 TB/s—8 TB/s. Given the bandwidth-constrained nature of high-intensity parallel computation in GPUs and accelerators, this increased bandwidth translates directly to more performance.

However, the wide interface makes HBM difficult to produce, requiring multiple specialized DRAM devices interconnected using through-silicon vias (TSVs) stacked on top of a base die. HBM makers also vary the number of stacked memory dies to increase capacity, denoted by terminology such as 8-Hi for eight stacked dies, or 12-Hi for 12 stacked dies.

Due to its huge bandwidth, HBM is, and will continue to be, the de facto memory standard for AI systems, HPC ASICs, and GPUs.

12-Hi HBM3E is almost here

Today's highest-end AI accelerators — including Nvidia's H200 (141 GB), B200 (192 GB), and AMD's Instinct MI300X (192 GB) — use 24 GB 8-Hi HBM3E stacks based on 24 Gb DRAM devices. The next step for the industry is to adopt higher-capacity 36 GB 12-Hi HBM3E packages featuring 24 Gb memory dies. These will be used by Nvidia's upcoming B300-series and AMD's next-gen MI325X AI accelerators.

SK hynix has begun mass production of 36 GB 12-Hi HBM3E chips, whereas Micron has been sampling similar products since September, with mass production of the new packages understood to be imminent.

Samsung, on the other hand, was late to the party with its 8-Hi HBM3E certification, and its 12-Hi HBM3E dies also suffered from a slight delay. Samsung's delay is likely caused by sticking with its 1α fabrication technology, unlike Micron and SK hynix, which use a 1ß (5th Gen, 10nm-class) DRAM process to make their HBM3E DRAM ICs. By the time Nvidia's B300 enters mass production, Samsung will likely be able to compete with 12-Hi HBM3E 36 Gb offerings of its own.

HBM4: 2048-bit I/O and up to 16 layers

While manufacturers are still wrapping their hands around the upcoming HBM3E rollout, HBM4 and HBM4E are both already on the horizon.

The preliminary HBM4 specification (unveiled in July 2024) introduces a wider 2048-bit interface for HBM stacks. It also specifies 24 Gb and 32 Gb DRAM layers at up to 6.40 GT/s. The spec supports 4-Hi, 8-Hi, 12-Hi, and 16-Hi configurations, ensuring greater flexibility and potentially enabling even larger 64 Gb HBM4 packages.

Meanwhile, HBM4E may also boast high interface speeds of around 9 GT/s, as Rambus' HBM4 memory controller IP exceeds the announced capabilities of HBM4's JDEC-standard 6.40 GT/s speeds.

With HBM4E, memory makers will be able to customize base dies of packages (which SK hynix envisioned in early 2024) by adding additional functions, which could potentially extend to enhanced caches, custom interface protocols, and more.

All three leading memory manufacturers, Micron, Samsung, and SK hynix, have confirmed their intentions to produce HBM4 and HBM4E memory, but their overall rollout strategies may differ.

HBM4: 16-Hi stacks, but no 32 Gb devices on horizon

For now, none of the prominent DRAM producers have HBM4 or HBM4E stacks based on 32 Gb memory devices on their roadmaps. As such, all HBM4 and HBM4E products are expected to utilize smaller 24 Gb DRAM dies when they first roll out.

Micron is expected to keep using its proven 1ß (5th Gen, 10nm-class) process technology to make 24 Gb memory ICs for HBM4 stacks; however, Samsung plans to transition to 24 Gb DRAM dies made on its 1γ (6th Gen, 10nm-class) process with HBM4 and HBM4E. This will likely offer Samsung substantial performance, power efficiency, and cost advantages. SK hynix also intends to use 1ß for HBM4 DRAM ICs and may transition to a 1γ process for the HBM4E offering.

When it comes to layers, Micron lists 12-Hi and 16-Hi versions of its HBM4 and HBM4E offerings, whereas Samsung and SK hynix may go straight to 16-Hi HBM4 stacks. With the standard appearing to be 24 Gb DRAM devices and 12-Hi or 16-Hi stacks, HBM4 will increase per-package capacity to 48 Gb, a noticeable leap over HBM3E's 36Gb.

It's possible that by the time HBM4E finally arrives, the number of supported layers may exceed 16, with rumors that South Korean manufacturers could adopt a 20-layer design (which should be taken with a grain of salt). By then, DRAM makers may have also adopted a 32 Gb package for high-bandwidth offerings.

HBM4 & HBM4E production nodes

It should be no surprise that HBM4 and HBM4E memory stacks will rely on base dies produced by logic manufacturers using logic process technologies, thus boosting transfer speeds and signal integrity. TSMC and SK hynix were the first to disclose that they plan to use TSMC’s 12FFC+ and N5 base dies for HBM4. It's likely that Micron will also use TSMC's base dies (as the two companies are partners), though this has not been officially confirmed.

Samsung is expected to use its own Samsung Foundry nodes for HBM4 and HBM4E base dies. There is still uncertainty around the exact node it will employ, though it is reasonable to expect similar process technologies to TSMC's 12FFC+ and N5 processes.

HBM4 is coming in 2026 & HBM4E expected a year later

Samsung and SK hynix are rumored to introduce their first HBM4 offerings around Q3 2025, whereas Micron is projected to follow in Q4 2025. In both cases, 'introductions' likely mean the delivery of the first working samples to partners like AMD and Nvidia, not high-volume manufacturing.

Considering that the mass production of actual processors that support HBM4 is not expected until 2026, Micron's slight delay does not seem like a major issue.

Curiously, Micron began discussing HBM4E around a year before the planned mass production of HBM4 was set to commence. Typically, 'extended' variants of HBM specifications are introduced years after the original standard. According to Micron's official roadmap, HBM4E is set to arrive in late 2027.

HBM4E is likely to be used in the generation after the release of Nvidia's upcoming Rubin architecture and AMD's MI400 AI accelerator. Both are slated to support HBM4 in 2026.

If the industry requires customizable memory, HBM4E might land earlier than expected, but don't hold your breath — HBM development is notoriously challenging.

Decades of evolution have made NAND flash memory both cheap and incredibly sophisticated. No matter what modern device you pick up, the likelihood is that it will use some kind of NAND, which has become ubiquitous in both consumer products and data centers. If you cast your mind back several decades, NAND was expensive, despite its capability to be faster than spinning disks. As the technology has matured, its use has grown exponentially. But what's next?

In the coming years, we're going to see cheaper, more advanced non-volatile flash memory inside our devices. Those 3D NAND devices will be built from over 500 layers and boast interface speeds of up to 4800 MT/s. This blistering speed may pave the way to all-new kinds of devices with significantly increased performance compared to today's best SSDs.

The next step

Like other technologies, 3D NAND develops in multiple directions. End users demand higher capacity, higher performance, lower power, compact dimensions, and lower cost. Manufacturers themselves want to earn money, so while meeting demand, they try to cut costs by making smaller memory devices. Given the current state of industry development, the best way to keep the size of 3D NAND dies in check is to increase the number of layers and decrease the size of the actual data storage location — the memory cell itself. This practice is commonplace among memory makers today.

Leading makers of 3D NAND memory, including Kioxia, Micron, Samsung, SK Hynix, and YMTC, have all developed multiple 3D NAND generations, consistently increasing layer counts while reducing cell sizes. For now, the majority of 3D NAND-based devices, including SSDs and smartphones, rely on memory with 2xx layers, with each layer holding an incredible number of memory cells for data storage.

This might be 218-layer 3D NAND from Kioxia, 232-layer 3D NAND from Micron, or 286-layer 3D NAND from Samsung.

The pace at which manufacturers adopt new layer counts and boost transfer rates varies across the industry, making things difficult to track. So let's examine where we were in 2023, how it's going, and where we might be in 2027. Just as a reminder: Kioxia also has a close production partnership with Western Digital's flash division, which also owns SanDisk as a subsidiary. Within this article, we'll refer to the duo as Kioxia / Western Digital.

In recent years, the industry faced significant challenges in building an SSD with a PCIe 5.0 x4 interface that would fully saturate that interface. ICs with a high-performance interface that could fully saturate the lane using an eight-channel controller (e.g., 2400 MT/s) are rare. Instead, ICs that supported lower speeds are much more common.

By early 2023, all three major NAND vendors — Kioxia / Western Digital, Micron, and Samsung — had established 2400 MT/s as the baseline interface speed across TLC products. Kioxia's BiCS 6T and 6Q nodes, Micron’s B58, and Samsung’s V8T are representative of these tiers as a mainstream standard, and perhaps this reflects a consistent performance scaling for both consumer and enterprise storage segments.

In 2024, Samsung took the next incremental step by introducing its V9T TLC at 3000 MT/s. This intermediate speed tier, not shared by other vendors in the roadmap, highlights Samsung’s focus on being a vertically integrated company that focuses mainly on its own-brand products, like smartphones and SSDs.

Kioxia / Western Digital reached 3200 MT/s in the second half of 2024, with its 8th Gen BiCS 3D TLC, followed by QLC (BiCS 8Q) products in 2025 H2. However, Kioxia / Western Digital has not mentioned using 7th Gen products at all, skipping it entirely.

This reflects a general push to align both TLC and QLC offerings on higher-performance platforms. Notably, Kioxia / Western Digital is the only vendor explicitly listed in the roadmap as deploying 3200 MT/s in both cell types, showing a strong commitment to QLC performance uplift.

In 2024, Micron came to leadership with its B68S IC, sporting a 3600 MT/s data transfer rate. By the second half of 2025, the company’s QLC roadmap plans to catch up with Samsung via the N69 generation. This highlights Micron’s early adoption of faster interfaces for high-end products, but since it's yet to be released, its impact and uptake remain to be seen. Kioxia/Western Digital also lists its BiCS 8Q QLC reaching 3600 MT/s in 2025 H2, indicating a broader QLC performance push across the industry.

All vendors eventually converge at 4800 MT/s by 2027, which becomes the high-performance standard. Kioxia/WD reaches this milestone with BiCS 9T TLC in 2027 H1, Micron with B78 TLC and N79 QLC in 2027 H1–H2, and Samsung with its 11th generation of V-NAND.

Performance headwinds

Manufacturing high-speed NAND flash (3600 MT/s and higher) requires a more expensive logic process technology, which drives up production costs and inflates flash memory prices.

An increase in 3D NAND data transfer rates will have a very practical implication on how devices like SSDs or smartphones are built.

To fully saturate a PCIe 5.0 x4 interface — which provides up to 15.75 GB/s of effective bandwidth — a modern NAND flash setup requires an SSD controller with eight channels at 2400 MT/s, six channels at 3600 MT/s, or just four channels at 4800 MT/s. In a year or two, PCIe 5.0 SSD controllers won't require eight channels to fully saturate the hungry interface.

For PCIe 6.0 x4, which doubles throughput to around 31.5 GB/s effective (after protocol overhead), the number of required channels increases 16 at 2400 MT/s, 12 at 3600 MT/s, and eight at 4800 MT/s. As NAND I/O performance approaches these thresholds, high-end SSDs can exploit PCIe 6.0 capabilities with eight high-speed NAND devices. However, it remains to be seen whether PCIe 6.0 x4 SSDs will be a reality for consumer storage devices within the next few years.

Die capacities

Based on the roadmap data that we have collated, leading 3D NAND makers will converge, landing with 1 Tb and 2 Tb die capacities by around 2026 - 2027, particularly for 3D QLC products. While there are some 2Tb QLC NAND devices announced as of May 2025, none of them are actually on the market yet.

Micron, Kioxia/Western Digital, Samsung, SK Hynix, and YMTC all plan to offer 3D QLC devices reaching 2 Tb capacities, typically paired with interface speeds of 3200MT/s – 4800 MT/s over the next few years. Despite the significantly increased layer count, 3D NAND manufacturers are not jumping to capacities higher than 2Tbs per device for the time being, perhaps due to cost concerns.

Rising layer counts: How does each company stack up?

Kicking off with Kioxia and Western Digital, this duo's 3D NAND roadmap featured BiCS 6 with 162 layers across both TLC and QLC variants in the first half of 2023. BiCS 6 represents a mature and commercially proven node, used in mainstream SSDs and enterprise storage. This generation aligns with the industry’s transition toward high-density vertical stacking, while supporting a 2400 MT/s interface speed.

Kioxia and Western Digital didn't stop there, and in the second half of 2024, these companies introduced BiCS 8 in both TLC (BiCS 8T) and QLC (BiCS 8Q) forms, now featuring between 218 and 232 layers. This generation continues to rely on 2400 MT/s – 3600 MT/s interfaces, marking both vertical and performance scaling. Also, it demonstrates Kioxia’s intent to advance QLC’s competitiveness in both storage density and performance.

BiCS 8 will be a fairly long-standing node for Kioxia and Western Digital, as it will be replaced in the first half of 2027. BiCS 9T is set to replace it, boasting a layer count of greater than 300, representing quite an aggressive step forward. This milestone puts Kioxia in alignment with other vendors’ 3D NAND scaling targets, while also introducing 4800 MT/s interface speeds.

Micron’s lineup includes the now legendary B58 IC with 232 layers and a 2400 MT/s data transfer rate. But its 1st Gen ICs featured a lower rate; its full speed was only achieved sometime in the first half of 2023. Nevertheless, the B58 gave Micron an early lead in vertical scaling versus competitors still shipping 162–192 layer products.

In the second half of 2024, Micron advanced to the B68S IC, increasing the layer count to 276. This generation pairs higher density with elevated performance (3600 MT/s), making it a major step in Micron’s 3D NAND roadmap, and making the company one of the leading makers of enthusiast-grade SSDs with the model 4600.

In the first half of 2027, Micron is expected to introduce its B78 3D TLC NAND ICs, with a 4800 MT/s interface. However, the exact layer count is not known. Given the trend from B58 (232L) to B68S (276L), it is reasonable to expect B78 to reach well beyond 300 layers, likely on par with Kioxia’s and Samsung’s leading nodes. However, there are no official materials on exact layer counts, so this remains speculation.

When it comes to 3D NAND makers, Samsung is a rare animal. All producers of flash memory prefer to sell their chips as parts of their own devices, such as SSDs, and to that end, Micron works closely with Silicon Motion and Phison to optimize controllers for its memory and drives. In a similar vein, Kioxia works with Phison. Unlike its rivals, Samsung has its own 3D NAND and controllers to build its SSDs and other products using NAND flash memory. The company also sells its 3D NAND ICs on the open market as an additional boon.

Samsung offered its V8T IC in 2023 H2 with 236 layers, placing it alongside Micron’s B58 and slightly ahead of Kioxia’s BiCS 6. This node continues to be Samsung’s workhorse today.

By the second half of 2025, Samsung is set to mass produce V9T, scaling to 286 layers — a 50-layer jump over V8T. This milestone indicates V9T’s interface speed remains at 3600 MT/s, indicating a controlled ramp before moving to more aggressive performance targets.

Looking ahead to 2026 H1, Samsung’s roadmap lists V10T IC with an expected layer count of over 400, representing the most ambitious vertical target. While this node’s interface speed is also pegged at 4800 MT/s, its standout feature is the sheer layer height, suggesting multi-tier stacking and next-gen integration techniques, such as string stacking and hybrid bonding. However, Samsung has not officially announced that it is using any of those specific techniques quite yet.

SK hynix’s current product lineup includes the V8T IC with 238 layers, a 2400 MT/s interface, and has been available since the second half of 2023, marking their entry into late-Gen 3D NAND scaling. The next major leap occurs with V9T, reaching 321 layers in the first half of 2025, and then increasing interface performance to 3600 MT/s by the second half of 2025.

This shows a rapid vertical scaling effort while improving I/O bandwidth. The company's most ambitious node, V10T, is set to debut in 2027 H1, with 500 layers and a 4800 MT/s interface — matching top-tier bandwidth targets from other vendors, and surpassing them in vertical stack height. The roadmap extends further to V11T (4800 MT/s), though its layer count is not explicitly known.

On the QLC side, SK hynix’s roadmap begins with V7Q in the first half of 2024 at 176 layers, then it extends to V9Q, which delivers 3200 MT/s performance and a 2 Tb die capacity — implying a 300L+ stack. By the first half of 2027, QLC products are also expected to adopt the 500-layer structure (V10Q) at 4800 MT/s, mirroring TLC’s configuration.

When it comes to layer counts, China-based YMTC is not a leader, but its 3D NAND development shows a clear trajectory from mid-tier to high-tier stacking. YMTC’s 3D TLC product (X4-9060) features 128 layers and a 3600 MT/s interface, and was followed quickly by X3-9070 in the second half of 2024. X3-9070 jumped to 232 layers while maintaining the same data transfer rate. This indicates a rapid scaling of vertical density — despite sanctions by the U.S. government. This is likely enabled by the company’s proprietary Xtacking architecture, which separates logic and memory layers to simplify integration. However, no QLC-specific layer counts are known for now.

By 2026 – 2027, YMTC’s roadmap aims to enter the high-performance class of its competitors. The X5-9080 and X5-9070 3D TLC NAND products operate at 4800 MT/s, and the latter is explicitly listed as a 1 Tb die, suggesting a likely move to 300+ layers, although exact counts are not known. Meanwhile, the company’s 3D QLC line (e.g., X4-6080, X5-6080) appears on the roadmap in parallel, also reaching 4800 MT/s by the second half of 2026, hinting at comparable architectural advances.

YMTC’s roadmap outlines a fast-paced rise from 128L to 232L and potentially 300L+ stacking within three years—driven by a balance of aggressive layer scaling and interface speed improvements across both TLC and QLC products.

What's next for 3D NAND?

The future of 3D NAND is defined by fairly aggressive vertical scaling, faster interfaces, and a push toward higher per-die capacities, which will enable products that will enable faster, denser, and more cost-efficient storage across consumer and enterprise segments. To make that happen, all major vendors are set to converge at a 4800 MT/s interface speed and 300–500-layer stacks by 2027.

However, this progress is not without complexity. Vertical scaling introduces new challenges in terms of yield, while higher speeds now also require logic process nodes, which raises manufacturing costs. Eventually, when everyone in 3D NAND manufacturing converges at hybrid bonding (which YMTC already uses, while sporting one of the industry’s widest patent portfolios). These techniques will add another layer of complexity, and companies will require some time to get used to these new processes.

In any case, the future of 3D NAND is bright, as the industry races towards faster speeds, higher stacks, and more complex manufacturing technology.

Micron this week announced its 9650 SSD, the industry's first solid-state drive with a PCIe 6.0 x4 host interface aimed at performance-hungry workloads and offering unprecedented sequential read speed and random performance. In addition, the company formally introduced its 6600 ION family of SSDs with capacities of up to 245 TB.

Micron's data center-grade 9650 SSD is based on a proprietary controller designed in-house and the company's 9th Generation 276-layer 3D TLC NAND with a 3.6 GT/s interface. The PCIe Gen6 drive promises a sequential read speed of up to 28,000 MB/s and a sequential write speed of up to 14,000 MB/s, which by far exceeds the capabilities of the best SSDs with a PCIe 5.0 x4 interface. As for random performance, the drive is speced for up to 5.5M read IOPS, which is a record, and up to 0.9M write IOPS, which is a moderate result for an enterprise-grade SSD.

For now, Micron positions its 9650 SSD primarily for AI servers that need extreme performance both for sequential reads and (more importantly) random reads. The drives will be available in E1.S (9.5mm and 15mm) as well as E3.S 1T form-factors, with some drives being friendly to liquid cooling systems for consistent performance under high loads.

Micron already demonstrated its 9650 SSDs with Astera Labs and Broadcom at various trade shows, including Computex. The drive is meant to communicate in peer-to-peer PCIe 6.0 mode at 64 GT/s with Nvidia's Blackwell GPUs using Astera's or Broadcom's retimers and switches without CPU intervention, which is important both for AI training and inference workloads.

"With up to 5.5 million IOPS for random reads, the Micron 9650 is purpose-built for AI pipelines' high-throughput, low-latency demands," said Arunkumar Narayanan, senior vice president of Compute and Networking, Infrastructure Solutions Group (ISG) at Dell Technologies. "This product helps ensure GPUs remain continuously fed with data, minimizing idle cycles and maximizing system efficiency. Combined with Dell’s advanced server architecture, this innovation empowers enterprises to unlock new levels of performance and insight."

In addition to the high-performance 9650 SSD with a PCIe 6.0 x4 interface, Micron also announced its 6600 ION SSD family that is designed for high-density, power-efficient storage in AI and hyperscale data centers.

ChangXin Memory Technologies (CXMT) had to delay mass production of its DDR5 memory devices in a bid to improve quality to late 2025, reports Digitimes. However, it looks like the quality of the company's DDR5 ICs is now on par with that of Nanya, according to the same report. The combination of improved yields, quality, and CXMT's expanding production capacity can make not only smaller Taiwan-based vendors, but also global players worry about CXMT's impact on the market.

Quality and yields plague CXMT's DDR5

In an unexpected turn of events, CXMT reportedly began to produce its DDR5 memory late last year, which made the industry worry that the China-based DRAM maker planned to flood the market with cheap DDR5 ICs. Later on, it was revealed that CXMT was using an outdated (presumably its 4th Generation DRAM node) process technology to make its 16 GB DDR5 devices, which is why they were 40% larger compared to 16 GB DDR5 ICs produced by Samsung. This meant that CXMT's DDR5 DRAMs are significantly costlier to build compared to DDR5 chips by Samsung, which makes flooding the market with such devices particularly hard and unprofitable. 

But costs were not the only reported issues with CXMT's DDR5 chips. Early testing of CXMT's DDR5 samples in early 2025 allegedly exposed stability issues at around 60°C (a common temperature for DDR5 memory modules in tightly packed systems) and also problems with operation at sub-zero temperatures. These issues prevented modules based on CXMT's DDR5 ICs from meeting reliability standards. As a result, CXMT reportedly had to change the design of their DDR5 devices to a degree that it had to make new photomasks (a costly process), which reportedly solved problems with operating at high or low temperatures. 

As a result, CXMT had to delay mass production of its DDR5 memory. Insiders initially projected volume production to start around May or June 2025, but by July, there was no evidence of volume shipments, reports DigiTimes. As it turns out, despite advancements with thermals, yield rates on CXMT's production line are still relatively low, hovering just above 50%, which is unacceptable for commodity DRAM. Digitimes supply chain sources suggest that more refinement and operational experience will be required before CXMT can reach yields competitive with the industry average, which will further delay mass production. For now, the company is targeting large-scale DDR manufacturing by the end of 2025.

Improving quality

Recent tests of CXMT's DDR5 modules indicate a significant leap in quality and performance that are now said to be nearly on par with Taiwan's Nanya Technology, according to DigiTimes. If these products are validated by leading PC makers or module products, their validation will suggest that CXMT is closing the gap with established DRAM suppliers. Of course, these parts have not yet entered high-volume production due to yield issues, so for now, CXMT can hardly be considered a competitor on the DDR5 market.

Western companies may withdraw maintenance

While CXMT has reportedly refined the quality of its DDR5 ICs and is on track to improve production yield, the company still faces major challenges. 

First up, CXMT's 16 GB DDR5 is costlier to make than similar chips from other companies as CXMT's G4 fabrication technology has a feature size of around 16nm, according to TechInsights, which corresponds to Samsung's 3rd Generation 10nm-class node the company introduced in early 2021. 

Secondly, because CXMT's G4 manufacturing process has a feature size of 16nm, makers of wafer fab equipment can no longer maintain tools used to build such memory chips in China as the U.S. export rules imposed in 2022 prohibit shipments or maintenance of wafer equipment in China that can be used or are used to make DRAMs on nodes more advanced than 18nm. If CXMT's suppliers (which include American, European, and Japanese companies) can no longer support the company's tools or supply spare parts or raw materials to the DRAM maker, it will make it particularly hard for the company to improve yields or mass produce its DDR5 memory.

CXMT keeps expanding capacity, for now

Micron this month announced a renewed U.S. buildout strategy that expands investment plans to $150 million, plans to build an HBM packaging facility in Virginia, and invest some $50 billion in R&D. Micron's first new U.S. fab in years will begin operations in the second half of 2027, the company revealed this month.

Following the enactment of the CHIPS and Science Act in August 2022, Micron unveiled major plans to build new fabs worth over $115 billion in Idaho and New York with the aim of building 40% of its DRAM products in the U.S. over the next decade. Under the new plan, Micron projects investing $200 billion in U.S.-based memory production and R&D over the next 20+ years, with support from the U.S. government.

The effort includes $150 billion for manufacturing and $50 billion for R&D, with the goal of creating around 90,000 direct and indirect jobs. The new plan envisions two leading-edge DRAM fabs in Idaho, a site with four fabs in New York, and an HBM packaging facility in Virginia. Let's take a closer look at Micron's plans.

A $200 billion plan

The first part of the original plan involved building one of the world's largest and most advanced DRAM production facilities near Boise, Idaho, which is now known as Fab ID1. Once fully outfitted with production equipment, the cleanroom area of ID1 will span 600,000 square feet (~55,700 square meters). This is roughly double the cleanroom capacity of GlobalFoundries’ Fab 8 and on par with the large-scale fabs operated by competitors Samsung and SK Hynix in South Korea.

Micron's first new fab in Idaho (ID1) reached a key construction milestone in June 2025 and is expected to begin wafer output in the second half of calendar 2027, with customer qualifications following thereafter, Micron announced this week. The second Idaho fab (ID2) will be built adjacent to ID1, benefiting from shared infrastructure and R&D co-location. Micron expects ID2 to enter production before the New York fab, although the company didn't elaborate on the exact timing.

However, while Micron broke ground on its new fab in Idaho and ID1 is expected to begin operations in a couple of years, the company is still struggling to start construction near Clay, New York. Micron plans to begin groundwork for its New York fab by the end of 2025, after completion of federal and state environmental reviews. Micron's New York plan is even more ambitious than the Idaho plan, as it involves four fab phases with cleanroom areas of around 600,000 square feet (approximately 55,700 square meters). While no specific production timeline has been announced for this site, it is clear that the site is a part of Micron's strategic long-term effort to establish a robust domestic manufacturing footprint in support of both commercial and national computing needs.

In addition to building brand-new fabs, Micron is set to expand its facility in Manassas, Virginia. Currently, this plant manufactures memory chips for automotive, aerospace, defense, and industrial applications. After the upgrade, the fab will gain capacity as well as advanced packaging capabilities to assemble HBM memory stacks in the U.S. However, Micron will only add HBM capability to its Virginia plant after it ramps up production of enough DRAM wafers in the U.S. at its fabs in Boise, Idaho. That said, expect Micron to build HBM5 or HBM6 in the U.S.

"As part of this $200 billion investment plan, Micron plans to […] [bring] advanced packaging capabilities to the U.S. to support our long-term HBM growth plans after we have established sufficient DRAM wafer scale in our U.S. operations," said Sanjay Mehrotra, chief executive and chairman of Micron.

"[…] Our first Idaho fab, ID1, achieved another key construction milestone in June. We expect first DRAM wafer output at ID1 to begin in the second half of calendar 2027, with customer qualifications to follow. The second Idaho fab, ID2, will benefit from manufacturing economies of scale with ID1, and add to R&D co-location benefits with greater efficiencies and faster time to market. To meet anticipated demand, ID2 will begin production before the first New York fab. We expect to begin ground preparation in New York later this year following the completion of state and federal environmental reviews," he concluded.

A great unknown

Although Micron clearly states that it plans to invest some $150 billion in its manufacturing capacities in America, it only disclosed the completion schedule for its Fab ID1, which is about to be completed, and the groundwork for the first New York facility. No schedules for other projects have been mentioned, except that Micron intends to invest $150 billion in its U.S. operations over the course of 20 years or more.

But perhaps the biggest unknown in Micron's announcement is its $50 billion R&D project. The company spent between 10% and 20% of its revenue on R&D in 2022 – 2024 (from $3.1 billion to $3.43 billion). Last year, the company invested $3.43 billion (14% of revenue) on research and development, so $50 billion is Micron's R&D budget for around 14 years. Yet, the company conducts R&D operations not only in the U.S. but also in Japan, Taiwan, and Singapore. To that end, it is unclear whether $50 billion means increase of R&D operations in the U.S. at the expense of other sites, or additional spending of $50 billion dollars on R&D in the U.S. on top of regular expenditures over the course of the next 20+ years (less than $2.5 billion per year), which would be a significant addition.

"Micron's U.S. memory manufacturing and R&D plans underscore our commitment to driving innovation and strengthening the domestic semiconductor industry," said Mehrotra. "This approximately $200 billion investment will reinforce America’s technological leadership, create tens of thousands of American jobs across the semiconductor ecosystem and secure a domestic supply of semiconductors — critical to economic and national security."

Micron expects all its U.S. projects to qualify for the Advanced Manufacturing Investment Credit (AMIC) and has secured support at the local, state, and federal levels. This includes up to $6.4 billion in CHIPS Act funding for two fabs in Idaho, two in New York, and the Virginia site upgrade.

Summary

Yangtze Memory Technologies Company, also known as YMTC, has filed the third lawsuit in an extended legal battle against American competitor Micron. YMTC is now accusing Micron of funding and perpetuating an extended misinformation campaign with the help of American public affairs firm DCI Group aimed at slandering YMTC.

The new suit leveled against Micron claims that the American firm has "lagged behind YMTC in innovation and product performance," causing it to resort to illegal means to get ahead. Specifically, Micron is accused of funding DCI Group's "China Tech Threat" astroturfing campaign website. The CTT website, which claims that YMTC's NAND memory chips include spyware backdoors to the Chinese Communist Party, has been reportedly funded in large part by U.S. tech companies Micron and Dell.

"Astroturfing," a word used repeatedly in the YMTC lawsuit, refers to the practice of disguising corporate interests and messaging as grassroots advocacy. YMTC's newest lawsuit hinges on Micron funding China Tech Threat, along with other major U.S. tech firms, and also states that the claims bought and paid for were provably false. For example, a NAND Flash chip does not have built-in communications abilities to send its data overseas, as CTT alleges.

The lawsuit is the third in a protracted legal battle between Micron and YMTC. YMTC first became labelled as an enemy of U.S. tech interests in 2022, when the company was blacklisted by the Department of Commerce as a potential Entity with connections to the Chinese government or military. YMTC responded by convincing the Chinese Cybersecurity Review Office to ban Micron devices for use in Chinese government computers.

In 2023, YMTC leveled its first lawsuit against Micron, accusing the company of breaking 11 of YMTC's copyrights. Micron soon filed a countersuit, instead accusing YMTC of violating its own copyrights. A recent court order in the case ordered Micron to hand over 73 pages of confidential documents regarding company technologies as part of discovery in the case.

Micron earlier this week filed a motion to block this order, alleging that YMTC had requested too many pages and would surely steal sensitive information from the documents. However, the nature of the discovery, meaning that the documents would be printed, available for eyes only, and would not be seen by YMTC but by YMTC's court-approved outside counsel and experts, makes this claim somewhat shaky.

Micron's alleged partners who have been confirmed to be involved in the China Tech Threat astroturf campaign have been provably making money off of the anti-China campaign, according to the YMTC lawsuit. Other China Tech Threat claims have included uncited and unprovable claims that YMTC was involved in a Social Security scam in 2020, or that PC OEM Lenovo is also a Chinese spy asset (U.S. OEM Dell was also found to have monetarily backed the CTT website).

The YMTC and Micron legal battle shows no signs of slowing down. Micron is a famously litigious company — though it has lost similar legal battles claiming IP theft from other Chinese tech firms (like its 5-year legal battle against Fujian Jinhua). How Micron will fare now, engaged in both a lawsuit claiming patent theft and one alleging defamation and misinformation, has yet to be seen.

While many fabs co-funded by the U.S. government under the CHIPS and Science Act are being built or are about to start ramping production of semiconductors, there are some facilities for which construction has not started due to environmental reviews and protests of local residents, with companies "mired in NIMBY fights and two-year permits." Among such projects are Amkor's advanced packaging facility in Arizona, Micron's DRAM fab in New York, and SK hynix's HBM facility in Indiana, reports SemiAnalysis.

Locals oppose Amkor's facility

Amkor's plan to build a $2 billion chip packaging facility near Peoria, Arizona, is facing resistance from nearby residents of Vistancia. The locals are opposing Amkor's proposed site due to concerns about the potential strain on water resources and increased traffic congestion. Some residents are threatening legal action and calling for the project to be moved elsewhere.

Amkor's advanced packaging facility, which will include over 500,000 square feet (46,451 square meters) of cleanroom space when constructed and equipped, is crucial for the local semiconductor supply chain that already includes TSMC's Fab 21 campus as well as over a dozen suppliers. The plant, which is expected to be one of the world's largest advanced packaging factories in the world, is also crucial for companies like Apple, which has committed to building chips at TSMC's Fab 21 and packaging them at Amkor's facility. However, given the ongoing protests, it remains to be seen whether the plant will come online in 2027, as planned.

Micron's $100 billion campus faces delays

The situation is not unique to Amkor and Arizona. In Clay, New York, Micron's planned massive $100 billion DRAM production site (originally expected to be completed in the 2040s and create some 50,000 direct and indirect jobs) has experienced scheduling setbacks. The company's environmental review was delayed, and the period for public feedback has been extended through August. As a result, construction, which was supposed to start in 2024, cannot begin until community objections are resolved.

The campus near Clay, New York, was expected to become the largest manufacturing site Micron has ever developed and one of the biggest semiconductor facilities in the United States. The site is projected to house four clean rooms totaling 600,000 square feet (around 55,700 square meters), which is about eight times larger than the clean room space at GlobalFoundries' Fab 8 facility.

The fab is a key part of Micron's strategy to expand its U.S. production. The initial stage of construction in Clay was projected to require approximately $20 billion in spending through the end of this decade, setting the stage for the larger buildout planned in the following years. However, Micron is facing massive delays, so instead of earning a million a day later this decade producing memory in the U.S., the company will have to invent ways to produce enough DRAM later in the 2020s. According to the report, delays on a $20B fab are costing $5M per day.

Micron planned to manufacture 40% of its DRAM output within the United States by the mid-2030s, operating its facilities near Boise, Idaho, and Clay, New York. However, given the current delay, it is unclear whether Micron manages to execute its plan.

SK hynix gets approval, but that was hard

In West Lafayette, Indiana, SK hynix obtained approval for its $3.9 billion high-bandwidth memory (HBM) production site, but it took it seven hours to persuade the city council. The company faced resistance from local residents regarding the rezoning of over 120 acres near their homes. Residents expressed concerns about industrial development near residential zones, nearly stalling the project.

The $3.9 billion facility dedicated to HBM and other exotic types of memory is expected to be one of the biggest and most sophisticated DRAM assembly facilities on the planet when it starts operations in 2028. The plant is projected to create up to 1,000 jobs, and SK hynix also plans to partner with Purdue University over future R&D projects.

Preventing delays