Micron's next-generation 3D NAND, which will enter mass production in 2H 2027, is set to offer three significant advantages: it will double storage density, increase I/O performance by 50% compared to the company's current-generation NAND memory, and decrease power consumption, the company revealed at an event this week. To achieve these aggressive goals, Micron plans to take a page from YMTC's book and adopt wafer-on-wafer bonding. Meanwhile, Micron is also developing new materials and denser memory cell architectures to extend 3D NAND scaling beyond G11.

"We had mentioned we will bring in wafer-on-wafer bonding technology at the right time when it’s cost-effective, and it brings in capability that is important for the product specs at the time, and this is the right timing for that technology," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event this week. "So this G11 technology is the world's most advanced NAND. It will ramp in the second half of next year, [and] it is based on wafer-on-wafer bonding technology."

G11: Over 400 layers and wafer bonding

Micron's G11 3D NAND represents a substantial advancement over its current G9 (N160) generation. The company expects the new memory to achieve approximately twice the bit density of G9 (3D TLC 21 Gb/mm² => 3D TLC 42 Gb/mm²?), which means a dramatic increase compared to Kioxia's BiCS10 or Samsung's V10; increase I/O speeds by up to 50% (3,600 MT/s => 5,400 MT/s?); and reduce data transfer energy consumption per bit by more than 25%.

These improvements should benefit both conventional high-capacity SSDs for client and data center applications and emerging AI-oriented storage devices, which require greater bandwidth and energy efficiency.

One of the key changes introduced with G11 is wafer-on-wafer bonding, which enables Micron to manufacture different parts of its NAND device on separate wafers using different process technologies — a new 3D NAND node to build a NAND array and a logic fabrication process to make peripheral circuits and I/O — and subsequently bond them together. The company has used CMOS-under-array architectures for several generations. Still, wafer bonding provides additional flexibility to optimize memory arrays and peripheral logic independently, which means more capacity and performance if all goes as planned.

Another important innovation is the transition to more than 400 NAND layers. Micron has not disclosed the exact number of active wordline layers or the number of memory decks used by G11, but the company says the technology will feature an industry-leading memory cell pitch, which suggests that its density improvements will come from both additional layers and smaller cell dimensions.

Micron expects to disclose more technical details about G11 in 2027, closer to the start of high-volume manufacturing in the second half of next year.

Beyond G11: New materials and denser memory cells

Without any doubt, Micron will continue scaling 3D NAND along all three dimensions rather than simply increasing the number of layers going forward. While conventional 3D NAND scaling initially relied primarily on adding more memory layers, future generations will also require reductions in cell dimensions along the X and Y axes to improve bit density while keeping manufacturing complexity in check.

To achieve this, Micron is developing what it describes as breakthrough high-mobility materials, ultra-dense cell architectures, and more energy-efficient devices and data paths. These technologies could improve transistor characteristics, enable further reductions in memory cell dimensions, and reduce the energy required to move data within NAND devices.

"Beyond G11, we have a strong roadmap, not going to go into great detail on it today, but really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward," said DeBoer. "[…] The current industry direction and Micron’s direction is scaling both by adding layers [and] also by shrinking the cell dimensions."

The company has not disclosed specific architectural details, density targets, or production schedules for its post-G11 generations, though its roadmap suggests that future NAND scaling will increasingly depend on innovations in materials, cell architecture, and peripheral circuitry rather than layer-count increases alone. Meanwhile, since the number of active layers is arguably the easiest way to increase storage density, we would not expect the race towards the highest layer count to slow down substantially in the coming years, especially given strong demand for 3D NAND-based storage.

DRAM featuring 4F² memory cells has long been considered one of the holy grails of the DRAM industry, as they promise to reduce cell area by 33% compared with conventional 6F² designs and therefore enable building DRAMs with more memory cells in the same area. However, after working on 4F² memory cells for a couple of decades, Micron has concluded that the architecture offers no meaningful density advantages, increases manufacturing complexity and costs, and has fundamental scaling limitations. This has a dramatic impact on Micron's future plans.

"Micron invented 4F² DRAM," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event on Wednesday. "The path with 4F² DRAM is always been an option through time, and we have evaluated it and not pursued it due to increased complexity and cost through this past two-decade period of time."

Interestingly, both Samsung and SK hynix still have 4F² memory cells in their roadmaps (according to TechInsights), so Micron's rejection of the technology puts the company on a unique trajectory. Several years ago, the company delayed integration of EUV lithography into its manufacturing flow, contrary to what its rivals did, and still managed to retain competitive positions both in terms of costs and in terms of performance. Therefore, skipping 4F² memory cells is not completely surprising.

4F² is not the future of Micron's DRAM

The main attraction of 4F² DRAM is its theoretically smaller memory cell. The 4F² naming refers to a cell area equivalent to four times the square of the minimum lithographic feature size (F), compared with six times F² for conventional DRAM.

At identical feature dimensions, a 4F² cell occupies approximately 33% less area than a 6F² cell, which could theoretically increase the number of memory cells per wafer by 50%. Such an improvement would reduce manufacturing costs per bit and increase per-device memory capacity even without an equivalent reduction in feature dimensions. However, to make these advantages possible, DRAM makers must develop a suitable transistor architecture and a sufficiently compact capacitor arrangement. This is not easy at all.

The CTO of Micron says that the theoretical advantages of 4F² DRAM do not necessarily translate into higher memory density in practice. DeBoer explained that dimensions and pitch of DRAM capacitors, rather than the nominal area of DRAM transistors, ultimately determine how many memory cells can fit on a wafer. Both 4F² and 6F² transistor structures must fit beneath the capacitors, which means that reducing transistor area alone does not guarantee a corresponding reduction in overall cell size because transistors need a capacitor. Furthermore, Micron believes that 4F² introduces additional manufacturing steps and complexity that increase costs without delivering sufficient benefits.

"It is important to understand the capacitor pitch, the capacitor size, and dimensions, is what sets the DRAM bit density, not whether it is 6F², 4F², 8F²," DeBoer said. "From our investigation of this technology over the past couple of decades, it is a bit of a myth that 4F² actually provides anything versus 6F². It is capacitor pitch that defines the DRAM. You can build the cells, the transistors underlying them in different ways, but they still have to fit under the capacitor pitch, which sets the DRAM [cell size]. So, some of that is just smoke and mirrors in terms of talking about 6F² versus 4F²."

4F² memory cells may curb new process technologies

Instead of adopting the 4F² DRAM cell architecture, Micron plans to continue scaling conventional 6F² DRAM. The company believes it can increase bit density by reducing capacitor pitch and shrinking process technologies even without introducing a fundamentally different transistor architecture.

Advanced lithography, new materials, and wafer bonding should allow Micron to extend planar DRAM scaling for several more generations, according to the company. For example, its upcoming 1δ process technology, scheduled to enter volume production in the second half of 2027, promises a mid-20% improvement in bit density compared with its predecessor. Micron also plans to adopt High-NA EUV lithography for future DRAM generations.

Interestingly, DeBoer fully acknowledges that 4F² DRAM is technically feasible and that Micron itself has manufactured experimental devices based on the architecture. However, its manufacturing complexity and costs become increasingly problematic as feature dimensions shrink, so essentially Micron claims that it can either adopt 4F² or use more sophisticated process technologies, a claim that perhaps implies why China-based CXMT recently praised 4F². Although DeBoer did not identify any specific physical limitations involved, he stated that 4F² has no sustainable scaling path beyond a certain point. This suggests that Micron sees little value in introducing an intermediate architecture that would eventually require another major transition.

"When you look at a scaling path, you can go back a few nodes and absolutely, 4F² can be built back a few nodes, no question about it," DeBoer noted. "It is more complicated, it is more complex, it is more costly, but you can do that. When we look at scaling 4F² beyond where we are sitting today, there it is; it is physics. There are fundamental problems with 4F² scaling that ultimately will lead to 3D DRAM coming in instead of 4F²."

3D DRAM is the future

Indeed, Micron's preferred long-term solution is 3D DRAM, which would increase memory density by stacking memory cells vertically rather than relying exclusively on reductions in their lateral dimensions. Alongside development of multiple next-generation planar DRAM process technologies, the company is already developing multiple generations of 3D DRAM production nodes (which is not surprising, as 3D NAND nodes will rely on fundamental innovations developed for planar processes), although it has not disclosed when the new architecture will enter commercial production. DeBoer indicated that Micron will make the transition when 3D DRAM offers the right combination of density, manufacturing complexity, and cost.

Although both Samsung and SK hynix have 4F² DRAM products in their roadmaps, Micron believes that the assumption that reducing the nominal footprint of DRAM cells improves manufacturing economics is wrong and that extending 6F² scaling and eventually adopting 3D DRAM offers a better long-term strategy.

Micron faces a one-day labor stoppage at its Taoyuan operations in Taiwan on October 22, Reuters reports. Micron's employees are striking for concrete terms for this year's bonus and a clearer mechanism for sharing the company's future profits. The strike's teeth come from the resultant financial impact on Micron's operations, as semiconductor fabs are supposed to operate around the clock. The scheduled protest comes amid strong demand for memory chips and will have a minor impact on Micron's memory output.

The Taoyuan union wants Micron to present a specific proposal for this year's additional employee bonus and establish a transparent formula for distributing a portion of future profits. Previous negotiations between the company and the union ended unsuccessfully in September, which prompted employees to approve industrial action in early October. Nonetheless, the union stresses that the October 22 strike is intended to pressure Micron into reaching an agreement rather than terminate negotiations. The union is prepared to conclude a deal if the company presents terms acceptable to employees across its Taiwanese operations.

The situation could become more serious if employees at Micron's Taichung operations, its largest manufacturing site in Taiwan, decide to join the action. A separate labor organization that represents workers at that facility is scheduled to meet with Micron for mediation on October 22, the same day as the Taoyuan protest. However, the Taichung union has not yet authorized a strike.

Micron's fabs in Taiwan produce commodity DDR5 and LPDDR as well as expensive high-bandwidth memory (HBM) for AI accelerators. Amid record demand for memory of all types, even a one-day suspension of operations would have a material impact on Micron's output and earnings.

Modern semiconductor fabs are supposed to work 24/7/365, as many processes cannot be halted. However, if management has sufficient time and personnel to prepare, a one-day warning strike does not necessarily mean a complete shutdown of Micron's Taoyuan manufacturing operations, not to mention permanent damage to wafers or equipment. The actual consequences of the strike will depend on employee participation, which manufacturing operations are affected, and Micron's contingency plans. While it is likely that the output will drop, the decline will likely be negligible.

Micron employs approximately 15,000 people in Taiwan. The workers point to compensation arrangements at Samsung Electronics and SK hynix as examples of how semiconductor manufacturers can distribute profits among employees as AI-driven demand generates unprecedented cash flows for memory firms.

Elon Musk has criticized memory makers for what he calls 'extortionate' pricing amid an unprecedented shortage of both conventional DRAM and high-bandwidth memory (HBM). Although Musk did not identify the companies he criticized, his remarks seem to be directed at Samsung Electronics and SK hynix, as he praised Micron for its more 'reasonable' approach at the same time. Interestingly, Micron also enjoys exceptionally high profitability: its latest quarterly gross margin reached 81%.

"Micron has been reasonable regarding future memory prices, while others have been extortionate, which is something today's customers will not forget," Musk wrote in a post on X. "Micron is making the smart move for long-term customer loyalty."

Musk did not provide specific details of said extortionate pricing or disclose terms offered by different memory suppliers (which tend to be confidential). Consequently, it is impossible to determine whether Samsung and SK hynix charge substantially more than does Micron for comparable products. Nevertheless, Musk's remarks suggest considerable frustration with the pricing policies of South Korean memory manufacturers.

Over the past several quarters, memory has transformed from an easy-to-obtain commodity to a strategic asset, and makers of 3D NAND and DRAM have certainly benefitted massively from this shift. Historically, memory makers have responded to strong demand and rising prices with aggressive capacity expansions, which eventually led to oversupply and falling prices. This time around, however, manufacturers have raised memory prices severalfold without comparable increases in production capacity. As a result, supply still lags behind demand and will continue to do so for years to come, which puts further upward pressure on memory prices.

What makes Musk's praise of Micron particularly interesting is the company's financial performance, which clearly suggests that the company is taking advantage of the situation in the market. In its fourth quarter of fiscal 2026, Micron reported revenue of $54.23 billion and a GAAP gross margin of 81%, up from 40% a year earlier. The company's cloud memory unit earned $16.283 billion, and its non-GAAP gross margin totaled 83%; its core data center storage business sold goods worth $18.002 billion with a 90% gross margin; while sales of the automotive and embedded units totaled $6.824 billion with gross margins reaching 84%.

Perhaps the most surprising part of Micron's last quarter report was its mobile and client revenue of $13.114 billion and non-GAAP gross margin of 90%, which means that Micron earned higher profit selling memory and storage for client devices than it did for selling memory solutions for data centers. Such results clearly indicate that even supposedly reasonable memory prices can generate extraordinary profits in the current market.

Memory manufacturers are increasingly shifting toward long-term supply agreements (LTAs) that guarantee future supply and provide customers with predictable prices of DRAM, HBM, and NAND. So far, Micron has signed 26 strategic customer agreements that cover more than 35% of its expected revenue through 2030. These contracts include $32 billion in customer financial commitments, most of which consist of cash deposits. The company acknowledges that its new agreements reflect higher prevailing memory prices, and it by no means is trying to sell memory at a discount.

Samsung has reportedly secured long-term contracts covering 75% – 80% of its planned memory output in 2027, according to South Korea's ⁠Korea Economic Daily (via @Jukan05). SK hynix is reportedly pursuing similar arrangements as AI infrastructure investments continue to absorb available memory capacity.

Market insiders and analysts expect memory supply shortages to persist through at least 2028, and that gives manufacturers considerable leverage in contract negotiations. Memory suppliers have little incentive to reduce prices and are eager to enjoy their position, but Musk's warning suggests that today’s pricing policies could influence customer relationships once supply and demand eventually return to balance.

Micron released its fiscal Q4 2026 financial results on Wednesday, expectedly setting another record for revenue with $54.23 billion for the quarter, up nearly five times since the same period last year. Micron also hit a record 87% gross margin, the largest contributor to which was Micron's Mobile and Client (consumer) business unit. Further, Micron's client business was the only one that shipped less memory last quarter, despite bringing in the highest operating margin at 88%.

Micron's margins overall are up significantly year-over-year; Core Data Center surged from 25% to 85%, and Automotive and Embedded have climbed from 20% to 79%. The Mobile and Client unit also saw significant growth, with a 29% operating margin in fiscal Q4 2025, and now a margin of 88%. Cloud Memory margins grew, though not to the same extent as other units, moving from 48% to 76%.

The gross margins are interesting to look at, too. In a financial statement, the gross margin equals revenue minus cost of goods. Operating margin, on the other hand, equals revenue minus cost of goods and all other operational expenses. The operating margin simply excludes taxes and interest.

The gap between gross and operating margin is what's interesting in the breakdown above. The Mobile and Client unit has the smallest gap, with only a 2% difference. The Core Data Center unit matches the Mobile and Client unit with a 90% gross margin, but it has a lower operating margin at 85%. In other words, the cost of running Micron's consumer business is extremely low relative to the amount of revenue it currently generates.

It also saw the lowest amount of growth for the quarter, with revenue up 14% quarter-over-quarter. Micron says this was "driven by higher pricing, partially offset by lower bit shipments." Out of Micron's four business units, the Mobile and Client unit was the only one that shipped less memory in the past quarter.

For clarity's sake, a bit shipment is just a shipment. Micron measures shipments in bits rather than units. It's the capacity Micron has shipped in a quarter, not the actual number of DRAM or NAND chips.

Outside of Mobile and Client, Micron attributes higher revenue to higher pricing and bit shipments. The situation in the Mobile and Client unit echoes a sentiment we've heard elsewhere: growth in the consumer market is still happening, but it's driven by higher pricing, not growth in shipments.

Earlier this year, Intel's David Zinsner, chief financial officer, attributed a 13% YoY growth in Intel's consumer business to higher average selling price (ASP), not increased unit sales. Zinsner clarified that Intel "thought we had seen some inflation on our cost and needed to pass that on to the end customer."

Micron's outlook for fiscal Q1 2027 has revenue set at another record of $61.5 billion ± $1.5 billion, with gross margin rounding from 87% in fiscal Q4 2026 to 86.25%.

Another record quarter signals more squeeze on the DRAM and NAND markets. Echoing rival SK hynix, Micron says it expects memory and storage to be "much tighter" in 2027 and 2028, claiming that the company expects the industry to be supply-constrained in both years. That's despite a growth in supply that Micron anticipates.

The company says it expects industry NAND bit shipments to grow in the mid-20% range, and DRAM bit shipments to grow in the low-20% range. The industry broadly will produce more memory over the next two years, says Micron, but that still won't keep pace with demand.

Worrying still is this line in Micron's earnings slides: "we do not have line of sight to when supply and demand will return to balance." However, the company says it plans to increase its capital expenditure (capex) in fiscal 2027 compared to its prior estimates.

A "majority" of that increase is set aside for construction of additional clean room space, which Micron has set for 2028 through the end of the decade. Hopefully, that additional clean room space coming online will ease supply constraints, but we're still a long way from that point.

Micron said during its FY 2026 earnings call that RAM and storage chip shortages will worsen in 2027 and 2028, even as it announced a record gross margin of 86.25%. CEO and chairperson Sanjay Mehrotra said that the company has already sold most of its capacity for next year and that customers will have to pay more compared to 2026.

“In calendar 2027 as well as 2028, we see demand exceeding supply. In fact, we see greater tightness in the industry in 2027 and in 2028 versus 2026. Overall, supply-demand environment is only getting tighter,” Mehrotra said. “We do not have line of sight to when supply and demand will return to balance.”

The memory and storage industry is not holding back on increasing production, though, with Micron saying that NAND and DRAM shipments are expected to grow in the low-to-mid 20s percentage range for the next two years. However, it seems that this is not enough to match growing demand, as it expects “the industry to remain supply constrained in both years.” Still, it seems that manufacturers are prioritizing HBM demand for AI data centers, with the company expecting shipments of these chips to grow faster than conventional DRAM.

Micron and other chip manufacturers are bringing new factories online to increase output, but it’s going to take years before they can start producing chips. But even as we’re amid an unprecedented multi-year memory chip shortage, Micron also announced record financial guidance. It forecasted a record $61.5 billion FQ1 revenue and a gross margin of 86.25%, implying a gross profit of more than $53 billion. After accounting for an estimated $2.06 billion in operating expenses and a tax rate of around 15.5%, the company said its earnings per share sit at $38.15, plus or minus $1.00, for approximately 1.15 billion shares.

These are record numbers, but it’s not surprising given the amount of money being poured into AI data centers. It has gotten to the point where the memory workers from Samsung and SK hynix have demanded and received bonuses worth hundreds of thousands of dollars, with Micron’s workers in Taiwan threatening to strike if they do not receive a bigger slice of the AI pie. While this is good news for the average employee from these big companies, it’s unfortunately bad news for the average person who must pay for RAM and storage at higher prices.

Micron’s prediction goes directly against the Acer CEO’s prediction that PC prices will decline by late 2027, especially as Chinese RAM chips enter the market and consumers simply refuse to pay more for expensive memory chips. We can only wait and see which of these CEOs will be correct when it comes to DRAM and NAND pricing.

Micron this month filed a lawsuit against China's 3D NAND champion YMTC, accusing it of poaching its leading engineers, illegally obtaining its NAND memory know-how from them, and then using that information to build its own non-volatile memory as well as its patent portfolio. The Boise, Idaho-based company further alleges that YMTC uses patents granted to its former employees to accuse Micron of patent infringements in various jurisdictions.

To assemble a comprehensive IP portfolio that would cover everything from essential technologies to sophisticated manufacturing methods quickly, as well as to ensure that its patents overlapped with those of other 3D NAND manufacturers to enable it to attack Micron, the firm asserts YMTC opted for a rather simple, yet effective strategy: It poached engineers from Micron, then made them patent either standard essential inventions or inventions that closely resembled those they worked on while at Micron.

To leave Micron without being asked questions, its former employees cited a broad range of personal or family reasons for their resignations and even did not update their LinkedIn profiles to reflect their new roles at YMTC. These employees had confidentiality obligations that continued after termination of their employment and proscribed them from using, disclosing, or possessing Micron’s confidential information. Meanwhile, Micron did not really investigate the whereabouts of its former employees and "had no reason to suspect YMTC itself" of planning to use its confidential information because "YMTC did not have any material market share in the industry.”

We are all used to cut-throat competition on the memory market as leading producers of DRAM and NAND try to win market share from each other and maintain profitability at the same time. These companies have broad cross-licensing agreements to neutralize direct patent wars that can result in devastating injunctions that could paralyze fab operations and eventually lead to assured mutual destruction. However, this does not seem to be the case for emerging competitors from China, ChangXin Memory Technologies (CXMT) and Yangtze Memory Technologies Co. (YMTC), both established in 2016, which are increasingly attacking Micron in various courts, perhaps making pre-emptive strikes to avoid the destiny of their Chinese counterpart, Fujian Jinhua.

Using Micron's 3D NAND know-how against Micron

In its lawsuit against YMTC, Micron asserts that Yangtze Memory's patent campaign against Micron largely relies on patents that were granted to former Micron employees. Furthermore, Micron alleges that former employees brought its 3D NAND know-how to YMTC and subsequently developed patents covering related or overlapping technologies, which essentially means that Yangtze Memory has built its patent portfolio using Micron's intellectual property, which is why Micron claims that YMTC patents belong to Micron and therefore cannot be used against it.

"For example, these individuals include Daesik Song, Wenxi Zhou, and Hua Tan," Micron's lawsuit reads. "Each of these employees owed Micron contractual obligations to keep trade secrets confidential, had access to certain of the Micron Trade Secrets further described below while employed at Micron, and on information and belief, each joined YMTC shortly after leaving Micron. Each of these employees also regularly accessed one or more of the Trade Secrets that were located on servers in Boise by accessing Micron's highly confidential technical materials relating to its test and/or production nodes."

Micron's allegations in the new complaint go well beyond simple claims that its former employees brought manufacturing expertise to YMTC, something that happens often. The company alleges that YMTC systematically obtained confidential 3D NAND and memory technology from former Micron engineers and incorporated that knowledge into its manufacturing processes starting from its 64-layer 3D NAND, memory products, and, most importantly, its patent portfolio. Micron says it began to uncover the alleged scheme after YMTC sued it for patent infringement in California in November 2023, when it noticed that several patents asserted against it named former Micron engineers as inventors.

In its complaint, Micron identifies a number of its former employees who subsequently became inventors on YMTC patents, including Hongbin Zhu, Jun Liu, Yushi Hu, Qian Tao, Changhyun Lee, Daesik Song, Wenxi Zhou, and Hua Tan. According to Micron, these engineers had access to different classes of confidential technology that covered a broad range of 3D NAND-related know-how, including high-aspect-ratio etching, replacement gate processing, multi-deck connections, pillar shaping and cleaning, and memory I/O circuitry, among others.

Patent records independently confirm an important part of Micron's allegations: several former Micron engineers later became inventors in YMTC patents that YMTC eventually used against Micron. In general, this does not prove any misappropriation: engineers routinely change employers and continue to invent in their areas of expertise, but Micron alleges that some of these patents cover inventions conceived or developed while their inventors still worked for Micron, which is why it is asking courts to transfer ownership of these patents from YMTC to Micron.

One of the clearest examples involves Hongbin Zhu, who left Micron in September 2017 and subsequently became an inventor in numerous YMTC patent applications. One family originates from the international patent application PCT/CN2018/101482, filed on August 21, 2018, and includes three patents. Micron's complaint alleges that these patents relate to technology Zhu 'learned of, worked on, and/or conceived while at Micron' and asks the court to transfer their ownership from YMTC to Micron. The same family also includes two additional patents that YMTC asserted against Micron in its California infringement lawsuit. Micron has already challenged ownership of these two patents in that litigation and claimed that Zhu invented the underlying technology while employed by Micron and had assigned his rights to the company.

Daesik Song provides another connection between Micron's allegations and YMTC's patent enforcement campaign. Song previously worked at Micron on memory I/O technology and later became an inventor on a patent titled 'Double Data Rate Circuit and Data Generation Method Implementing Precise Duty Cycle Control.' YMTC asserted the '851 patent against Micron in the Eastern District of Texas, yet Micron now alleges that it is actually the rightful owner of the patent because Song's invention-assignment agreement transferred inventions conceived during his Micron employment to Micron. The company is therefore asking the Idaho court to transfer legal title to the '851 patent from YMTC to Micron.

The Song connection also extends beyond the United States. In Europe, YMTC owns European patent EP 3 909 047, which covers the same invention as the '851 patent, and uses it against Micron in its UPC in Düsseldorf and U.K. litigations. Thus, YMTC is enforcing different members of the same invention family against Micron in Texas, the UPC, and the U.K. while Micron alleges that the U.S. patent from that family actually belongs to Micron. That does not automatically mean Micron owns the EP '047 since the U.S. and Europe are different jurisdictions, but it demonstrates how Micron's ownership allegations intersect with YMTC's international patent campaign.

There are additional connections. Former Micron engineers Yushi Hu and Qian Tao are named as inventors on two patents that YMTC asserted in California, while Jun Liu, Qian Tao, and Yushi Hu are all inventors on another patent asserted against Micron there. Changhyun Lee is an inventor on US 11,468,957, also part of YMTC's California case. Meanwhile, Wenxi Zhou appears on a YMTC patent family that covers barrier layers for word-line contacts, including US 12,094,767.

The European cases provide a somewhat narrower connection. Of the three European patents YMTC is asserting through the UPC and UK proceedings, EP 3 909 047 is directly relevant because it names former Micron engineer Daesik Song. The other two — EP 3 850 660, which names Qinxiang Wei, Jianhua Sun, and Ji Xia, and EP 4 236 650, which names Zilong Chen and Xiang Fu — do not name any of the former Micron engineers identified in Micron's complaint. Meanwhile, YMTC has also filed eight patent cases against Micron in China, three in Beijing and five in Shanghai, although we have not found a reliable public list of the eight Chinese patents involved, so it is not yet possible to determine whether they include Chinese patents of YMTC's inventions in the U.S. and Europe.

To sum up, the list of patents and YMTC engineers reveal a much more complicated dispute than an ordinary patent fight between two memory manufacturers. In less than a decade, YMTC has built an international patent portfolio and is attempting to enforce it against Micron across the United States, China, Germany, the UPC, and the U.K. Several of the patents used in that campaign are assigned to engineers who previously worked for Micron. Furthermore, Micron now alleges that at least some of those inventions were conceived while at Micron or using its trade secrets, so at least in some cases these patents belong to Micron, according to the company's complaint.

In short, Micron's main allegation is not that YMTC obtained its manufacturing know-how through former employees, but that some of this know-how was ultimately converted into YMTC intellectual property that YMTC later used to sue Micron itself. Hence, if Micron proves to the courts that YMTC's inventions are in fact Micron's inventions, then the whole Yangtze Memory campaign falls apart. However, the decision by the Munich I Regional Court looks rather alarming for Micron, as the company has so far failed to persuade the court that it not only did not infringe any YMTC patents, but that the very patents in question were obtained illegally.

All-out war

YMTC sued Micron in the Northern District of California in early November 2023, alleging that Micron's 3D NAND infringed eight U.S. patents. In early 2024, YMTC brought three additional patent cases against Micron in Beijing, then followed up with another California lawsuit in July that asserted another 11 U.S. patents against Micron’s 3D NAND and DDR5 products. In September 2024, YMTC expanded its Chinese campaign with five more patent cases in Shanghai. The dispute became global on October 6, 2025, when YMTC simultaneously launched another wave of litigation, asserting eight patents in the Eastern District of Texas, three patents in the U.K., three European patents before the Unified Patent Court in Düsseldorf, and five patents before the Munich Regional Court.

By then, what had begun as an eight-patent U.S. dispute had evolved into a multi-jurisdictional patent war covering dozens of patents and some of Micron's most important NAND products. Hence, Micron had to start responding. On October 18, 2024, the company filed a counterclaim alleging that it is the true owner of the US 10,879,254 and US 11,581,322 patents (more on this later). Then, almost two years after YMTC first sued Micron, the company filed the case on October 7, 2025, asking the U.S. District Court for the Northern District of California to issue a declaratory judgment of non-infringement concerning YMTC patents, which essentially means that Micron asked the court to rule that its patents did not infringe certain YMTC patents. These actions were barely a defense from YMTC's all-out patent war.

However, having spent nearly three years primarily defending itself and challenging YMTC's patents, Micron decided to respond more vigorously, which it did in its lawsuit filed with the Boise, Idaho, court on September 15. In the new lawsuit, Micron alleges that YMTC systematically obtained Micron's 3D NAND manufacturing know-how through former Micron engineers and then incorporated that information into both YMTC's manufacturing processes (64-layer, 128-layer, 232-layer, and subsequent nodes) and its patent portfolio. The alleged trade secrets cover multiple aspects of contemporary 3D NAND production, including high-aspect-ratio etching, replacement gate processing, multi-deck connections, pillar formation, and other manufacturing techniques.

Micron claims that its former employees who had access to this information later worked on similar technologies at YMTC and became inventors in YMTC patent applications. More importantly, some of these patents or their family members were subsequently used by YMTC against Micron, which essentially means that YMTC used patents granted to Micron's former employees against Micron itself. In many cases, YMTC allegedly poached Micron engineers who had previously developed and patented certain technologies at Micron, then tasked them with working on similar technologies and filing new YMTC patents covering essentially the same technical solutions. As a result, Micron now claims that several of the underlying inventions actually belong to it.

Back in Europe, Micron launched its own patent offensive against YMTC and companies that sell products which allegedly use the disputed technologies. In July, Micron sued YMTC in the Munich Regional Court, where it named Apacer, Lexar, and Ultron as co-defendants. In addition, it took a separate U.K. High Court action targeting YMTC alongside its partners Apacer, Lexar, and TeamGroup (note that TeamGroup is one of the SSD makers that from time to time uses different memory and even controllers on the same SSD models).

The German ruling

Before we proceed with a rather unprecedented decision of the Munich I Regional court, let us explain the difference between the patent and utility model as neither the U.S. nor the U.K., nor Canada, support the utility model system.

A patent protects major technical inventions across process technologies, tools, and materials for up to 20 years, but it requires a rigorous step-by-step patent office examination that typically takes years and significant expense to obtain. By contrast, a utility model protects incremental, practical mechanical or structural improvements to physical products for a shorter duration (usually 5 to 10 years). It is granted rapidly within months and at a fraction of the cost because it involves a lower inventive threshold and skips substantive examination prior to registration. While most patent offices register utility models without checking whether the idea is actually new, the validity of a utility model remains uncertain until enforcement. This is where YMTC prevailed to a degree that nobody expected.

In fact, YMTC has so far failed to gain any substantial court victory in the U.S., but it scored its first major victories in its German litigation against Micron in September, when the Munich I Regional Court ruled that Micron infringed two YMTC German utility models and granted injunctions against the company. The two utility models — DE 20 2020 006 166 U1 and DE 20 2021 004 551 U1 — cover 3D NAND-related to staircase structures and barrier layers for word-line contacts, respectively. The injunctions prohibit Micron from offering and selling products that infringe the two utility models in Germany. Meanwhile, the court has adjourned decisions on three infringement actions: it did not reject the other three, but simply has not resolved them.

Normally, this would not be a problem for Micron's clients, as unlike injunctions by the U.S. ITC, these rulings in the European Union typically have no effect on downstream entities, so Dell, Lenovo, and other PC OEMs can continue selling PCs containing violating hardware. However, it is possible that this particular decision could affect Micron's downstream partners, effectively prohibiting them from selling systems with Micron's 3D NAND inside. As a result, the injunctions could disrupt sales of PCs, SSDs, servers, and other products containing the affected Micron NAND in Germany.

Micron has appealed the decisions and is challenging the validity of the rights, so the September rulings represent first-instance victories for YMTC rather than the end of the dispute. Three other Munich cases brought by YMTC — including one that involves a European patent — have not yet produced infringement decisions. Yet, the existing decision shows that courts can side with Yangtze Memory and rule that Micron uses YMTC's intellectual property illegally.

Normally, this would be a 'local' problem for Micron. However, it is important to mention that some of the technologies and patent families involved in the European litigation overlap with those asserted in the United States. Several of them name former Micron engineers as inventors.

In fact, both German utility models on which YMTC just won injunctions appear to belong to patent families that involve former Micron engineer Wenxi Zhou, with corresponding U.S. patents being used by YMTC against Micron in Texas. This becomes particularly important in light of Micron's new allegations that former employees brought its 3D NAND know-how to YMTC and subsequently developed patents covering related technologies. If YMTC can win a litigation in Germany, can it also prevail elsewhere using the same patent families?

Summary

The conflict between Micron and YMTC emerged amid the escalating U.S. – China semiconductor confrontation. In October 2022, the U.S. imposed sweeping restrictions on exports of advanced semiconductor manufacturing equipment and technology to China, and in December 2022, the U.S. Department of Commerce added YMTC to its Entity List, which severely restricted the company's access to American fab tools. China responded with pressure on Micron: in May 2023, the Cyberspace Administration of China concluded that Micron had failed a cybersecurity review and prohibited operators of critical information infrastructure from purchasing affected Micron products.

The commercial conflict between the two memory makers eventually moved into the courts, with YMTC accusing Micron of patent infringement and Micron largely defending itself rather than launching a comparable patent offensive of its own. Micron’s new complaint in Boise, Idaho, may explain this strategy: the American memory maker not only seeks to defend itself against YMTC's infringement claims, but also alleges that some of the patents YMTC is using against it incorporate Micron’s confidential technology or actually belong to Micron itself. But while Micron can potentially prevail in the U.S. and perhaps in Europe and the U.K., China represents a different challenge, as the legal battle between the two memory makers may well be considered a part of the broader geopolitical confrontation between the U.S. and China.

Micron is reportedly pulling the plug on its 2 GB (16Gb) GDDR7 memory chips, ending production and sales of both the 28 Gbps and 32 Gbps variants. According to an X post by UNIKO’s Hardware, the chips — some of which shipped on some GeForce RTX 50 graphics cards — are now designated as “End of Life” on Micron's site. Tom’s Hardware can confirm that the pages for module norms return “No results found.”

Micron just began supplying its 2GB GDDR7 to Nvidia earlier this year, with Samsung and SK Hynix being the main GDDR7 suppliers. As a result, Micron's 2GB module only shipped on a few Nvidia models, such as retail variants of the GeForce RTX 5060. Samsung and SK Hynix cover the vast bulk of 2 GB GDDR7 modules for the standard RTX 50 retail lineup, so the risk of immediate shortages is minimal. Micron’s uncompetitive position in the 2 GB segment also appears to have made a fast exit logical to free up fabrication capacity.

The company is reportedly shifting its focus toward higher-density 3 GB (24 Gb) GDDR7 chips. These larger packages are considered impractical for Nvidia's RTX 50 lineup because they are more expensive and result in less conventional consumer memory capacities. However, they yield higher profit margins and are actively utilized in Nvidia's high-end RTX PRO Blackwell GPUs tailored for generative and agentic AI workloads.

Micron’s decision follows the ongoing trend of memory suppliers prioritizing AI-facing technologies over their consumer and retail counterparts. The company exited its Crucial consumer memory and SSD business earlier, explicitly saying that surging AI data-center demand had prompted it to prioritize larger strategic customers in faster-growing segments.

A court in Germany has granted court injunctions against Micron, marking a win for YMTC on the European/German front in the 3-year legal war between the two companies over memory technology patents.

According to a Digitimes report, the court ruled on Sept. 18 that Micron did infringe YMTC’s 3D NAND technology patents in two instances. The injunctions could restrict Micron’s supply in Germany and impact the broader European NAND market. Micron said it disagreed with the court ruling and has already filed an appeal. It is also challenging the validity of the related patents in separate legal cases across various countries.

YMTC filed the lawsuit that won the recent injunctions in late 2025 at the Munich 1 Regional Court, opening five cases involving four German utility models and a European patent. The court granted injunctions on two of the utility models with 10-year protection periods — DE202020006166U1 (case No. 7O12615/25) and DE202021004551U1 (case No. 12614/25) — and adjourned the others. The injunctions are only first-instance rulings and can be suspended if Micron successfully appeals at the Munich Higher Regional Court.

The ruling is the latest development in a years-long dispute between the two memory makers that started in 2023 when YMTC sued Micron in California, alleging violations of eight 3D NAND architecture patents. The dispute has since snowballed into a multi-front war involving over 20 patents, with suits and countersuits on both sides. The cases cover patent infringement, declaratory judgment, spyware, libel, false advertising, and invalidation actions, and have been filed in courts across China, the U.S., the U.K., Germany, and in other parts of Europe.

Micron has vehemently denied any wrongdoing and has filed multiple patent invalidation challenges since 2024, the first of which came after YMTC dragged the company to court in China over related issues. Seven of the disputed patents have already been declared invalid, and Micron has said it will continue pushing to safeguard its intellectual property.

3D NAND is a flash-memory storage technology that stores data in products ranging from smartphones and SSDs to enterprise storage systems. Unlike older planar NAND, where memory cells are arranged side by side on a flat surface, 3D NAND stacks cells vertically in multiple layers, allowing manufacturers to pack more storage into a given area while increasing density and lowering cost per bit. Modern NAND chips can contain hundreds of these layers, making the architecture and manufacturing techniques behind them commercially valuable intellectual property.

The Micron-YMTC fight is playing out against the backdrop of the much larger technology dispute between the U.S. and China. Washington has tightened restrictions on China's access to advanced semiconductor manufacturing equipment and other chip technologies, while Beijing has placed export restrictions on many critical raw materials.

Memory prices are at record highs due to demand from the AI sector and are not going to drop any time soon. In fact, the cost of manufacturing memory chips on a per-area basis can be higher than the price of silicon processed using TSMC's N2 and N3 fabrication technologies, which are used to make compute chips, according to an observation made by Kurnal Insights. While the comparison has merit, it has an important caveat.

Based on media leaks, Kurnal from Kurnal Insights considers that a 300-mm wafer processed using TSMC's N3 technology costs $20,000, which translates to approximately $0.283 per mm² when the wafer price is divided by its area. For TSMC's N2, the analyst assumes a considerably higher wafer price of $30,000, or around $0.424/mm². These calculations are based on unofficial information and do not account for unusable wafer edges, dicing, test structures, defects, or yield, so they should be viewed as nominal wafer-area prices rather than the actual price of usable silicon.

The calculation for DRAM works differently. Kurnal assumes a DRAM price of $1.50 per Gb and then multiplies it by the bit density of different generations. At 0.219 Gb/mm², 1y DRAM works out to $0.329/mm², whereas 1z DRAM with its 0.273 Gb/mm² density reaches $0.410/mm². Finally, 1b DRAM at 0.436 Gb/mm² produces a figure of $0.654/mm², considerably higher than the nominal $0.424/mm² calculated for an N2 wafer.

There is an important distinction here. The N2 and N3 numbers represent assumed prices charged by TSMC for processing a wafer, whereas the DRAM figures represent the potential selling value of the memory contained within a square millimeter of silicon, thus illustrating how much revenue a DRAM maker can theoretically get from a given die area at the assumed memory price.

Interestingly, Kurnal Insights' $1.50/Gb assumption is almost exactly in line with the current spot price of DDR5 eTT memory. According to DRAMeXchange, 16Gb DDR5 eTT chips carried a session-average price of $24.80 on September 21, equivalent to $1.55/Gb. At that price, 1b DRAM with a density of 0.436 Gb/mm² would be valued at approximately $0.676/mm², just 3% above Kurnal's $0.654/mm² estimate.

It goes without saying that producing DDR5 memory is considerably cheaper than making logic chips using TSMC's N3 process technology. However, with DRAM in short supply, memory makers are getting considerably more money for their silicon than they did historically.

There are a few important caveats that make the comparison somewhat less straightforward. The calculations do not account for packaging costs, with logic requiring more expensive techniques. Additionally, TSMC manufactures chips on a contract basis, and the actual price of a processed wafer depends on the volumes, customer, and other commercial terms. Thus, comparing estimated TSMC wafer prices with DRAM spot prices is not exactly an apples-to-apples comparison. Even TrendForce notes that DDR5 spot procurement remains limited and transactions are sporadic, which means spot prices do not necessarily reflect the prices at which Micron, Samsung, and SK hynix sell the bulk of their DRAM.

Therefore, contract DRAM prices would provide a considerably better basis for an economically meaningful comparison. However, we do not know contract prices, and while they are clearly higher than historical memory prices, they may not be as high as spot prices. To that end, we cannot state for sure that DRAM makers get more money for their wafers than TSMC does for its logic wafers.

Even as chipmakers race to build the most advanced chips inside the United States, experts are saying that their efforts are facing one monumental challenge: a massive shortage of skilled workers to run the fabs and factories. According to CNBC, global consulting firm McKinsey and the SEMI Foundation suggest the industry will have up to 157,000 positions that could remain unfilled by 2030.

“I’m concerned,” Samsung semiconductor division EVP Jon Taylor told CNBC in an interview. “We just don’t see that there’s enough technical people in the pipeline.” The McKinsey report says that only 3% of U.S. engineering graduates end up working in the semiconductor industry, and that 73% of chip companies are finding it hard to fill engineering roles. This is a huge contrast to other tech jobs, which saw record layoffs by June of this year, when over 40,000 positions were axed, ostensibly largely due to AI.

The massive demand for memory and storage chips driven by the AI boom, combined with Washington’s efforts to bring semiconductor manufacturing back to the United States, has led to the buildup of multiple fabs and facilities dedicated to it. TSMC was one of the first companies to kick off this building spree, when it started construction on its Arizona campus in 2021. The site started churning out chips last year, with the company committing another $100 billion in July 2026 to build four more 2nm fabs. Intel’s Ohio One plant, which was, at one point, America’s largest fab complex, is also underway, with the site expected to start production between 2030 and 2031.

The big three memory makers — Micron, Samsung, and SK hynix — are also planning or have recently completed major expansions in the U.S. Samsung is starting advanced semiconductor manufacturing in the U.S., with its Taylor, Texas, fab entering risk production this year. The fab is targeting an output of 50,000 wafer starts per month, and it is expected to create 3,500 jobs. “We’re hiring engineers, we’re hiring technicians, we’re hiring people in the supply chain,” Taylor told the publication. “Everybody wants and needs the same thing, and it’s a bit of a race against time right now as everything is starting to come online.”

Micron is also currently building its Boise, Idaho, memory chip fab, which began construction in 2022 and is projected to begin wafer production by 2027. The company has also formally broken ground on its $100-billion New York “megafab,” with aims to produce 40% of its global output within the U.S. by the 2040s. Aside from these massive manufacturing sites, it has also committed $10 billion toward new research labs in the U.S., to be built near the global Micron R&D center in Boise.

Finally, SK hynix also started construction of its first HBM plant in the U.S., with its West Lafayette, Indiana, campus dedicated to packaging these crucial components for AI data centers. There have also been rumors that the South Korean company is in talks with Intel to either lease space at its Ohio One factory or launch a joint venture alongside other AI hyperscalers to build memory chips in the U.S.

All these construction projects, plus the requisite supply chains, will necessitate thousands of workers. Local universities like Purdue University and Arizona State University are already investing millions of dollars to help prepare a capable workforce, with the former launching degrees in 2022 focused on semiconductors. Samsung and Intel are also investing in various programs, including internships and scholarships, to help secure a future workforce for the companies.

However, salary is one major concern listed by the SEMI Foundation. U.S. chip fabs typically pay $127,000 to $187,000, with senior staff getting $238,000 or more. While this is a more-than-competitive salary in the U.S., it’s dwarfed by the bonuses recently offered by Samsung and SK hynix in South Korea, which have reached hundreds of thousands of dollars. With the projected worker shortfall, we should expect the job offers from these semiconductor companies to catch up with their eastern counterparts if they want to secure and maintain talent here in the U.S.

Micron this week introduced its first 512GB DDR5-9200 memory module that is designed for servers used for applications that demand a lot of memory. The new modules — which are currently being validated by AMD and Intel with their next-generation server platforms — will enable server makers to build machines with up to 12TB of fast memory. What remains to be seen is the price of such modules and servers.

To build its 512GB DDR5 RDIMM, Micron uses advanced packaging that stacks multiple DRAM dies vertically and connects them using through-silicon vias (TSVs). The company does not disclose which memory devices and how many of them it uses, but claims that a single 512GB RDIMM consumes over 60% less operating power than four 128GB modules — based on 16.0W for one 512GB module compared with the 44.2W total for four 128GB modules — which suggests that we are dealing with fairly advanced ICs.

Micron's 512GB module is not the industry's first 512GB DDR5 RDIMM — that achievement belongs to Samsung — but it is certainly the industry's first 512GB module certified to operate with a 9200 MT/s data transfer rate with standard 1.1V voltage (which implies on usage of Micron's 16Gb DDR5-9200 devices made on its 1γ (1-gamma) fabrication process that uses EUV lithography and consumes 20% less power than predecessors, though we are speculating).

Truth to be told, 512GB DDR5 memory modules are rather niche products, which is perhaps why Samsung's 512GB RDIMMs formally introduced in 2021 have not become widespread even after AMD and Intel introduced processors with over 100 cores. Micron positions its 512GB DDR5 RDIMM primarily for servers running analytics, in-memory databases, simulations, virtualization, agentic AI, and other workloads demanding high-core-count processors and plenty of memory. As processors with 200 or more cores emerge, 512GB modules may become more relevant as 12TB of memory in a server running two 256-core CPUs means 24GB per core, which no longer looks particularly excessive for applications like in-memory databases, analytics, or caching.

Micron claims that in memory-constrained Spark Support Vector Machine (SVM) analytics workloads, systems featuring 512GB memory modules can provide up to 1.4 times the performance of configurations equipped with 256GB DDR5 modules, though the company does not disclose how much memory in total these systems use. Micron also says the higher-capacity memory can increase throughput and concurrency for memory-intensive database and caching applications such as RocksDB and Redis.

AMD and Intel are working with Micron to qualify the new modules for their upcoming server platforms. Micron plans to begin volume production of its 512GB DDR5 RDIMMs sometime in the second half of 2027 and intends to align the schedule with customer requirements.

One of the more pressing questions about Micron's 512GB DDR5-9200 memory modules is their price. A 256GB DDR5-6400 RDIMM currently retails for around $19,000. Given the unique proposition that 512GB modules have for memory-constrained applications, such modules can cost significantly more than 256GB memory sticks, which will not help their broad adoption.

Micron has announced a one-time cash appreciation bonus of NT$1 million (US$31,650) as part of a broader compensation/reward package for its employees based in Taiwan. According to a Reuters report, the full package — which comes amidst ongoing disputes between the U.S. memory giant and its Taiwanese workforce — will see each employee earn a minimum of NT$1.7 million ($53,809.39).

The company called the payouts the largest rewards package in company history, confirming that more than 60,000 employees globally will receive scaled rewards for fiscal year 2026, “following an extraordinary year for the company.” Across the last four quarters, Micron’s cumulative net income from sales of high-demand memory chips has crossed a staggering $50.47 billion, with its Q3 earnings representing a 346% year-over-year increase. After the announcement, the union representing workers at Micron's Taoyuan plant officially rejected the company's bonus proposal, calling the package a distraction.

Under the announced payout, every Taiwan-based employee who joined the company on or before August 29, 2025, is eligible for the flat NT$1 million cash bonus. Those hired during fiscal year 2026 will receive a prorated amount. For direct manufacturing and production-line workers, the total bonus rewards are equivalent to 35 to 68 months of basic salary. Direct labor employees will receive a minimum total cash compensation of NT$1.7 million (US$53,809), while the average total compensation for junior engineers is projected to reach NT$3.4 million (roughly US$106,250), comprising NT$2.9 million in cash and the remainder in equity grants.

The announcement — which mirrors bonus payouts by Samsung and SK Hynix amid the soaring profits from the AI boom — comes after local unions in Taoyuan and Taichung, representing 10,000 of Micron's 15,000 Taiwan workforce, began threatening a strike on September 1, demanding packages similar to the payouts that will see Samsung employees receive over $300,000 in bonuses. The Taiwanese government stepped in to force a mediation. However, unlike in Samsung's case, which also involved government intervention that narrowly averted a potential strike, the talks fell through on September 4 after both parties failed to reach a consensus, leading Micron to announce the NT$1 million bonus package a week later.

In an official statement following Micron's announcement, the union said the new package "sidestepped" the real discussion about a transparent bonus system. The union is pushing for structural change, including a permanent profit-sharing model in which 15% of the company's operating profits are allocated directly to workers and distributed quarterly. They are also demanding a larger one-off payment equivalent to roughly 83 months of salary for fiscal year 2026. Last September, South Korea’s SK Hynix reached a settlement with its union to allocate 10% of annual operating profit directly to employees as performance bonuses for the next decade, eliminating bonus caps.

Similar incidents have played out across the semiconductor industry as companies continue to pull in unprecedented profits from the AI boom. Workers in these industries believe they should share in profits and are requesting concrete institutional safeguards to ensure they are fairly compensated during high-profit AI booms, rather than relying on arbitrary, opaque bonuses decided solely by management. Samsung's unions were ready to strike before reaching an agreement with the company and even held a demonstration attended by over 30,000 Samsung union members.

In the case of Micron — which announced a record-breaking GAAP net income of $28.24 billion in just Q3 2026 — the threat of a strike continues to loom following the Union’s rejection of its proposed payout. A critical second round of mediation is officially scheduled for September 21, 2026. If that upcoming meeting falls apart, the union plans to hold a vote allowing members to strike. In an earlier internal survey, 80% of union members voted in favor of a strike.

Micron Taiwan faces a potential strike as support for this labor action is increasing among its workers. Local media reports that a preliminary survey showed 80% of the people involved support such a move, with its labor union demanding that the current bonus system be replaced with a profit-sharing scheme, similar to what SK hynix employees receive. Micron, alongside Samsung and SK hynix, have been raking in a lot of cash because of the AI-driven memory chip shortage, and its workers want a piece of the action.

“Unions say peers offer far higher profit-based bonuses, with Samsung paying out 10.5% of profits and SK Hynix 10%,” Dan Nystedt said on X. “Formal mediation talks are expected to begin by mid-September at the latest, a mandatory requirement before an official strike vote can be held under Taiwan law.”

Earlier this year, Samsung narrowly avoided a strike after it agreed to a deal that gave its foundry workers bonuses that could go as high as $400,000 per employee. It seems that Micron Taiwan’s labor union is following suit, especially as the company’s last earnings call reported a revenue of $41.46 billion and a net income of $28.24 billion, with its Cloud Memory Business Unit, which provides high-bandwidth memory (HBM) to data center customers, accounting for more than 33% of the total revenue.

It’s unclear if Micron workers from other parts of the world will be affected by any deal made in Taiwan, but 60% of its global production capacity is centered around the island, with most of its HBM output coming from its facilities there. With the two sides beginning talks in September, we have yet to see what kind of deal they will reach. But given how lucrative the data center boom has been for the memory industry and the precedent set by workers at Samsung and SK hynix, it’s likely that they will have comparable demands.

While we’re unsure how much bonuses the workers in Taiwan will get, it’s likely that management will negotiate as production disruptions could mean massive losses for the company. Nevertheless, it would also raise complications for workers in other countries, as it could build jealousy and resentment among other workers who will not be part of the bargain, similar to what some Samsung workers are experiencing with the recently closed labor deal.

Memory and data storage manufacturer Micron announced its exit from the consumer market earlier this year and pledged to honor warranties for existing products. However, according to a recent RMA case on Reddit, the company seems to be struggling to stick to that promise. Instead of replacing a faulty portable SSD, the company offered the customer a refund that was significantly lower than the product’s current retail price.

Explaining their frustrating RMA experience, u/CarefulMeasurement99 said that their Crucial X9 4TB portable SSD stopped working, after which they contacted support, followed the troubleshooting process, and had their RMA approved. Unfortunately, they were later informed that the company did not have any units available for the particular product because the replacement inventory was exhausted. Therefore, instead of providing a 1:1 replacement SSD, the company would issue a refund of $199.99, the same as the original invoice price from last year.

Due to the ongoing NAND and DRAM crisis, almost every memory and storage product has significantly gone up in price. The Crucial X9 4TB is currently priced at over $500 on Amazon, which basically left the customer facing a loss of nearly $300. The customer explicitly refused to accept the offer and told Micron support that they did not want a refund and requested a 1:1 replacement under warranty. They also offered to accept an alternative 4TB SSD model or wait indefinitely until the RMA inventory was restocked.

After a long ordeal, pushing back eventually paid off for the customer. They sent Micron a firm final email rejecting the refund and demanding a 4TB equivalent replacement or alternative. The customer also mentioned that the case was gaining traction on Reddit and pointed out potential action under the FTC and Magnuson-Moss Warranty Act. Within a few hours, the case was escalated to a different representative, who informed them that a “recent inventory update” had revealed limited replacement stock and approved a direct 1:1 replacement.

While the case raises questions about Micron’s initial claim of no replacement units being available, there is no way to independently verify that. That said, this does not appear to be an isolated case. Earlier this month, we reported a similar RMA horror story in which Micron offered a customer a refund instead of replacing their product due to a lack of inventory. Only after further communication did Micron provide an acceptable solution.

Raghu Sreeramaneni, Micron HBM Design Architecture Fellow, told the Hot Chips 2026 conference on August 23 that the silicon penalty HBM carries against DDR5 is growing with every generation, and that it can’t be closed without giving up performance, something that Micron won’t do. Pressed on whether newer parts narrow the gap, he said it’s "definitely not getting better," putting the current overhead at roughly three times the wafer area of DDR5 for the same capacity. That trajectory is the reason why PC memory hit record prices this year, with conventional DRAM contract prices up 90% to 95% quarter over quarter in the first quarter of 2026.

Wafer mathematics

An HBM4 die fits 256 banks against 32 on a DDR5 die, and it reaches its bandwidth by running those banks in parallel, which requires far more die area for data paths, power delivery, and the through-silicon vias (TSVs) that link each layer to the base die. A single HBM3E die can feed 256 GB/s, while one DDR5 die supplies about 8 GB/s, so matching a given bit count makes the HBM die much larger.

Micron has publicly put that overhead at about three times the wafer area of DDR5, and Sreeramaneni said it traces to an HBM3E-against-DDR5 comparison that grows with each generation as pin speeds, bank counts, stack heights, and die sizes climb higher. He called HBM "probably the most cross-functionally complex solution that we make," and noted that in a two-GPU package, memory accounts for around 90% of the silicon, roughly eight times the area of the GPU dies. HBM already sells for about five times the price of DDR5 per bit, so each wafer a maker moves to it removes a disproportionate share of commodity memory from the market, pushing consumer product prices higher as a consequence.

Conventional DRAM contract prices rose 90% to 95% quarter over quarter in the first quarter of 2026 and a further 58% to 63% in the second. To put that into perspective, a mainstream 32GB DDR5-6000 kit sold for around $392 this month, up from $110 to $140 a year earlier, and 128GB of DDR5 passed $3,399, a 500% rise over 12 months, with European prices up 345% since September last year. Back in February, HP told investors that DRAM now makes up 35% of its PC build cost, up from 15% to 18% a quarter earlier, and Gartner expects PC shipments to fall more than 10% in 2026. While it’s true that the surge eased to 13% to 18% in the third quarter, that happened because consumer electronics makers reached the ceiling of what they could pass on, not because supply improved.

Bandwidth, stacking, and heat

Micron's presentation put compute performance scaling at roughly three times every two years and HBM bandwidth at under two times, a divergence Sreeramaneni summarized by saying "the memory wall is still present, and, in fact, maybe getting worse." HBM4 doubles the host interface to 2,048 I/Os, and Micron's parts run above 11 Gb/s per pin for more than 2.8 TB/s per stack, beyond the 8 Gb/s and 2 TB/s baseline in JEDEC's HBM4 standard.

Each of those gains comes from more parallelism, which enlarges the die again and widens the silicon ratio. Sreeramaneni said there is "a good path to 16 layers of DRAM," but "after 16, there's still a lot of work to be done." Meanwhile, SK hynix used its own Hot Chips talk to describe a 775-micron total-thickness ceiling that caps stacking until the industry adopts hybrid bonding, which SK hynix doesn't expect before HBM5. Micron's HBM4E, due around 2027, moves the logic base die to a TSMC foundry process, part of a wider shift toward customization as AI workloads fragment, which Sreeramaneni described by saying "disaggregation is the buzzword now."

The base die runs hottest because it sits at the bottom of the stack, doing the highest-speed interface work while the heatsink sits at the top. Every layer added between the base and the heatsink then raises thermal resistance. Sreeramaneni said Micron is now "architecting solutions around thermals rather than the other way around," a reversal from a few years ago. Micron highlighted how Meta's Llama 3 paper attributed 17.2% of unexpected interruptions during a 54-day run across 16,384 H100 GPUs to HBM3 memory, the second-largest cause behind failed GPUs, a reliability burden that scales with the amount of HBM in each package.

Share and supply outlook

SK hynix leads the HBM market with a share that Counterpoint Research places at around 58%, down from a high of around 69%, and Micron overtook Samsung for second place last year. Micron began volume shipments of 36GB 12-high HBM4 earlier this year for Nvidia's Vera Rubin platform, with Nvidia CEO Jensen Huang saying in June that all three suppliers are qualified and in production.

Analysts expect DDR5 per-wafer profitability to overtake HBM3E by the end of this year, leaving the three makers little reason to add commodity capacity when server DRAM pays nearly as well per wafer. SK hynix said last October that it had already sold its entire 2026 output, while Apacer's chief executive told investors that supply to independent module makers could fall to 30% of 2026 volumes next year. SK hynix CEO Kwak Noh-jung has called 2027 the worst year for memory supply in the industry's history, with demand outrunning production into 2030.

In response, Nvidia has raised its DGX Spark desktop from $3,999 to $4,699 and warned large customers of AI server price rises above 15%, both tied to memory. Realistically, the squeeze will loosen only under three conditions, none of them likely before new fab capacity comes online and scales up: China's CXMT ramping competitive DDR5 in volume, hybrid bonding arriving before HBM5, which SK hynix has already all but ruled out, or DDR5 profitability slipping back below HBM.

Full Micron Hot Chips 2026 presentation

The PCIe 6.0 specification was ratified in early 2022, but its actual implementation was delayed for years. Now, the spec is almost ready, with the first PCIe Gen6 platforms finally approaching, as are actual storage devices. Micron was the first with a PCIe 6 SSD in mid-2025, and Samsung caught up this July. Meanwhile, independent makers of SSD controllers — Marvell, Phison, and Silicon Motion — are also prepping their PCIe 6 SSD platforms.

For a full roadmap of PCIe, you can check out our dedicated page. In this article, we'll specifically focus on PCIe 6.0 controllers and devices and how they're soon becoming commercial products. For additional reading, you can also find our interview with Solidigm VP Avi Shetty, which covers the subject of PCIe 6.0 SSDs.

Per ardua ad astra

PCIe 1.0 through 5.0 used simple NRZ signaling (one bit per signal) with 128b/130b encoding, which was relatively simple to implement at the controller level. However, it required some complicated methods to ensure signal integrity at 32 GT/s per lane.

PCIe 6.0 now adopts PAM4 signaling (which encodes two bits per symbol using four voltage levels), which keeps the physical signaling rate at 32 Gbaud. However, it also doubles the effective transfer rate to 64 GT/s by transmitting two bits per signal instead of one. As a result, transmitter and receiver design became considerably more complicated, as it required sophisticated DSPs, equalization, FEC, and CRC-based retry mechanisms, which complicated the development of PCIe 6.0 controllers. Furthermore, PCIe 6.0 often requires retimers where PCIe 5.0 did not, which complicated the development of actual servers.

To make matters even more complicated, every new PCIe generation requires interoperability testing among CPUs, GPUs, SSDs, network cards, switches, retimers, and other devices from dozens of vendors. Since PAM4 behaves very differently from NRZ, PCI-SIG had to develop entirely new compliance procedures, test equipment, and interoperability programs. The development of those programs themselves slipped, which greatly delayed any commercial deployment. The very first PCIe 6 interoperability testing at 64 GT/s took place in late July.

Despite formidable implementation hurdles and interoperability program challenges, PCIe 6 is finally making its way into commercial platforms. AMD's 6^th Generation EPYC 'Venice' and Nvidia's Vera CPUs fully support PCIe Gen6, so companies from the adjacent industry sectors are catching up with their PCIe 6 products, and storage makers are among them.

For storage, PCIe 6.0 doubles host interface bandwidth to around 30.25 GB/s for a x4 link without the protocol's overhead (which is not that big with the 1b/1b 242B/256B FLIT encoding featured by PCIe 6). The new interconnect does not improve flash operation on its own. Meanwhile, PAM4 introduces Forward Error Correction (FEC), which slightly increases latency, but it also enables doubling throughput without doubling the signaling frequency to 64 Gbaud.

As a result, PCIe Gen6 generally delivers better bandwidth-per-watt than what an equivalent 64 Gbaud Non-Return-to-Zero (NRZ) implementation would have required. Given that modern data center deployments (particularly for AI) tend to be large, a greater bandwidth-per-watt metric should always be welcome.

In this story, we will summarize what the first breed of merchant enterprise-grade PCIe Gen6 controllers from three popular vendors will offer, and what we already have on the market from Micron and Samsung.

Marvell Bravera SC6: 500TB or more of speedy storage

Matt Murphy's appointment as Marvell CEO in 2016 marked one of the most dramatic strategic shifts in the semiconductor industry. Marvell transitioned from being a large merchant chip supplier to a company almost exclusively focused on data infrastructure, and that transformation had significant implications for its storage controller business. Storage still complements the broad data-center portfolio alongside networking, custom silicon, switching, compute, and optical connectivity. However, gone are the days when storage was a major priority for Marvell. Yet, Marvell's Bravera SC6 (MV-SF1410) looks to be quite a significant contender for the PCIe 6 storage market.

The Bravera SC6 controller is powered by 15 Arm cores in total, including 12 Cortex-R82 cores arranged in two six-core clusters, three Cortex-M7 cores, and a dedicated Cortex-M3 secure processor. The controller is NVMe 2.2 compliant and features a PCIe 6.0 x4 host interface, thus potentially offering a maximum of 30.25 GB/s of throughput.

The MV-SF1410 controller features 16 NAND channels, eight chip enables (CE) per channel, and support for SLC, MLC, TLC, and QLC 3D NAND with an up to 3600 MT/s interface. The part also supports Marvell's sixth-generation NANDEdge technology with LDPC error correction, a hardware RAID engine, end-to-end data protection, 5 MB of SRAM, and a 64-bit DDR5 interface with ECC. The security subsystem of the Bravera SC6 supports AES, SHA, RSA, and elliptic-curve cryptography (which seems to be among the industry's firsts), enabling compliance with Trusted Computing Group (TCG) security standards.

One of the things that strikes the eye about the Bravera SC6 is that its interfaces support data transfer rates of up to 3600 MT/s. While this speed bin seems a bit outdated now that 4800 MT/s devices have been announced, in eight- or 16-channel configurations, a 3600 MT/s transfer rate with raw bandwidth of around 3.6 GB/s per channel (38.8 GB/s and 57.6 GB/s in total, respectively) is more than enough to saturate a PCIe 6.0 x4 interface (30.25 GB/s without the overhead).

Another notable thing is that Marvell has not publicly disclosed the controller's maximum addressable NAND capacity or logical unit number (LUN) it can support within each CE, so we cannot derive an actual maximum addressable capacity or maximum usable capacity from the public specification we have at hand*. But we can make some useful estimates. The SC6 has 16 NAND channels and eight chip enables per channel, or up to 128 CE positions in total.

With upcoming 2 Tb 3D QLC NAND dies, each die stores 256 GB. Kioxia/Sandisk formally announced such devices last week, but did not disclose their availability timeframe. Since BiCS10 is aimed specifically at data center applications, Kioxia has indeed described this generation as suitable for very highly stacked packages, without disclosing the maximum number of NAND devices per package. Typical NAND packages carry between 1 and 16 NAND devices (though Kioxia/Sandisk probably meant more than 16 devices), though packages aimed at high-capacity drives tend to feature 8 or 16 devices. 16 2-Tb devices give 32Tb (or 4 TB) per NAND package.

If an SC6 implementation could populate 128 such package positions, that gives 512 TB of raw NAND memory. Of course, actual drives will have to reserve plenty of NAND for overprovisioning and other techniques required for reliability and longevity, so actual commercial SSDs will offer a lower capacity. However, they will remain in a 500TB-class. Meanwhile, if the SC6 can address 32-die packages, then we are talking about petabyte-class SSDs. Yet, 32-die NAND packages may require something other than formal controller support.

Marvell says that it will start sampling its Bravera SC6 (MV-SF1410) with its partners sometime in Q4 2026, which means that the first drives featuring the chip will hit the market in late 2027, but more likely in 2028. Given that actual SSDs featuring the controller are so far away, Marvell even refrained from disclosing the expected performance of these products and only told us to expect "multi-gigabyte-per-second throughput, millions of random IOPS, deep queue parallelism, and highly efficient DMA-based data movement."

*A CE may select a package containing many dies, and each die may contain multiple LUNs. To address all those dies and LUNs efficiently, the controller must be architected appropriately. If the number of supported LUNs is lower than the number of LUNs featured by all-flash devices in all-flash packages, this will affect performance and parallelism, which will lower the appeal of such drives for data center operators.

Phison X3: Up to 2PB of storage at 28.8 GB/s

Phison has yet to make a big formal announcement of its X3 — aka PS5303 — SSD controller, but it was demoed at both CES and Computex this year. At CES, the company only showcased concepts of its PCIe Gen6-based drives, whereas at Computex it showed off reference drives, clearly suggesting that it is in the final stages of development.

The Phison X3 (PS5303) is the company's first-generation PCIe 6.0 x4 enterprise SSD controller, and it happens to be specifically aimed at data center applications, which include AI, cloud, and hyperscale deployments. Normally, Phison would introduce an eight-channel controller that would target both high-end desktop, workstation, and server applications. But such controllers have not yet surfaced.

The X3 is a 16-channel and NVMe 2.3-compliant controller, which Phison rates for up to 28 GB/s sequential read and write performance, 6.8 million random read and write IOPS, and approximately 4 GB/s per watt, which doubles the performance and efficiency of the company's PCIe 5.0 enterprise controller. Keeping in mind that its current-generation controller is made on TSMC's N12 manufacturing technology, whereas the X3 is produced on the N4 fabrication process, this improvement is expected.

Perhaps the most intriguing specification is support for SSD capacities of up to 2 Petabytes, which likely suggests that the controller has been designed with multiple future generations of dense 3D NAND flash memory in mind.

The controller supports OCP Datacenter NVMe SSD Specification v2.6, advanced enterprise security features including TCG Opal 2.3, DOE, IDE, Caliptra, and CNSA 2.0, as well as 64 SR-IOV physical functions for storage virtualization.

Phison has indicated that reference designs — E3.S, E1.S, etc. — are expected to sample this November, while volume production is anticipated in 2027, if everything proceeds in accordance with the plan. If the company succeeds, the X3 (PS5303) will be one of the first merchant PCIe 6.0 SSD platforms intended for next-generation storage infrastructure in 2027. Then again, it usually takes a year before sampling and availability of the actual drives.

Silicon Motion's SM8466: A mystery at 28 GB/s

Silicon Motion was probably the first company to reveal many of its details about its PCIe Gen6 plans in an interview with Tom's Hardware in June '25, then a leak with some details about its PCIe 6.x SSD controller emerged in July '25. After then, SMI kept it pretty much close to the chest about the SM8466 unit, but let us recall what we know about the controller both from our interviews and from the leaks.

Silicon Motion's MonTitan SM8466 is the company's 2nd-generation enterprise-grade controller that is projected to support 16 NAND channels, next-generation TLC and QLC 3D NAND, NVMe 2.x, OCP enterprise SSD specifications, and enterprise security technologies such as TCG Opal, Secure Boot, and SR-IOV virtualization, based on our interviews with the company as well as leaks.

Just like its direct rival from Phison, the SM8466 is rumored to offer 28 GB/s of sequential throughput and 7 million random IOPS, though no official claims have been made so far. Just like the Marvell controller, the SM8466 supports SCA and other features of modern enterprise-grade SSD platforms.

Perhaps the most surprising part of the specification is support for SSD capacities of up to 512 TB, which clearly falls short of the 2 PB capacity advertised by Phison's competing PCIe 6.0 controller. Then again, this is based on leaks and rumors, rather than official information.

Now that we know something about PCIe Gen6 SSD platforms from Marvell, Phison, and Silicon, let us recall what is already on the market, or about to hit it.

Micron's 9650: First and furious

Micron's 9650 is the industry's first PCIe 6.0 x4 SSD that is based on an in-house controller and the company’s 276-layer G9 3D TLC NAND with a 3600 MT/s interface. The drive delivers up to 28 GB/s sequential reads, 14 GB/s sequential writes, 5.5 million random read IOPS, and 900,000 random write IOPS. Depending on the exact SKU, the drive offers up to 25.6 TB of storage.

Since the 9650 is aimed purely at AI servers based on Nvidia hardware, Micron has optimized the SSD for peer-to-peer PCIe 6.0 communication with Nvidia Blackwell GPUs using retimers and switches to enable storage to feed accelerators without CPU involvement.

Micron started sampling its 9650 back in Q3 2025, so by now this drive is likely already available to interested parties.

Samsung's PM1763: 16 TB at 28 GB/s

Samsung has never announced sampling of its first-gen PCIe 6.0 x4 SSD, but it officially began mass production of its PM1763 drive this July. The PM1763 drive is based on a proprietary controller made using Samsung Foundry's 4nm-class fabrication technology as well as Samsung's ninth-generation V-NAND.

When it comes to capacity, the PM1763 is offered in 4TB, 8TB, and 16TB capacities. The flagship 16 TB model delivers up to 28.4 GB/s sequential read and 21.9 GB/s sequential write speeds, though the company hasn't disclosed the random performance of either SSD. Then again, to maximize performance, the drive's design is optimized for direct-to-chip (D2C) liquid-cooled servers (Samsung has not divulged details, though).

When it comes to power efficiency, Samsung claims the drive delivers more than 1.8X higher power efficiency than its predecessor and enables it to sustain peak performance during prolonged AI training and inference workloads. Unfortunately, without hard numbers, we can only take Samsung at its word.

In addition, the SSD supports post-quantum cryptography (PQC) algorithms to help protect against future quantum computing attacks, as well as the TEE Device Interface Security Protocol (TDISP) to secure data movement in virtualized server environments.

According to Samsung, the PM1763 has completed validation for next-generation AI platforms and is positioned as a storage solution for an AI data center near you.

Almost across the line

After years of delays caused by the transition to PAM4 signaling and the resulting ecosystem-wide validation effort, PCIe 6-class storage is finally approaching commercialization.

While Micron and Samsung already offer PCIe 6.0 SSDs, merchant controller suppliers —Marvell, Phison, and Silicon Motion — are prepping their next-generation enterprise platforms with up to 16 NAND channels, throughput approaching 28–30 GB/s, and support for capacities ranging from 512 TB to as much as 2 PB.

Pushback against Micron's planned manufacturing complex in Clay, New York, which comprises four separate fabs, is once again at the center of an environmental lawsuit. Filed by Neighbors for a Better Micron and Jobs to Move America — the same groups that filed a separate lawsuit against Micron in January — filed a new complaint Friday, claiming that approved wastewater and air permits aren't valid and will allow Micron to leak "forever chemicals" into the Oneida River.

"The Permits were issued against eh backdrop of the significant environmental consequences already acknowledged through the course of the Micro Project's State Environmental Quality Review Act (SEQRA) review. including the release of PFAS and other highly persistent and hazardous chemicals," the complaint reads. "Rather than fully and meaningfully evaluate and address those consequences and impose the necessary protections before granting final authorization, [the Department of Environmental Conservation] issued permits that defer essential analyses, controls and limitations, and mitigation decisions until after issuance or until future regulations and studies have been conducted."

The lawsuit names the New York State Department of Environmental Conservation (DEC), Onondaga County (where Clay is located), and Micron. Its claim is that, despite Micron receiving wastewater and air permits from the DEC, those permits aren't adequate to regulate the plant's emissions. In one part of the lawsuit, the petitioners claim the permits are "not routine operating approvals," and in another, claim the loose permit guidelines "are not collateral or technical omissions."

Per- and polyfluoroalkyl substances, otherwise known as PFAS or "forever chemicals," are synthetic chemicals that are essential to semiconductor manufacturing. The chemicals are present throughout nearly the entirety of the manufacturing chain, necessitating strict water and air containment management to align with environmental regulations. "The SPDES permit authorizes the acceptance and discharge of Micron's industrial wastewater containing identified emerging contaminants, including PFAS compounds, but it imposes no substantive controls on those harmful contaminants beyond monitoring their presence and concentration."

In January, the two petitioners named in this complaint filed another lawsuit against Micron, claiming that the project failed to comply with the state's environmental review process. Last month, Micron asked a judge to dismiss the lawsuit. It's still set for oral arguments on August 25, however.

This lawsuit currently doesn't have a date set for oral arguments, if it ever reaches that point. The petitioners are seeking the nullification of both wastewater and air permits, which would force Micron back under the environmental review process, and costs associated with the suit.

One of the common misconceptions in today's memory market is that once memory modules based on chips from CXMT enter the consumer market, there will be cheaper alternatives to memory sticks running DRAM from the Big Three. While availability of CXMT-powered modules certainly impacts average selling prices, these products are not cheaper than those based on ICs from Micron, Samsung, and SK hynix even in China, as noticed by @harukaze5719.

A 64GB DDR5-5600 RDIMM based on memory from Samsung or SK hynix costs 18,595 CNY ($2,745) at JD.com, whereas a module featuring the same capacity and specification, but using DRAMs from CXMT is priced at 18,999 CNY ($2,805), according to observations by @harukaze5719. It is noteworthy that a Samsung 64GB DDR5-5600 RDIMM made by Samsung and sold by Samsung costs $2,425 at Amazon.com in the U.S.

While the $60 difference seems significant, it is really just 2.2%, which can be considered negligible at these sky-high prices. Nonetheless, many expect CXMT-based memory modules to be cheaper than those carrying chips from Micron, Samsung, or SK hynix, so observing that they are even a bit more expensive than offerings with ICs from renowned manufacturers may be a bit surprising.

Indeed, because CXMT produces memory chips using an outdated fabrication technology, its DRAM ICs consume more power than those made using the latest manufacturing processes, have lower performance potential, and mediocre overclockability. Furthermore, the Chinese government heavily subsidizes both ChangXin Memory Technologies and Yangtze Memory Technologies (YMTC), which enables both to sell their memory at lower prices although their actual costs may be higher compared to those of the Big Three.

As a result, it is reasonable to expect CXMT to charge less for its chips compared to chips from renowned producers. Truth to be told, we do not know CXMT's quotes, they may be as high as those from other manufacturers and the only reason why module producers buy them is that they are the only chips available. Furthermore, companies tend to price products based on what the market will bear, not strictly on production cost or their characteristics. In fact, as everyone is capacity constrained these days, there is little incentive for CXMT to price its DRAMs significantly below those from renowned makers. However, while CXMT may indeed charge less for chips (e.g., because the Chinese government issues an appropriate directive), this lowers costs for module makers, but has a limited effect on retail prices of actual DIMMs or RDIMMs.

Whether potential savings reach end customers depends on market competition, supply-demand conditions, and the pricing strategies of module makers, distributors, and retailers. Furthermore, when prominent companies like Apple, Dell, or Corsair use a memory chip SKU, this one must pass rigorous validation processes and is usually tested in-house, or by contract manufacturers, which adds to costs and somewhat erases the price difference between suppliers.

As a result, CXMT memory chips may make the lives of hardware makers easier, but are not expected to impact the retail prices you pay.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

Micron has said it will invest up to $3 billion in the U.S. semiconductor supply chain, with $500 million of that going to GlobalWafers as strategic financing for its 300 mm raw silicon wafer plant in Sherman, Texas, alongside a 10-year agreement giving Micron access to that plant's wafer output. In a separate announcement, the memory maker raised its planned U.S. spending to more than $250 billion through 2035, up from $200 billion, and confirmed the first concrete pour at its Clay, New York campus more than a quarter ahead of schedule.

Sherman is the sole operating facility in the U.S. capable of producing advanced 300 mm raw silicon wafers, the substrate on which every leading-edge DRAM, NAND, and logic die is built. GlobalWafers opened the plant in May last year and holds a $406 million CHIPS Act award covering the site and a silicon-on-insulator facility in St. Peters, Missouri. The 142-acre campus is designed for up to six phases, one of which is running. Micron's other American sites draw their wafers from Japan, Taiwan, Germany, and South Korea; Shin-Etsu, SUMCO, GlobalWafers, Siltronic, and SK Siltron together control the overwhelming majority of global 300 mm supply, making raw silicon the most concentrated layer in the chip space.

Doris Hsu, chairperson and CEO of GlobalWafers, set out her terms for building phase two at Sherman during the plant's opening last year, telling Reuters the company needed profitability at the first two phases, customers willing to sign long-term contracts, reasonable pricing, prepayments, and government support. Thursday's announcement supplies most of that list in a single transaction.

Wafer suppliers spent the 2023-2024 downcycle protecting margins rather than adding capacity, and SUMCO is winding down 200mm production at Miyazaki this year while holding the line on new 300mm expansion. Customers, not suppliers, are therefore now underwriting the capacity. The last time the industry did this, during the 2017-2018 megacycle, chipmakers signed prepaid long-term agreements that turned into liabilities when pricing rolled over.

Silicon wafer shipments reached 3,275 million square inches in Q1 2026, up 13.1% year over year, with SEMI.org attributing the growth to AI data center demand across advanced logic, memory, and power devices. Micron's first new Idaho fab, ID1, is expected to begin wafer output in mid-2027, and production at Clay isn't expected until around 2030. The company began making 1-alpha DRAM at its Manassas, Virginia fab in May.

Micron told investors last December that it can serve only half to two-thirds of customer demand, and nothing announced Thursday changes the supply position of DRAM this year or next.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

Samsung, SK hynix, and Micron were sued on June 25th in the U.S. District Court for the Northern District of California, where 17 plaintiffs accuse the three memory makers of illegally coordinating to restrict DRAM supply and inflate prices that the complaint says have risen roughly 700% over four years. The class action, filed as Garciaguirre v. Samsung Electronics and assigned to Judge Noel Wise, invokes Section 1 of the Sherman Act and targets companies that together hold around 90% of the global DRAM market. Samsung and SK hynix have pleaded guilty to criminal DRAM price fixing once before, with the latter paying a $185 million fine in April 2005.

The complaint argues that the three companies used a coordinated shift toward high-bandwidth memory (HBM), the stacked DRAM that feeds AI accelerators, as a cover to curtail production of older DDR3 and DDR4 modules. That contraction in commodity DRAM, the plaintiffs argue, pushed prices to record highs while no rival could step in: building a new DRAM fab costs tens of billions and takes years, leaving the incumbents free to cut output without fear of being undercut.

The named plaintiffs include 14 individuals and three small PC businesses, among them Troy's Computers and Florida repair outfit My Florida PC, and they cite Apple's recent iPad and Mac price increases as evidence of the squeeze. They’re seeking class status, an injunction, and treble damages as a result.

However, this case revisits a precedent that was already established in the same courthouse. A 2018 class action brought by law firm Hagens Berman made similar claims about parallel production cuts, and the district court dismissed it in 2020. The Ninth Circuit upheld that dismissal in 2022, ruling the trio's conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by an illegal agreement.

It was held at the time that the plaintiffs’ eight “plus factors” didn’t clear Section 1’s threshold, which demands evidence of an actual agreement rather than the conscious parallelism common in a three-supplier market. The new complaint leans on the pivot to HBM as the additional evidence that this earlier lawsuit lacked.

The three memory makers have publicly stated they’re operating independently while redirecting capacity to HBM, and senior executives have warned the shortage could run for years. Investment bank Jefferies expects DRAM prices to rise another 40% to 50% in the third quarter and a further 30% to 40% in the fourth, with no meaningful relief before 2028. The allegations remain unproven, and the defendants have not yet responded in court.

Micron announced this week that it has begun manufacturing 1α (1-alpha) DRAM at its Manassas, Virginia, facility. This action brings the company's most advanced DDR4-compatible process technology to U.S. soil for the first time. The expansion, which Micron says will quadruple DDR4 wafer output at the site, represents a $2 billion-plus investment supported by $275 million in finalized CHIPS and Science Act funding, and production is expected by the end of the year.

The company is the only manufacturer of memory in the United States, and the Manassas fab specifically serves long-lifecycle customers in the automotive, defense, aerospace, industrial, networking, and medical device sectors.

Micron is scaling up DDR4 production as the supply of the older memory standard has become unexpectedly tight. All three major DRAM producers are reallocating fab capacity toward DDR5, LPDDR5X, and high bandwidth memory (HBM) to meet AI-driven demand from hyperscalers and data center operators. Micron itself issued end-of-life notices for mainstream DDR4 and LPDDR4 products in high-volume consumer and data center segments last year, with final shipments to those customers expected to wrap up in early 2026.

That decision has left industries with long product cycles exposed, and S&P Global Mobility estimated that automotive DRAM contract prices could rise 70% to 100% in 2026 compared with 2025 levels, warning that the supply of older-generation automotive DRAM will begin to dry up sharply by 2028. DDR4 inventory buffers for automotive and industrial buyers have reportedly contracted from over 31 weeks to as few as six to eight weeks.

The 1α process node, which Micron first brought to volume production at its Taiwan fabs in late 2020, delivers roughly 40% higher bit density than the preceding 1z node and was the first DRAM technology to achieve sub-15nm cell dimensions. It uses DUV lithography rather than the more expensive EUV tools that Samsung has adopted for its advanced DRAM nodes. Micron's newer 1β and 1γ nodes are dedicated to DDR5, LPDDR5, and HBM.

Onshoring 1α to Virginia effectively creates a dedicated domestic production line for DDR4 and LP4 memory that won't compete for wafer starts with Micron's leading-edge AI-focused products. The Manassas site will also support more than 3,100 direct manufacturing and community jobs.

The Virginia fab is part of Micron's broader $200 billion U.S. investment plan. The company broke ground on a new memory manufacturing complex in Clay, New York, in January, and initial wafer output at its first new Idaho fab is expected in mid-2027. Micron has also committed to eventually adding HBM advanced packaging capabilities at the Virginia site once sufficient DRAM wafer capacity is established at its other U.S. facilities.

Across all three sites, Micron says the investments will create an estimated 90,000 direct and indirect jobs.

Micron’s planned $24 billion NAND flash expansion in Singapore will require 400 to 500 power transformers, which is more than double the 100 to 150 units a standard wafer fab typically needs, according to industry sources as reported by DigiTimes. The scale exceeds the annual output capacity of any single Taiwanese transformer manufacturer, turning heavy electrical equipment into a bottleneck for AI-driven semiconductor buildouts.

This level of demand from Micron reflects the power intensity of modern memory fabs tied to AI. HBM production for AI servers has driven every major memory maker into simultaneous expansion, and the electrical infrastructure required to support those fabs is now outpacing the supply chain built to serve it.

Micron's Singapore project, where production is targeted for late 2028, is one piece of a broader global buildout. The company has acquired PSMC's Miaoli Tongluo fab in Taiwan for $1.8 billion, with that facility slated for 2026, while new plants in Idaho and New York are underway, and a Hiroshima facility is expected to begin operations in the second half of 2026.

Samsung Electronics and SK hynix have also announced their own capacity expansions, all driven by the same demand curve: AI server deployments consuming HBM at volumes that existing production lines cannot satisfy. We’re now seeing a synchronized wave of fab construction across three continents as a result, with each project competing for the same pool of heavy electrical equipment and raw materials.

The toll this is taking is already visible in pricing and availability, with major heavy electrical equipment suppliers Fortune Electric and Allis Electric both having implemented price increases of 20% to 30%, driven by the surge in orders and rising costs of copper and other raw materials. Meanwhile, some transformer manufacturers have declined to quote on large-scale semiconductor projects entirely, citing an inability to meet the tight timelines and volume requirements. Industry sources say no single maker can absorb the scale of orders now flowing from the AI and semiconductor sectors.

International transformer brands, despite commanding higher prices, are gaining ground because their larger overseas factories can push out more units. Domestic Taiwanese manufacturers have responded by collaborating with secondary suppliers, dividing specifications and capacity across multiple firms to meet individual customer demands.

Transformers are also shared infrastructure, and, beyond fabs, the same equipment is needed for AI data center construction, utility-scale energy storage, and grid expansion projects. A supply chain that was already stretched before the AI buildout wave is now absorbing orders measured in the hundreds of units per project.

Unfortunately, delayed transformer deliveries will likely translate into delayed fabs, which in turn will push back the timelines for memory production that AI buyers are counting on. Data center operators planning new facilities are in the same queue, competing with semiconductor companies for equipment that takes months to manufacture and deliver.

Micron CEO Sanjay Mehrotra said that cars will eventually require more than 300GB of RAM as automakers introduce vehicles that have L4 autonomy. According to The Register, Mehrotra said this after Micron released its quarterly earnings report, with the company reporting $23.86 billion in revenue for the second quarter of this year — a huge 200% jump from the $8.03 billion it posted in 2Q25. This massive jump is still driven by the incredible demand for premium HBM chips from AI hyperscalers combined with “structural supply constraints and Micron’s strong execution across the board.”

As the company is raking cash from the AI infrastructure build out, it’s also expanding its output with several planned fabs in Japan, Singapore, and even a “megafab” in New York. These projects are expected to come online between 2028 and 2029, and the Micron CEO said that it’s looking to boost output by 20% in 2026, which could help alleviate some of the pressure on the supply side. However, even as these new factories start production, Mehrotra predicts that there will be a new market that demands massive amounts of high-speed memory — self-driving cars.

There are six levels of vehicle autonomy, starting at L0 for cars that have no driving automation whatsoever. A vehicle with a single automated system (such as cruise control) counts as L1, while those equipped with advanced driver assistance systems (ADAS) that both control steering and acceleration, such as Tesla’s Autopilot and Cadillac’s Super Cruise, are considered as L2. On the other hand, vehicles with L4 autonomy basically do not need human intervention in any task, like overtaking or deciding when to cross a busy intersection. However, it still gives the driver the option to take control and manually drive the vehicle.

Nvidia announced that it’s working with Chinese carmakers BYD and Geely and Japanese marques Isuzu and Nissan to adopt the Nvidia Drive Hyperion platform. This is the AI chip maker’s end-to-end autonomous vehicle platform meant to deliver an L4 system to car manufacturers. Since this is an AI system, it will likely demand a lot of high-speed memory to be able to run effectively.

Most modern vehicles require at least 16GB of memory, but if car makers introduce L4 autonomy, it will definitely need a lot more RAM. We’ve seen this with the shortage of high-end Macs with up to 512GB of Unified Memory as many users have become interested in running the likes of OpenClaw on their own systems. It has even gotten to the point that Apple pulled the $4,000 512GB Mac Studio from its online store and raised the 256GB version to $2,000. So, if carmakers started churning out hundreds of thousands, if not millions of vehicles with AI-powered driverless features, Micron expects demand for automotive memory to pick up as well.

This might take some time to happen, though, especially as vehicles with these features are quite expensive and regulations haven’t quite caught up with L4 autonomy just yet. But if and when people start buying cars like these, we hope that memory chip makers have excess capacity to absorb the increase in demand. Otherwise, we might be seeing another round of memory chip shortages, this time driven by AI supercomputers on wheels.

Micron has announced that it has entered high-volume production of its HBM4 36GB 12-Hi memory, designed for Nvidia's Vera Rubin GPU platform. Making the announcement at GTC 2026, the memory giant simultaneously confirmed high-volume production of the industry's first PCIe 6.0 data center SSD and a new SOCAMM2 module, making it the first memory supplier to bring all three products to volume shipment for the Vera Rubin ecosystem at the same time.

The HBM4 36GB 12H stack runs at over 11 Gb/s pin speeds, delivering bandwidth greater than 2.8 TB/s. Compared to Micron's HBM3E at the same 36GB 12H configuration, that represents a 2.3 times bandwidth increase alongside more than 20% improvement in power efficiency, according to Micron's internal power calculator data.

"The next era of AI will be defined by tightly integrated platforms developed through joint engineering innovations across the ecosystem. Our close collaboration with NVIDIA ensures that compute and memory are designed to scale together from day one," said Sumit Sadana, executive vice president and chief business officer at Micron Technology, in a press release. "With HBM4 36GB 12H, alongside the industry's first SOCAMM2 and Gen6 SSD now in high-volume production, Micron's memory and storage form a core foundation that unlocks the full potential of next-generation AI."

Micron has also shipped samples of a 48GB 16H HBM4 stack to customers. The additional four die layers give the 16H configuration a 33% capacity increase per HBM placement over the 36GB 12H product, a milestone that points toward denser configurations in future AI accelerator generations.

Last month, the company announced that the 9650 SSD had entered mass production, marking the first time that a PCIe 6.0 SSD had entered that stage of production. The drive supports up to 28 GB/s sequential read throughput and 5.5 million random read IOPS, doubling PCIe 5.0 read performance at 100% higher performance per watt. Unsurprisingly, it targets AI inference, training, and agentic workloads in liquid-cooled environments and is optimized for Nvidia's BlueField-4 STX reference architecture.

Meanwhile, the 192GB SOCAMM2 module is designed for Nvidia Vera Rubin NVL72 systems and standalone Vera CPU platforms, with Micron's SOCAMM2 portfolio spanning 48GB to 256GB capacities. The Vera Rubin platform supports up to 2TB of memory and 1.2 TB/s of bandwidth per CPU using the module.

SK Hynix has announced the successful development of its first LPDDR6 DRAM, touting 33% greater speed and 20% better power efficiency compared to previous generation LPDDR5X memory. The memory manufacturer also announced that it has developed its LPDDR6 memory on its leading-edge 10nm-class (1c) process node that it announced in 2024.

The new modules have a base operating speed of "over" 10.7 Gbps — which exceeds the fastest outgoing LPDDR5X memory modules on the market today — and a memory capacity of 16Gb per chip. To help with power consumption, SK Hynix implemented a new sub-channel structure and DVFS, or Dynamic Voltage and Frequency Scaling, which it says reduces power consumption by more than 20% compared to previous generation LPDDR memory products. The sub-channel structure accomplishes power reductions by powering only the data paths that are in use, while DVFS reduces clock speed and voltage when memory demands are light.

SK Hynix has announced its LPDDR6 eight months after JEDEC finalized and published the LPDDR6 standard last July. However, SK Hynix is not the first manufacturer to make LPDDR6; Samsung already announced its first LPDDR6 product and showcased it at CES 2026, with speeds up to 10.7Gbps.

SK Hynix has confirmed that its 1c LPDDR6 will be used in smartphones and tablets, but we can also expect LPDDR6 to be a huge boon in the datacenter market. LPDDRX has been very popular in AI servers that take advantage of SOCAMM/SOCAMM2 memory modules that only support LPDDR memory. For instance, Nvidia's GB300 Grace Blackwell Ultra Superchip uses SOCAMM, and Nvidia's latest Vera Rubin Superchip uses SOCAMM2 memory modules. Late last year, SK Hynix stated that it expects post-Vera Rubin Nvidia AI chip designs to take advantage of LPDDR6.

This is just the beginning for LPDDR6; speeds well beyond 10.7Gbps are expected to become the norm as memory makers get to grips with optimizing and improving on their LPDDR6 designs. The JEDEC group believes that LPDDR6 will have data rates of up to 14,400 MT/s, which is well beyond what the fastest DDR5 overclocking record holds.

Most of the conversation about speed in AI datacenters revolves around the accelerators themselves, discussing tokens per second and the like. However, the battle for AI performance is fought on multiple fronts, and one of them is in memory capacity and power efficiency. Today, Micron unveiled what look to be the industry's first 256 GB SOCAMM2 units, a sizable step up from the last-best 192 GB modules released just six months ago.

The company says it's now shipping samples to customers, who will most definitely be happy at the notion of having 2TB of memory wired to each CPU. For just one major example, the typical Nvidia NVL72 rack can now carry 72 TB of RAM for its 36 CPUs.

The 33% improved density over previous-generation SOCAMM2 is excellent news on its own, but that's not the only advantage of this form factor. The new modules ought to offer 66% better power efficiency compared to bog-standard RDIMMs, and they're compatible with increasingly popular (and necessary) liquid cooling for AI servers.

According to Micron, the new sticks are the first to employ its 32 Gb (4 GB) LPDDR5X monolithic dies, where "monolithic" means all the memory and relevant circuitry are part of a single die.

Given the target market for these large SOCAMM2s, the firm touts the real-world performance improvements beyond just density and power efficiency. Having this much RAM available to a single processor lets AI models use much larger context windows. Consequently, it helps reduce the all-important TTFT (Time To First Token), meaning bots start answering your questions quicker.

In an AI future where context is literally everything, every gigabyte of memory closer to the xPUs in a system matters, and Micron's advancement today will doubtless be found in massive AI server installations worldwide as companies allocate hundreds of billions of dollars of capex in the race toward AI supremacy.

The SOCAMM2 form factor is the result of a partnership between Nvidia and memory makers Micron, Samsung, and SK hynix. The SOCAMM standard was originally designed by Nvidia, but the accelerator mogul reportedly had trouble getting the modules to operate without overheating on high-density servers. CEO Jensen Huang wisely teamed up with the folks who make computer memory for a living, resulting in SOCAMM2s with growing density and lower power consumption.

Micron has finally joined the 3GB GDDR7 party and has officially introduced 3GB modules to compete with Samsung and SK Hynix's 3GB variants. The memory maker officially announced its larger GDDR7 version in a blog post, revealing that its new 3GB ICs operate at 36 Gbps.

The new modules are 12.5% faster than the first GDDR7 modules that hit the market, which achieved 32 Gbps of bandwidth. However, Micron's new modules are noticeably slower than Samsung's competing solutions, which can run at up to 42.5 Gbps. SK Hynix similarly has outgoing GDDR7 modules that can scale up to 40 Gbps, and is working on future models that can reach 48 Gbps.

However, in Micron's favor, there are no outgoing Nvidia graphics cards that take advantage of GDDR7 speeds anywhere near 40 Gbps or faster. The highest GDDR7 transfer speeds on outgoing GDDR7 GPUs include the RTX 5080, which has its memory modules running at 30 Gbps. Other cards, such as the RTX 5090, use even lower memory speeds of 28 Gbps. That said, we have seen memory overclocks on the RTX 5070 Ti and RTX 5090D of up to 34 Gbps on SK Hynix and Samsung GDDR7.

As a result, there's not much reason for Micron to introduce new GDDR7 memory modules with blisteringly fast speeds of 40 Gbps or newer. The next generation RTX 60 series or next generation AMD Radeon GPUs might take advantage of higher memory speeds, but it's not required right now on existing GDDR7 GPUs.

Beyond speeds, having a third manufacturer for 3GB GDDR7 will be highly beneficial for Nvidia and other GPU makers. Nvidia is already taking 3GB GDDR7 chips from both Samsung and SK Hynix, and likely will start introducing Micron 3GB GDDR7 to help compensate for the outgoing NAND flash/memory shortage. Currently, the only Nvidia GPUs that use 3GB GDDR7 are the laptop-variant of the RTX 5090 and the RTX Pro 6000 Blackwell workstation GPU. If Nvidia ever decides to launch the RTX 50 Super series, it is expected that all rumored GPUs in that lineup, the RTX 5080 Super, 5070 Super, and 5060 Super, will use 3GB modules.

The artificial intelligence supercycle is reshaping the semiconductor and electronics industries, as the scale of the AI infrastructure buildout strains the entire supply chain. While developers of AI accelerators like Nvidia are cashing in on the AI boom, it's memory makers that will earn the most cash, according to estimates from TrendForce. Arguably, this is a result of the different business models and expansion strategies memory makers use compared to foundries, in addition to the behavior of the commodity market.

Demand outstrips supply

The company projects that while global foundry revenue is expected to total $218.7 billion, 3D NAND and DRAM revenue will reach $551.6 billion, which means that the total market for memory is more than twice as large as contract chip production. TrendForce attributes this to structural market changes caused by AI buildouts. The latter creates elevated demand for specific types of memory, creating shortages of all types of memory, and therefore affecting prices across the industry. As a consequence, while the AI industry does not need low-capacity commodity memory devices, they also become substantially more expensive amid tight supply. This creates the perfect conditions for memory makers to capitalize upon.

Indeed, the spot price of a 16 Gb DDR5 chip at DRAMeXchange was $38 on average, with a daily high of $53 and a daily low of $25. By contrast, the very same chip used to cost $4.75 on average just one year ago ($3.70 session low, $6.60 session high). Similar changes occurred to the prices of 3D NAND memory in recent quarters.

Fundamental differences

Just like some other analyst firms, TrendForce calls the AI megatrend a 'supercycle,' indicating its overwhelming ubiquity, which affects multiple industries, and its potential length.

There were two periods in the last few decades when revenue of memory makers grew significantly year-over-year for two years in a row: in 2017 – 2018, when hyperscalers built their vast data centers (+62% in 2017 and +27% in 2018), and in 2020 – 2021, when people increased purchases of PCs amid the COVID-19 pandemic. In both cases, memory makers increased capacity to meet demand and maintain their market share, which caused sharp drops in revenue back in 2019 and 2022.

The foundry industry — which is much more capital-intensive than the 3D NAND or DRAM industries — uses fabs that are harder and longer to build, and only suffered a year-over-year revenue decline in 2023.

The situation today is vastly different. On the one hand, leading developers of frontier AI models need the most powerful clusters to train their models, therefore creating demand for leading-edge hardware with expensive HBM3E memory and plenty of storage. On the other hand, these companies and their clients need more powerful inference systems to use those models. Therefore, demand for CPUs, AI accelerators, memory, and storage does not decline over time. Meanwhile, buyers like cloud service providers (CSPs) tend to be less sensitive to price increases, which is why 3D NAND and DRAM suppliers are expected to raise average selling prices more aggressively than in the past cycles.

Foundry vs. Commodity

3D NAND and DRAM are commodities, so their prices behave like prices of commodities, almost immediately reacting to tightening supply, increasing demand, or sentiment among buyers. While large PC makers purchase their memory at prices agreed upon every six months, a significant portion of memory is sold on the spot market.

This dynamic is reflected in TrendForce's projections that show memory revenue growth accelerating after the downturn of 2022 – 2023, including an expected 80% increase in 2024, followed by 46% growth in 2025, and a projected 134% surge in 2026.

By contrast, foundries tend to operate under long-term agreements that smooth price fluctuations, which prevents sharp swings that characterize memory markets. Even during periods of strong demand, foundry pricing adjustments occur gradually, which means slower revenue growth compared to memory vendors.

TrendForce models that following a 19% year-over-year revenue increase in 2024, the foundry market grew 25% in 2025 and will grow another 25% this year.

As a result, boosted by the AI supercycle and not constrained by long-term agreements, memory vendors will earn more than two times more this year alone compared to producers of logic, which have to adhere to their long-term contracts.

The biggest question

With HBM4 memory devices using four times more silicon than typical DRAM ICs, it is obvious that memory makers cannot meet all the demand that exists because of insufficient capacity, which results in price adjustments. However, the biggest question is how significantly current commodity 3D NAND and DRAM prices are influenced by insufficient supply, and how significantly they are influenced by typical commodity memory market behavior that dictates that customers buy more memory when it is getting more expensive, as it may get even more expensive in the future?

In one of the most hotly competitive and profitable tech industries, the three major memory makers, Samsung, SK Hynix, and Micron, are individually investigating their customers to prevent memory hoarding, according to Nikkei Asia. They’re asking customers to disclose their own customers and order volumes to ensure that no one is hoarding more memory than they need, exacerbating memory supply problems.

The immediate impact of this may well be to accelerate price increases for consumer devices. After all, if a company can’t buy cheaper memory now, it could be more expensive to buy it later. But this may help give memory makers the confidence they need to effectively invest in increased production, and it might just give smaller customers a chance to compete fairly.

Fool me twice… you can’t fool me again

Since memory demand started skyrocketing in 2025, memory makers have been inundated with calls to increase supply while brands panic-bought what was available. Ramping up production lines and retooling fabs is required, but it’s not that easy. NAND flash, particularly the newest and most capable chips, uses cutting-edge facilities, and those manufacturing lines take years to bring online.

Production can and is being increased, but the required investment for such an endeavour is enormous. Though the potential upsides are excellent – increased supply should mean the memory makers can sell more in turn – the potential downsides are there too. Most notably, if supply and demand equalize, any industry changes could swing the ratio in the other direction, leaving the memory companies oversupplied and competing with each other to sell what they have.

This isn’t some theorized scenario, either. It’s already happened, which is why Samsung, SK Hynix, and Micron are twice shy about increasing production.

During the pandemic, as everyone rushed to buy desktops and laptops to work from home, memory was once again in short supply, and the memory makers scrambled to catch up. They invested in new facilities, taped out new production lines, and pivoted the enterprise to adjust to a new world where memory wasn’t plentiful.

But it wasn’t to last. Just a few years later, as demand started to fall, problems arose. Because during those pandemic months and years, customers of the major memory manufacturers overbooked and built up stockpiles of their own, they didn’t continue to replace them when their own orders dwindled. By the end of 2022, memory sales had dropped by almost a third, and revenue was crashing right behind it as the going price for memory cratered.

This led to companies like Samsung actually cutting production of its 3D NAND and DRAM products. Although it claimed to be continuing R&D expansion and infrastructure building, it wasn't on the same scale as it would have been had orders remained strong. SK Hynix followed suit several months later, and those cuts continued throughout 2023 across a range of companies.

Which brings us back to 2026. This time, the memory makers are looking to ensure that the memory hoarding doesn’t happen, so that if and when demand and supply are realigned, there’s less chance of the swing continuing into oversupply, under-demand territory.

That’s good for them, because it means demand should remain stable even if there are wobbles in the AI industry, or even an eventual bubble burst and collapse. If memory customers don’t have their own stockpiles, they’ll still need at least some memory, even if demand falls dramatically.

But won’t this just keep memory prices permanently high? Won’t it help prevent a big pricing correction if and when that bubble bursts, just keeping us all paying over the odds for memory forever?

Perhaps.

A boon to consumers

In the near term, it might actually stop memory prices from rising as quickly. If customers of Micron, Samsung, and SK Hynix have been overbuying – and why wouldn’t they, if they can afford it – then preventing that immediately should curb demand. That could help slow the current parabolic price rises for memory specifically. While that might mean the major customers who had planned on stockpiling cheaper memory end up raising their prices sooner than they had planned, the overall effect should see a slowdown.

Similarly, cutting the overbooked orders should make it easier for smaller memory customers to gain access to orders. If they aren’t trying to compete with not only major companies but also major companies overbuying, they should find it easier to get stock of memory at fairer prices. That has the potential to stabilize industries and prevent smaller brands from being pushed out of markets entirely, keeping competition healthier, which is always good for customers.

It could also help give the memory manufacturers the confidence they seek to build out production faster and more effectively. Whereas previously their efforts in boosting supply ended up with them having to reduce supply down the line, this way they can be more confident of a longer tail for their business.

We just had a flurry of new investment announcements from Micron, SK Hynix, and Samsung, all of which are building new fabrication lines and packaging facilities. They won’t really come online until 2027-2028, but that at least gives us some time frame for when memory supply and demand could stabilize, with or without an AI bubble collapse.

Here’s hoping

What Micron, SK Hynix, and Samsung are doing in looking over the books of their customers feels like them expanding their influence even beyond being one of the most important technological bottlenecks facing the world right now. It feels intrusive, and even a little oppressive. They’re looking to control not only this limited supply of incredibly important hardware, but what their customers do with it, too.

But what’s good for them may be better for us, too. Demand policing doesn’t create new chips, but in reducing the phantom demand, they do lower overall demand, and bring back a little more predictability to an industry that has been racing ahead of everyone’s best guesses as the world panic bought what was available in a rush against one another.

Now, maybe the smaller buyers can compete because they aren’t trying to compete against capital and stockpiles. The memory makers can commit to capacity expansion without fearing a post-AI cliff face, as they did with the pandemic aftermath.

None of that is guaranteed, and the bigger buyers will continue to outweigh their smaller contemporaries and garner the priority they seek. But if it can slow things down just a little, it might make the next hard year ahead a little softer while we wait for that new capacity to come online in the years to come. Cutting that overbuying now is one of the few levers the industry can pull to prevent this cycle from getting far worse before it may get better.

Update 17/02/2026 9:30am PT: Article introduction amended to reflect that the memory makers are operating independently of one another.

ASML this week posted its highest yearly result ever as demand for its chipmaking tools set records. The company's revenue for the fiscal year 2025 totaled €32.7 billion ($39 billion USD), up 15% from the previous year. As expected, sales of lithography and other wafer fab equipment to China-based entities decreased in 2025 due to export rules imposed by the U.S. and the Netherlands. When it comes to sales of lithography systems, EUV tools became the leading source of ASML's revenue.

Fewer sales in China

Driven by the Made in China 2025 program and the buildout of the Chinese semiconductor industry amid tightening export curbs by the U.S. in recent years, ASML's sales to the People's Republic set records and culminated with 41% of the company's system unit share in 2024. Last year, sales of ASML's fab tools to China dropped, but 33% of ASML's tools (in terms of units) were sold to the PRC, meaning that Chinese chipmakers kept buying dozens of lithography and other machines for their fabs that use trailing nodes. Some of those older DUV systems are reportedly being upgraded by grey-market means.

China is followed by sales of wafer fab equipment to customers in South Korea (25%) and Taiwan (22%). By contrast, only 12% of ASML-produced tools (by unit count) were shipped to the U.S.

High-end EUV

U.S.-based Intel bought the world's first High-NA EUV Twinscan EXE:5200B lithography tool with 0.55 numerical aperture optics, designed for mass production of chips using next-generation process technologies, such as Intel's 14A (1.4nm-class). Another system was assembled at SK hynix's fab M16 in Icheon, South Korea. Meanwhile, ASML has supplied eight High-NA EUV tools (including six EXE:5000 and two EXE:5200B machines) to additional partners so far.

Speaking of EUV lithography systems, it's important to note that both current-generation Low-NA EUV scanners and next-generation High-NA EUV machines accounted for 48% of ASML's system revenue in 2025 (or €11.6 billion / $13.8 billion USD), up from 38% a year earlier. For the whole year, the company shipped 48 EUV systems and 131 immersion DUV tools, up from 44 EUV scanners and 129 immersion DUV machines in 2024.

Sales of EUV and sophisticated DUV tools are primarily driven by leading-edge logic fabs that build chips for AI infrastructure as well as smartphones and PCs. In fact, logic fabs accounted for 66% of ASML's system sales, whereas memory accounted for 34%. Although both logic and memory makers strive to increase their output and procure new tools, logic producers buy more expensive EUV systems.

"In advanced Logic, our foundry customers have become more positive on the long-term sustainability of demand on a number of fronts," said Fouquet. "AI accelerators are migrating from the 4nm node to the more litho-intensive 3nm node. At the same time, customers continue to ramp the 2nm node in support of next-generation HPC and mobile applications."

However, as DRAM vendors adopt more sophisticated fabrication processes that rely on EUV, they will also intensify procuring EUV scanners, which will significantly increase demand for this type of equipment as memory makers tend to operate very large fleets to fab commodity products in the most cost-efficient way.

"In memory, our customers are reporting very strong demand for both HBM and DDR products with supply remaining very tight through at least 2026 as they ramp both their 1b and 1c nodes in support of the demand," Fouquet added. "In addition, DRAM customers continue to adopt more EUV layers on these nodes. This is expected to continue on their future nodes as they migrate more multi-patterning DUV to single-exposure EUV, resulting in an increase in litho intensity."

Record results

ASML closed 2025 with a record fourth quarter and its strongest year ever. In Q4 2025, the company's revenue totaled €9.7 billion ($11.5 billion USD), its gross margin reached 52.2%, and net income hit €2.8 billion ($3.3 billion USD).

For the full year, the company generated €32.7 billion ($39 billion USD) in net sales, up from €28.3 billion ($33.8 billion USD) in 2024, with a 52.8% gross margin and €9.6 billion ($11.4 billion) in net income.

ASML's net bookings reached €28.0 billion ($33.4 billion USD), whereas their year-end backlog grew to €38.8 billion ($46.3 billion USD), another record for the company.

During the final quarter of 2025, the company supplied 94 new photolithography systems as well as eight used lithography machines. For the whole year, ASML sold 300 new lithography tools and 27 used lithography systems.

For the first quarter of 2026, ASML expects revenue of €8.2 billion – €8.9 billion ($9.7 - $10.6 billion USD), which is up year-over-year but down sequentially. Full-year 2026 revenue is projected to be between €34 billion and €39 billion ($40 billion - 46 billion USD), this reflects growing demand for lithography tools and EUV scanners, primarily due to the wide AI infrastructure buildout. Gross margins at ASML are projected to be between 51% and 53%.

"In the last months, many of our customers have shared a notably more positive assessment of the medium-term market situation, primarily based on more robust expectations of the sustainability of AI-related demand," said Christophe Fouquet, chief executive of ASML. "This is reflected in a marked step-up in their medium-term capacity plans and in our record order intake. Therefore, we expect 2026 to be another growth year for ASML's business, largely driven by a significant increase in EUV sales and growth in our installed base business sales. We continue to invest in people and footprint to support that growth in 2026 and beyond."

Looking ahead

Being the only supplier of EUV and advanced DUV tools on the planet, ASML has every reason to expect sales of these scanners to increase in the coming years. The number of EUV layers increases with the upcoming process technologies, driving its revenue all the way to €44 billion - €60 billion ($52 billion - 71 billion USD) in 2030. Indeed, EUV tools accounted for 65% of ASML's backlog in late 2025, up from 62% a year before. If the demand for their tools continues apace, then ASML will be sitting as one of the most important companies in the ongoing AI boom, right alongside Nvidia.

Micron this week announced that it had begun construction of a new advanced wafer fabrication facility in Singapore, which will take over 10 years to completely build and will cost about $24 billion. The new fab will produce 3D NAND memory with initial wafer output sometimes in the second half of 2028.

The new Fab 10B is being built at Micron's existing 3D NAND manufacturing campus in North Coast Wafer Fab Park in Singapore and is designed to deliver up to 700,000 square feet of cleanroom space once it's fully built out. To put the number into context, Micron's Fab 10A and Fab 10X have a cleanroom space of around 500,000 square feet, so the new Fab 10B will more than double Micron's 3D NAND capacity in Singapore.

"This investment underscores Micron’s long-term commitment to Singapore as an important hub in our global manufacturing network, enhancing supply chain resiliency and fostering a vibrant ecosystem for innovation," said Manish Bhatia, executive vice president of global operations at Micron Technology.

The new facility will be Singapore's first double-story wafer fab, which will enable Micron to build it out in iterations and without increasing actual footprint of the fab, which greatly simplifies building out the facility, albeit at the cost of more complex architecture.

The new Fab 10B will be configured in a way to support multiple next-generation 3D NAND manufacturing technologies, including nodes with over 500 active layers, so expect it to be equipped with the latest fabrication tools. In addition to volume production of 3D NAND, the new facility will also be used for R&D purposes, which will greatly simplify process integration and product ramps up. As an added bonus, the new facility will enable Micron to deepen its collaboration with academic and industrial research partners in the region.

Micron says that the new fab will focus on production of high-capacity 3D NAND devices for AI and data center applications, as the company considers these applications its major growth engines going forward. Still, it is necessary to note that the fab will be capable of making all types of 3D NAND devices if Micron needs to in response to future market changes. The current AI boom may or may not last beyond the 10-year timeframe it'll take for Fab 10B to become fully operational, so that versatility is welcome in the face of the typically cyclical nature of silicon demand.

In addition to producing 3D NAND in Singapore, Micron is also constructing an HBM assembly plant in the country. That HBM packaging operation remains on track to contribute materially to Micron's HBM output in calendar 2027.

From an employment standpoint, the new 3D NAND wafer fab is expected to create around 1,600 jobs, largely focused on fab engineering and manufacturing operations. Combined with the approximately 1,400 roles associated with the HBM packaging facility, Micron's current expansion plans in Singapore amount to about 3,000 new positions.

In an unexpected turn of events, Micron announced plans to buy Powerchip Semiconductor Manufacturing Corporation's (PSMC) P5 fabrication site in Tongluo, Miaoli County, Taiwan, for a total cash consideration of $1.8 billion. To a large degree, the transaction would evolve Micron's long-term 'technology-for-capacity' strategy, which it has used for decades. This also signals that DRAM fabs are now so capital-intensive that it is no longer viable for companies like PSMC to build them and get process technologies from companies like Micron. The purchase is also set against the backdrop of the ongoing DRAM supply squeeze, as data centers are set to consumer 70% of all memory chips made in 2026.

"This strategic acquisition of an existing cleanroom complements our current Taiwan operations and will enable Micron to increase production and better serve our customers in a market where demand continues to outpace supply," said Manish Bhatia, executive vice president of global operations at Micron Technology. "The Tongluo fab's close proximity to Micron's Taichung site will enable synergies across our Taiwan operations."

Deal expected to close in Q2 2026

The deal between Micron and PSMC includes 300,000 square feet of existing 300mm cleanroom space, which will greatly expand Micron's production footprint in Taiwan. By today's standards, a 300,000 square foot cleanroom is a relatively large one, but it will be dwarfed by Micron's next-generation DRAM campus in New York, which will feature four cleanrooms of 600,000 square feet each. However, the first of those fabs will only come online in the late 2020s or in the early 2030s.

The transaction is expected to close by Q2 2026, pending receipt of all necessary approvals. After closing, Micron will gradually equip and ramp the site for DRAM production, with meaningful wafer output starting in the second half of 2027.

The agreement also establishes a long-term strategic partnership under which PSMC will support Micron with assembly services, while Micron will assist PSMC's legacy DRAM portfolio.

The end of a tried and true model?

While the P5 site in Tongluo isn't producing memory in high volumes today, the change of ownership and inevitable upgrade of the fab itself will have an impact on global DRAM supply, which is good news for a segment that is experiencing unprecedented demand. While it is important that Micron is set to buy a production facility in Taiwan, it is even more important that the transaction marks an end to its technology-for-capacity approach to making memory on the island. In the past, instead of building large amounts of new greenfield fabs in Taiwan, Micron partnered with local foundries (most notably PSMC, but also with Inotera and Nanya) and provided advanced DRAM process technology in exchange for wafer capacity, manufacturing services, or fab access.

This approach allowed Micron to expand output faster and with less capital risk, leveraged Taiwan's mature 300mm manufacturing ecosystem, and avoided duplicating the front-end infrastructure, which was already in place.

However, it looks like the traditional technology-for-capacity model — which worked well in the 90nm – 20nm-class node era — no longer works. It worked well when DRAM fabs cost a few billion dollars, when process ramps were straightforward, and when partners could justify their capital risks in exchange for technologies (which cost billions in R&D investments) and stable wafer demand.

Today’s advanced DRAM fabs require $15 – $25 billion or more of upfront investment. This would go into equipment like pricey EUV scanners, as well as longer and riskier yield ramps. In that environment, a partner running someone else's IP absorbs massive CapEx and execution risk while getting limited advantages, which makes the economics increasingly unattractive: after all, if you can invest over $20 billion in a fab, you can certainly invest $2 billion in R&D.

The end of an era

In recent years, Micron's behavior has reflected this shift in thinking. Early technology-for-capacity deals helped it scale quickly, but once fabs crossed a certain cost and complexity threshold, Micron had to move on and own fabs instead of renting capacity. This is reflected in moves like its Elpida acquisition in 2013, where the company purchased a bankrupt memory maker to secure the company's capacity. This was followed up in 2016 with the Inotera acquisition, and now with PSMC.

What remains of the model is essentially pushed to legacy nodes, which are almost all fully depreciated, or to specialty DRAM, which does not require leading-edge process nodes. Other remnants of the model may be found in additional backend services, where capital intensity and strategic risks are also lower.

For leading-edge DRAM, ownership and control now outweigh the benefits of partnership, which marks the end of an era as modern fabs are now too expensive, too strategic, and too tightly integrated with product roadmaps. The acquisition of the P5 site was preceded by perhaps the last technology for a capacity partnership for Micron in Taiwan. Now, the American company will own the site and invest in its transition to its latest process technologies.

For the first time since announcing its seismic decision to kill its consumer SSD and memory brand Crucial, Micron has addressed the notion that it is leaving consumers behind in a new interview. The company also warned that despite breaking ground on new memory fabs, we shouldn't expect to see meaningful output impacting memory supply until at least 2028.

Micron's push back against the criticism of its decision to shutter Crucial comes by way of a WCCFTech interview with Christopher Moore, Micron's VP of Marketing, Mobile and Client Business Unit. The outlet wasted no time pressing Moore in Micron's controversial, but not entirely unexpected, decision to shutter the Crucial brand late last year. In early December, the company said that it plans to wind down its consumer business by the end of next month (January), reallocating its output and time to enterprise-grade DRAM and SSDs for AI buildouts.

Moore was asked if memory suppliers were inclined towards catering to the AI sector, "leaving consumers behind" as a result. "Well, first I would want to try to help everybody understand that the perception may not be exactly correct, at least from our point of view," Moore said. He stated that while he would "never want to tell someone what to think or that they're wrong... our viewpoint is that we are trying to help consumers around the world." Moore then cited Micron's sizeable businesses in the client and mobile market. Moore hinted that Micron is still technically serving consumers by supplying LPDDR5 to OEMs like Dell and Asus for inclusion in laptops, amongst other things. While this is technically correct, the news will be of little comfort to the DIY community and enthusiasts facing colossal price increases.

While the report claims Micron is in contact with "every single PC brand out there", the company simply cannot afford to ignore AI demand.

Some hope on the horizon for PC builders and the consumer sector is increased DRAM capacity in the supply chain. Micron recently announced it would begin work on a $100 billion New York 'megafab', where it plans to produce 40% of the company's overall DRAM output by the 2040s. Moore also noted its upcoming ID1 facility in Idaho, which is scheduled to come online in mid-2027. However, he warned that it will be 2028 before we see "real output, meaningful output," in its DRAM supply chain. Don't forget that Micron can't even keep up with current demand. Its CEO said in December that it can only meet half to two-thirds of demand, meaning that even the upcoming new capacity will initially go towards making up shortfalls for existing demand. As such, while 2028 might mark the first meaningful dent Micron makes in DRAM supply, it could be months more before consumers start to see any shift in pricing for PC builds.

Sandisk is on track to double the price of its high-capacity 3D NAND memory devices for enterprise-grade solid-state drives this quarter in anticipation of strong demand for server-class storage in the coming quarters, reports Nomura Securities (via @jukan05). It is unclear to what degree the price increase of high-capacity 3D NAND will affect quotes on mainstream flash memory used in client devices, but normally, 3D NAND for smartphones and PCs follows enterprise-grade chips as they are made at the same fabs.

"Channel checks indicate that several memory suppliers continued to push prices higher, with enterprise-grade NAND facing especially aggressive increases," a note to clients by Nomura Securities reads. "SanDisk’s NAND used in enterprise SSDs is cited as potentially rising by more than 100% quarter over quarter in the March period."

Nomura Securities, which is among the prominent financial analyst firms with good contacts in the high-tech industry, attributes plans of memory suppliers to increase prices of enterprise-grade 3D NAND both to short-term shortages and to mid-term growth of demand driven by AI in general and changes to AI storage in particular.

Nomura names Nvidia's Inference Context Memory Storage Platform (ICMSP) — which is based on the BlueField-4 DPU equipped with a 512 GB SSD that carries KV cache — among the demand drivers for enterprise storage this year. Every compute tray in the VR NVL144 rack is equipped with a BlueField-4 data processing unit with a 512 GB drive, making it 18 DPUs with 9.216 TB of 3D NAND per rack. Assuming that Nvidia ships 50,000 VR NVL144 racks per annum, the company will have to get roughly 0.439 EB of 3D NAND somewhere. Its partners supplying their versions of VR NVL144 racks with BlueField-4 DPUs will also increase their consumption of 3D NAND memory this year with the Vera Rubin platform.

While Nvidia's ICMSP can consume around an exabyte of 3D NAND per annum in 2026 ~ 2027 in the best case scenario, it cannot really be a reason for 3D NAND price doubling overnight, as the industry produces over 800 EB of NAND every year. Meanwhile, we still do not know how much 3D NAND a typical VR NVL144 machine carries, so we cannot estimate storage demands for Rubin-based platforms in general.

Nonetheless, as demand for AI systems for storage is skyrocketing in general, they will inevitably drive up demand, and once it outpaces supply, prices will get higher, which is exactly what we are seeing today.

Micron this week announced that it would formally break ground on its fab site in Onondaga County, New York, on January 16. When fully built, the new site will house four fab modules and will cost around $100 billion in total. All four fab phases are scheduled to be completed by 2041, according to the company. The site will be an instrumental part of Micron's plan to build 40% of its DRAM output in the U.S. by the 2040s, up from virtually 0% today.

Five years of reviews and approvals

Micron's fab complex near Clay, New York, will be the largest semiconductor production facility in the state, as well as one of the largest fab complexes in the U.S., which will also outpace the company's site in Idaho when fully operational. In addition, $100 billion represents the largest private investment in the state ever, and one of the most expensive semiconductor manufacturing operations in America.

The groundbreaking ceremony to be held next Friday follows rigorous environmental review and necessary permit approvals, which has taken Micron around five years, something that delayed the whole project by around half a decade. Surprisingly, the groundbreaking ceremony precedes ground preparation, which is a rather unique situation. Normally, groundbreaking follows ground preparation, not preceding it. Yet, ground preparation will start more or less in-line with the schedule that the company outlined in 2025.

Micron's Environmental Impact Statement (EIS) filing, published in November 2025, indicates that Fab 1 site preparation was set to start in late 2025, but was obviously delayed by several weeks. The construction of the first facility is now set to begin in late 2026, and will run through Q2 2028. Given that equipping a fab typically takes nine to 24 months (depending on how you count), Micron expects the fab to start operations as early as Q1 2029. However, it will still take some time before the fab is fully equipped and ramped, so expect tangible DRAM output from Micron's New York Fab 1 by 2030, around five years later than originally planned.

The same documents schedule Fab 2 to break ground in the second half of 2028, Fab 3 in the second half of 2033, and Fab 4 in the first half of 2039. As a result, Micron's fab site near Clay, New York, will reach its full build-out and volume production by 2045, again, roughly five years behind the original timeline.

A long road ahead

Micron's new campus in New York will manufacture DRAM using advanced process technologies and is ultimately planned to feature four fabs with four cleanrooms of 600,000 square feet (55,700 m²) each, constructed in four major build-out phases.

To put the 600,000 square feet number into context, GlobalFoundries Fab 8, located in Malta, New York, has a cleanroom space of approximately 460,000 square feet (though this is set to expand). The initial fab will cost around $20 billion, with successors expected to cost more, as Micron adopts more Low-NA EUV tools (priced around $235 million per unit) and eventually High-NA EUV tools (circa $400 million per unit) for its process technologies.

The New York complex will complement Micron's new site near Boise, Idaho. Last year, construction of the first new fab in Idaho (ID1) was completed, and the facility is now projected to begin wafer output in the second half of 2027. The company is also hard at work in its efforts to speed up the completion of its fab ID2, which will be built adjacent to ID1, benefiting from shared infrastructure and R&D co-location. It is projected that ID2 will start mass production of DRAM ahead of New York's Fab 1, though no further details are known.

Micron's wafer fabrication facilities near Boise, Idaho, will be adjacent to the company's R&D center, so will adopt the latest process technologies and will benefit from short feedback loops between the fab's process-integration teams and R&D personnel nearby. Such close collaboration will likely enable faster time-to-yield, which will improve Micron's profitability.

The close collaboration between process-integration and R&D teams will be particularly instrumental given Micron's current focus on high-capacity enterprise-grade DDR5 for servers and high-bandwidth memory (HBM) for AI accelerators. Both types of products tend to consume large DRAM dies, so rapid yield improvement is particularly important for these kinds of applications, as larger DRAM dies are expensive to make.

The grand plan

Right now, Micron has five wafer production facilities globally: two 3D NAND fabs in Singapore, a DRAM fab in Japan near Hiroshima, and two DRAM fabs in Taiwan (near Taichung and near Taoyuan). In addition, the company has an HBM packaging facility in Singapore, plans to build another fab module in Japan, as well as an HBM assembly plant in the U.S.

Given that the HBM packaging facility in Virginia is expected to come online after Micron ramps up production of HBM memory devices in Idaho, expect it to begin assembling HBM5 or HBM6 stacks towards the end of the decade.

Micron's grand designs include building 40% of its DRAM output in the U.S. by sometime in the 2040s. To achieve this, Micron plans to invest around $150 billion in six fab modules in America through 2045, as well as spending an additional $50 billion on R&D over the same period. However, it is unclear whether $50 billion will be spent exclusively in the U.S. (which will be a major boost for the American semiconductor industry) or whether it will be spread across Micron's R&D facilities across the world.

In any case, Micron's groundbreaking ceremony in New York next week will mark a key landmark in the company's expansion in the U.S. as well as a major milestone in the broad return of DRAM production to America.

Micron just announced the 3610 SSD, which offers PCIe 5.0 speeds with the higher density of Quad-Level Cell (QLC) chips. According to the company’s press release, this chip uses its G9 NAND that lets it achieve competitive PCIe 5.0 performance while offering more storage space in the same footprint. Because of this, Micron says that this is the first SSD in the world to offer 4TB in a compact single-side M.2 2230 form factor, allowing manufacturers to pack in so much more memory in thin-and-light laptops and handheld devices. Aside from the greater storage density, it’s also touted to have 43% better performance per watt for better power efficiency and battery life.

“The 3610 SSD combines cutting-edge PCIe Gen5 technology, Micron’s most-advanced G9 QLC NAND, and a sleek, single-sided design to deliver premium performance, capacity, and power efficiency,” Micron Mobile and Client Business Unit senior vice president Mark Montierth said. “The 3610 will enable ultra-thin devices that meet the growing demands of on-device AI, immersive streaming, and performance-intensive workloads.”

The memory and storage chip maker has previously used G9 TLC NAND on its high-end 4600 PCIe 5.0 NVMe client SSDs, which deliver a blistering 2.1M IOPS random read and write speeds, and up to 14,500 MB/s and 12,000 MB/s sequential read and write speeds in a 2280 form factor. While these are the best speeds that you can get from the company, it’s only available in 512GB, 1TB, 2TB, and 4TB capacities. While the brand-new 3610 SSD offers relatively lower speeds, Micron says that they’re still good enough for AI applications, capable of loading a 20-billion-parameter model in under three seconds.

More importantly, using QLC technology on the 3610 SSD means that Micron can cram more chips in a single wafer, cutting production costs and making PCIe 5.0 SSDs more accessible. And even though the denser design of this chip means that it likely runs hotter than previous generations, it comes with host-controlled thermal management, allowing it to run under for extended periods without compromising reliability.

Even though the company markets this for productivity devices and AI applications, handheld gaming enthusiasts will likely be excited for this chip to hit store shelves, too, as it effectively doubles the largest available M.2 2230 SSD on the market. This means that users can install several AAA titles on their devices without having to worry about running out of space. We don’t have pricing and availability information for these chips yet, especially as they’re still under OEM evaluation. Furthermore, we hope that this technology alleviates the ongoing storage crisis a bit, especially as it allows Micron to eke out larger storage capacity from the same wafer size.

Micron has secured another major vote of confidence from the Taiwanese government, winning approval for an additional NT$4.7 billion (approximately $149 million) in subsidies to expand HBM research and development in Taiwan. Combined with an earlier grant awarded in 2021, the total public support now approaches NT$10 billion, or roughly $318 million, making Micron the largest single recipient of Taiwan’s flagship industrial R&D subsidies to date.

The funding, approved by Taiwan’s Ministry of Economic Affairs under its A+ Corporate Innovation and R&D Enhancement program, supports a three-year project running from November 2025 through October 2028. Micron’s total budget for the effort is NT$11.75 billion, with the company covering close to 60% of the cost itself.

The goal is to develop and industrialize leading-edge, high-performance, and HBM technologies in Taiwan at a time when HBM has become one of the most strategically constrained components in the global semiconductor supply chain, driven by surging demand from AI accelerators, data center GPUs, and high-performance computing systems.

HBM as strategic infrastructure

HBM has shifted from a niche technology used in a handful of HPC accelerators into a foundational element of modern AI hardware. Unlike conventional DDR or GDDR memory, HBM stacks multiple DRAM dies vertically and connects them through an ultra-wide interface, delivering orders of magnitude more bandwidth per watt.

Current HBM3E stacks already provide several terabytes per second of bandwidth, feeding GPUs such as Nvidia’s H200 and AMD’s MI300X without becoming a performance bottleneck. Next-gen HBM4 pushes this further by doubling the interface width to 2048 bits and supporting taller stacks with higher-density dies. In doing so, HBM4-class memory enables larger models, faster training, and more efficient inference without relying solely on brute-force compute scaling.

This, unfortunately, has also turned HBM into a choke point. AI accelerators cannot ship without it, and the ability to produce advanced HBM at scale now directly limits how many high-end GPUs can reach the market. As a result, memory suppliers have found themselves graduating from being interchangeable commodity vendors to fully-fledged semiconductor industry behemoths whose roadmaps influence the entire AI hardware ecosystem.

That explains why governments are increasingly willing to subsidize HBM development, and Taiwan’s Ministry of Economic Affairs has been explicit that memory is the missing pillar in its semiconductor ecosystem. The island already dominates advanced logic manufacturing and chip design, but has historically relied on foreign suppliers for cutting-edge memory technology. Supporting Micron’s HBM R&D is a way to anchor that capability locally.

Micron’s position

Micron is the smallest of the three major HBM suppliers by volume, behind SK hynix and Samsung, but it has rapidly closed the tech gap over the past two product generations. Micron’s HBM3E has already been qualified by major accelerator vendors, and the company has publicly stated that its HBM capacity for 2026 is fully booked. The company recently made headlines when it axed its Crucial consumer business to enable the company to focus more on producing HBM and storage devices to feed the AI beast.

SK hynix, meanwhile, currently holds a dominant share of the HBM market and has reportedly committed much of its near-term output to Nvidia, while Samsung is investing aggressively to regain momentum, pushing 12-layer HBM3E and preparing for HBM4 transitions. In that environment, Micron’s ability to accelerate development, improve yields, and bring new stacks to volume production earlier than rivals could materially affect market share.

Taiwan also offers Micron more than just money. The subsidy requires R&D to be conducted locally and encourages collaboration with Taiwanese companies, particularly in equipment, materials, and advanced packaging. That’s key because HBM development is not just about DRAM cell design but also involves through-silicon vias, wafer bonding, thermal management, and increasingly complex interposer and advanced packaging technologies.

Taiwan’s semiconductor supply chain is exceptionally strong in these areas. Locating HBM R&D there shortens feedback loops between design, process development, and manufacturing equipment vendors, which can translate into faster iteration cycles and more predictable ramp-ups.

Implications for Taiwan’s semiconductor industry

From Taiwan’s perspective, this deal is about long-term positioning, with the government estimating that Micron’s DRAM and HBM investments could generate more than NT$800 billion in domestic output value and create over 20,000 direct and indirect jobs. Those numbers are ambitious, but they underscore the scale of economic activity tied to advanced memory manufacturing.

More importantly, HBM development reinforces Taiwan’s role as a system-level semiconductor hub rather than a single-node manufacturing center. As AI hardware becomes more tightly integrated across logic, memory, and packaging, geographic clusters that can support all three gain an advantage. Taiwan already hosts the world’s most advanced logic fabs and a dense network of OSAT and materials suppliers. Adding leading-edge memory R&D to that mix strengthens the entire ecosystem.

There are also the obvious geopolitical elements. Memory supply has become a major concern for both the United States and its allies, particularly as AI hardware increasingly underpins economic and military capabilities. Micron is the only major U.S.-headquartered DRAM manufacturer, so supporting its advanced R&D footprint in Taiwan aligns with broader efforts to diversify and secure critical semiconductor supply chains without concentrating all leading-edge development in a single country.

Ultimately, this subsidy reinforces the broader industry consensus that the HBM shortage is not a transient problem that’s going to resolve itself or be resolved through incremental capacity additions. There’s a serious, structural deficit driven by sustained AI demand and increasing technical complexity — moving from HBM3E to HBM4 brings all new architectures and closer integration with advanced packaging — and the only way to solve it is through solid, calculated R&D; government-backed funding can meaningfully influence how quickly the necessary transitions occur.

By offsetting some of the risk and cost, Taiwan is effectively saying that it thinks HBM will remain a bottleneck well into the second half of the decade, and that it’s a bottleneck worth solving.

The competition to calculate digits of Pi was initially an informal pursuit but grew more serious over time. Our server-oriented colleagues at StorageReview have proven that storage performance can make or break a Pi run, setting their latest record at a whopping 314 million digits with a single server that ran for four months.

Calculating Pi quickly became a way to benchmark the floating-point performance of CPUs. As the calculations grew ever larger, however, the task became more complicated, as RAM, I/O architectures, and storage systems came into play. That's a point StorageReview clearly illustrated by achieving a record with a single 2U server over a four-month calculation run.

The said machine is a Dell PowerEdge R7725 unit fitted with two AMD Epyc 192-core chips, for a total of 384 cores, along with 1.5 TB of DDR5 memory, an amount that could probably buy a small country at today's prices. The storage array is where this setup shines, though, with 2.5 petabytes of storage thanks to a 40-drive array of Micron 6550 Ion SSDs at 61.44 TB each.

It's long been the case that calculating Pi to such long extents requires a significant amount of bytes to store intermediate computations. After all, you're dealing with factors that are trillions of digits long. Past approaches, such as Google's 100-trillion record in 2022, used cloud server instances, and Linus Media Group and Kioxia's 300-trillion-digit run earlier this year used a Weka cluster with shared storage. But StorageReview opted to prove a point by using plain ol' simple fast local SSDs.

It's worth noting that one key factor enabling the 314-trillion-digit run is that, unlike the previous generation, the 17th-generation Dell servers used don't have a PCIe switch in their storage backplane; instead, they use a direct connection to the CPUs' PCIe lanes. With 40 bays, that works out to 2 to 4 lanes per SSD, but that still worked out to a meaty 280 GB/s of read/write performance, much higher figures than StorageReview's own past experiments.

There were additional relevant optimizations as well. The team tweaked the machine's scratch array for the patterns generated by the y-cruncher software at large digit counts. It also changed the server's standard air-cooling configuration to a CoolIT AHx10 setup, resulting in higher steady-state load clocks for the Epyc chips.

The power consumption was only 1,600W, a high number on its own but actually a pretty impressive figure as far as efficiency is concerned. Last but not least, the OS was changed from Windows Server to Ubuntu 24.04.2, a simple switch that resulted in better I/O performance on its own. We can't help but wonder if using the latest Windows Server release with native NVMe support would have been comparable. If you're curious about more details, go ahead and read the entirety of StorageReview's write-up.

As we detailed in October, the memory and storage markets were expected to face significant supply constraints. In the months following, DDR5 prices have skyrocketed. Kits that had sold comfortably below $100 months earlier were surging into the hundreds by early December. CyberPowerPC, one of the largest system builders in North America, warned in November that contract DRAM prices had jumped 500% since early October, while another report indicated that they had risen 171.8% year over year.

The disruption is being driven not by demand from gamers or device makers, but by artificial intelligence. Specifically, by the way hyperscalers are soaking up wafer starts and advanced packaging lines for high-bandwidth memory (HBM) used in AI accelerators.

The consequence is that anyone or anything that’s not part of that ecosystem — PC builders, laptop OEMs, and even phone makers — is fighting over the scraps of a shrinking pool of commodity DRAM. And with new fabs still years from coming online, the shortage is expected to last well into the second half of the decade.

RAM kits up 2-4x in a quarter

The most visible impact can be seen with retailers. A Corsair Vengeance DDR5-6000 32GB (2x16GB) cost $134.99 in September before reaching more than $420 in early December. G.Skill, TeamGroup, and Kingston all adjusted channel pricing by double digits across Q3, citing tightening availability.

That translated to a whopping 2-4x price swing for enthusiasts buying RAM, depending on capacity and bin. The G. Skill Trident Z5 Neo RGB DDR5-6000, our tried-and-tested best RAM for gaming, is now only available via third-party sellers through Amazon, with 64GB kits attracting prices beyond $500, with one seller listing them for a whopping $881.87 as of December 18.

Suppliers and distributors have sharply tightened allocation of DDR5 memory, with some channel partners reporting severely limited quotes and rollovers on orders as capacity is diverted to AI-driven demand. Reports from Taiwan and broader market tracking show memory modules selling out or being bundled to secure placement, indicating that mainstream buyers are being deprioritized.

That squeeze quickly filtered into GPUs, where memory is a major cost driver. AMD board partners raised card prices by around $10 per 8GB of VRAM starting in November. A rumor suggests AMD could increase Radeon RX graphics card prices with 8 GB models up by about $20 and 16 GB models up by about $40 in response to climbing GDDR6 spot prices and memory costs. SSD pricing has also reversed direction. 2TB Gen 4 NVMe drives that had been available for $80 in the summer were back at $130 by November. Contract pricing on NAND rose 60% in November, and module-level spot prices followed.

Framework was forced to increase its pricing on the DDR5 memory configurable in Framework Laptop DIY Edition orders by 50% in response to “substantially higher costs” they are facing from suppliers and distributors. Meanwhile, Dell and HP have both flagged component pricing, with HP’s CEO stating that memory costs in particular were affecting margin on consumer systems and Dell COO Jeff Clarke saying he’s “never seen memory-chip costs rise this fast.” Raspberry Pi also raised prices on its 4GB and 8GB boards, citing supply constraints on LPDDR4X.

Starving the market

All this is not being caused by insufficient demand for DDR5, but by wafer and packaging capacity being redirected to high-margin, high-volume AI parts. High Bandwidth Memory (HBM) is the main pressure point.

HBM differs from conventional DRAM in both structure and cost. Instead of planar dies mounted on PCBs, HBM stacks multiple DRAM dies vertically, linked with through-silicon vias (TSVs), and mounts them on an interposer alongside compute logic. These stacks offer enormous bandwidth and proximity advantages for AI accelerators, but they are incredibly expensive in terms of materials, tooling requirements, and especially wafer area.

Each gigabyte of HBM consumes roughly three times the wafer capacity of DDR5. That reflects both yield loss from stacking and the fact that many DRAM dies in HBM stacks are smaller or binned lower than equivalent RAM sticks. The TSV process and wafer thinning introduce additional steps that lengthen production cycles, leading to a catch-22 situation that, even when yields are strong, means the vertical integration of HBM requires advanced packaging lines that remain globally scarce.

SK hynix, the largest supplier of HBM to Nvidia, has told investors that its advanced packaging lines are at capacity through 2026. Micron, which supplies HBM3E to Nvidia and other U.S. clients, is in a similar position. Samsung has HBM capacity reserved through its Foundry and Memory business lines for tier-1 cloud clients. These lines are not interchangeable with conventional DRAM; tools, masks, and equipment for HBM production occupy space that would otherwise produce DDR5 or LPDDR5.

With wafer starts flat and packaging lines locked, every wafer pushed into HBM removes capacity from commodity DRAM and NAND. And the volume committed to AI is enormous.

The Stargate effect

In July, OpenAI and Microsoft finalized plans for Project Stargate, a multi-site hyperscale AI infrastructure program, with Samsung and SK hynix together committing to up to 900,000 DRAM wafer starts per month to support the buildout “at an accelerated capacity,” according to OpenAI.

That deal alone represents roughly 35-40% of global DRAM wafer capacity. The wafers will be used not just for HBM stacks, but for LPDDR and ECC DRAM used in adjacent server memory. Nvidia has its own multi-year agreements in place, reportedly accounting for the majority of SK hynix's HBM output through 2026. These allocations are inflexible, with contracts fixed, volumes tiered, and, in many cases, wafers fronted at favorable prices in exchange for capacity guarantees.

Naturally, memory vendors are reaping the rewards. Micron posted a record $11.3 billion quarter in Q4 2025, driven by HBM and enterprise DRAM margins. It subsequently announced plans to exit the Crucial consumer brand by early 2026. Executives stated that winding down Crucial would free up wafer supply for strategic accounts. “The AI-driven growth in the data center has led to a surge in demand for memory and storage. Micron has made the difficult decision to exit the Crucial consumer business... to improve supply and support for our larger, strategic customers in faster-growing segments,” said Sumit Sadana, EVP and Chief Business Officer.

Meanwhile, Samsung has raised its memory chip prices by up to 60% since September, driven almost entirely by the high demand for building new AI-focused data centers.

No new fabs until 2027

Memory makers are responding to surging demand by building new fabs, but the leadtime on greenfield facilities is long, and — of course — virtually all capex is going to go to HBM lines first, because that’s where the money is. Among the most notable investments is Micron’s $9.6 billion Hiroshima HBM facility, announced in partnership with the Japanese government. Construction of this fab is expected to begin around May 2026, with its first output expected in 2028.

Samsung is also committing billions in investments to new DRAM capacity in Pyeongtaek and Taylor, Texas. These sites will include HBM packaging and DRAM wafer lines, but company executives have cautioned that HBM and high-margin enterprise DRAM will receive priority through 2027. The company recently accelerated Phase 4 of its Pyeongtaek expansion in a renewed effort to reclaim leadership in the AI memory space. As for SK hynix, it’s expanding in Icheon — where it was the first memory maker to assemble ASML’s High-NA EUV lithography system — and Cheongju, with new DRAM output slated for 2026-2027.

Unfortunately, there’s no sign of the DRAM supply shortfall easing up before 2027. TrendForce has cautioned time and time again that capacity growth is limited relative to demand as AI and server requirements absorb a disproportionate share of wafer starts and production resources, and its pricing outlook shows DRAM contract rates continuing to rise through 2026 with constrained supply conditions. A leaked SK hynix internal analysis forecasts PC DRAM supply trailing demand until at least late 2028, and general industry consensus is that meaningful relief for DDR5 and LPDDR5 supply — at prices suitable for consumer SKUs — will not come until 2028 or 2029 at the earliest.

The situation is similar for NAND, with wafer investment having lagged since the 2022 price collapse. Most new NAND lines being built now are intended for enterprise SSDs or embedded memory for AI accelerators; client SSDs will see higher costs and tighter supply through 2026.

Consumers are now an afterthought

The effects of this reallocation are already locked into the next generation of consumer hardware, because memory decisions are made years in advance. Laptop platforms shipping in 2026 and 2027 are being finalized now, at a moment when DRAM and NAND supply are both constrained and volatile. That will have consequences that go beyond pricing.

Memory configurations that require large, predictable allocations of DRAM are riskier in a market where suppliers are prioritizing AI contracts and spot pricing can move sharply month to month. These conditions favor fewer SKUs and longer reuse of validated configurations rather than aggressive spec increases. Meanwhile, DDR4, which was expected to fade out quickly after DDR5 adoption ramped, is now likely to persist far longer in entry-level and midrange systems simply because its supply chain is more stable.

GPUs are in a similar bind. GDDR6 and GDDR6X, while not interchangeable with HBM, compete for wafer capacity and backend resources at the same suppliers. That makes large VRAM increases expensive at exactly the moment when software requirements are rising. This won’t necessarily mean fewer GPUs, but it could lead to slower movement at the top end of memory configurations, with vendors prioritizing yield and availability over aggressive capacity scaling.

NAND is under comparable pressure as investment in new client-focused capacity slowed down after oversupply and subsequent pricing collapse in 2022. What capacity is coming online is disproportionately aimed at enterprise SSDs and embedded storage tied to accelerators, where margins are higher, and contracts are longer. That leaves consumer SSDs exposed to price swings and supply tightening, particularly at higher capacities, even as PCIe generations continue to advance.

The problem is that none of these pressures are transient shocks that can clear in a quarter or two. The fabs that would meaningfully expand DRAM and NAND supply are not scheduled to come online until 2027 at the earliest, and even then, priority will remain with HBM and enterprise products. Consumer markets are now an afterthought among memory makers and, given the current state of AI, it’s difficult to see that changing.

Micron’s plans to shutter its Crucial consumer business next year did not stop the brand from appearing on the show floor at Delhi Comic Con over the weekend. A visitor took to X to share images of the Micron and Crucial branded booth, only days after the company told investors it would wind down consumer products by February 2026.

Micron’s presence was likely planned months in advance in collaboration with Indian partners and doesn’t represent a sudden U-turn on the decision to shutter its consumer business. Neither Micron nor Crucial is listed among the event’s headline exhibitors, and while Micron’s presence might seem unusual following last week’s announcement, it’s entirely understandable that the company wants to shift existing inventory ahead of February as the company reallocates its wafer supply to HBM and enterprise DRAM.

Ultimately, distributors and retailers still have stock to move, and partner booths at events and gaming shows remain one of the most effective ways to reach buyers in India’s growing PC market. Micron’s timeline gives those partners ample time to clear their shelves of soon-to-be-retired stock.

Micron’s December 3 announcement described a consumer exit shaped by AI demand rather than short-term performance in the retail channel. The company said it would retire Crucial as a consumer-facing business and concentrate investment on HBM memory lines feeding enterprise customers. The shift is intended to support advanced data-center products during a period of constrained supply and rising AI requirements.

HBM’s engineering is nothing like the consumer memory Micron is stepping away from. The technology stacks multiple dies into a single package and links them through dense vertical interconnects, producing far higher bandwidth per watt than conventional DDR and turning memory into a performance enabler rather than a bottleneck.

That is important at a time when hyperscalers are racing to stand up ever-larger AI clusters and where each new generation of GPUs pushes memory throughput harder than capacity. For Micron, the growth prospects and margins attached to HBM outstrip anything available in the price-sensitive retail channel, and the company’s decision places its wafer supply squarely behind the memory technologies that now define competitiveness in AI infrastructure.

In the meantime, consumer inventory remains, and resellers need to continue to promote it to shift inventory. The Delhi Comic Con booth is simply a reflection of that fact; a snapshot of a brand still active in public even as its parent company prepares to abandon consumers and concentrate on more lucrative memory technologies.

In keeping with the spirit of times, Micron on Wednesday announced plans to wind down its Crucial consumer business worldwide by the end of February 2026. The company is reallocating its output and investments to enterprise-grade DRAM and SSD products amid growing demand from the AI sector.

Micron will continue shipping Crucial-badged consumer products through retailers, online stores, and distributors until the end of its fiscal second quarter, which concludes in late February 2026. After that point, Micron will no longer supply the consumer channel with products under the Crucial name, but will continue to ship its Micron-branded enterprise portfolio, which will remain available through commercial and server-focused partners.

After Micron ceases to ship its Crucial devices, it will continue honoring warranty obligations and technical support for existing Crucial products. Customers who already own Crucial-branded memory modules, SSDs, and other products will continue to receive service coverage well after shipments stop, so the decision will not leave installed hardware unsupported.

As expected, Micron is abandoning its consumer business due to reallocation of its 3D NAND and DRAM output and production capacity to enterprise-grade SSDs, high-bandwidth memory (HBM) for AI accelerators, and server-grade memory modules.

"The AI-driven growth in the data center has led to a surge in demand for memory and storage," said Sumit Sadana, EVP and Chief Business Officer at Micron Technology. "Micron has made the difficult decision to exit the Crucial consumer business in order to improve supply and support for our larger, strategic customers in faster-growing segments."

Micron established its Crucial brand some 29 years ago, in 1996, when the enthusiast-grade hardware market began its rapid growth. Over time, Crucial got particularly successful in retail, where its name became synonymous "with technical leadership, quality and reliability," as Micron puts it. However, the current market situation is by far not favorable for these types of products, so instead of shrinking its Crucial portfolio, the company decided to wind it down entirely, albeit without selling off the Crucial brand (at least for now).

There are several reasons behind Micron's decision.

Firstly, client memory modules and SSDs sit at the lowest-margin end of Micron's portfolio as they compete in highly volatile, price-competitive, and promotion-driven market. Even though the Crucial and Ballistix brands still matter, they are squeezed between high-end enthusiast brands and low-end consumer brands, which makes their evolution difficult. By contrast, data center and enterprise products lock in long-term contracts, higher ASPs, and more predictable demand.

Secondly, the supply environment has changed permanently. AI infrastructure requires every single wafer with memory it can consume, something that has never happened with any industry megatrend previously. This means that every wafer Micron assigns to consumer parts is a wafer not going to a hyperscaler or enterprise contract. As a result, keeping a consumer line would directly limit Micron's ability to fulfill orders from its largest customers, which is a risk for profits and strategic relationships.

Thirdly, even a small consumer business would still require a minimum viable supply chain, including product development, firmware validation, compliance testing, sales teams, retail relationships, and global warranty operations. Such fixed costs barely shrink when volume shrinks, so a reduced consumer business would still burn resources while losing the economies of scale that make the segment viable.

As a result, it strategically makes far more sense to wind down consumer operations entirely and free production capacity, R&D, and product engineering resources for premium products like HBM4/HBM4E/C-HBM4E, enterprise drives, and high-density server memory modules.

Micron indicated it will try to reduce the impact of the decision on employees through internal reassignments into existing vacancies elsewhere in the company.

The ongoing structural change of the DRAM market caused by the shift of manufacturing capacities to production of high bandwidth memory (HBM) for AI accelerators has already caused a massive price hike of commodity DDR and LPDDR memory — but the worst is yet to come.

According to the general manager of Chinese memory giant TeamGroup, contract prices of DRAM and NAND products have almost doubled recently. Supply of commodity memory is set to worsen in early 2026, and normalization is unlikely before 2027 – 2028 when more production capacity emerges, reports DigiTimes.

December contract prices of some categories of DRAM and 3D NAND increased 80% to 100% month-on-month, according to Gerry Chen, general manager of TeamGroup, a prominent maker of memory modules, solid-state drives, and products based on 3D NAND. Spot prices tell a similar story. A 16Gb DDR5 chip was priced at $6.84 on average at DRAMeXchange on September 20. On November 19 average spot price was $24.83, but on December 1 average spot price of a 16 Gb DDR5 IC increased to $27.2 (session low was $19, session high was $37).

Essentially, memory alone for a 16 GB memory module costs around $217.6. A PCB, assembly, and testing, additional parts like PMIC will add $8 – $10, so a 16 GB memory module now costs $225 – $228 without manufacturer premiums, logistics, and taxes.

Chen expects availability of DRAM and NAND to worsen in the first and second quarters of 2026 once distribution stockpiles are exhausted. At that point, he cautions, obtaining allocation could become difficult regardless of willingness to pay. In his view, relief would not come quickly: he projects the current shortages to extend into late 2027 and potentially beyond.

The reason for shortages of commodity memory is well known: DRAM makers reallocate their production capacities to HBM (which uses larger DRAM dies than commodity types of memory) that is consumed by AI accelerators, like Nvidia's B300 or custom accelerators by large cloud service providers, such as AWS, Google, and Microsoft. These companies tend to book supply years in advance, so at some point, DRAM makers will not have enough capacity to meet demand for commodity DRAMs.

Building a new greenfield fab takes at least three years, so even if companies like Micron, Samsung, or SK hynix made a decision to build a memory fab today, it would come online in late 2028 at the earliest and would be fully ramped only sometime in 2029.

When it comes to NAND, NAND suppliers also prioritize large customers, which happen to be makers of AI servers. Chen does not expect capacity to swing back to PCs, smartphones, and other consumer devices in 2026, which will affect the prices of these devices.

The effects are clear to see. Enthusiasts are seeing RAM prices for custom-built PCs increase by orders of magnitude week on week, with 64GB of DDR5 RAM now costing more than a PS5 in some cases. This week's Black Friday and Cyber Monday RAM deals might be the last chance to buy RAM before prices skyrocket even further.

Micron is preparing a major expansion of its Hiroshima operations to build a dedicated high-bandwidth memory (HBM) facility, according to a report by Nikkei Asia. The report says the company intends to invest 1.5 trillion yen — US$9.6 billion — in a new plant on its existing site, with construction scheduled to begin in May next year. Shipments would follow around 2028. Japan’s Ministry of Economy, Trade and Industry (METI) is expected to contribute up to 500 billion yen in subsidies to support the project, though neither Micron nor METI has confirmed the report.

HBM has arguably become the most constrained component in the AI supply chain, giving the project some real weight in terms of government subsidies. SK hynix currently leads the market and has committed most of its HBM, DRAM and NAND output to Nvidia through 2026. Samsung is working to catch up with its 12-layer HBM3E stacks, while Micron has pushed hard to grow its own presence through HBM3E supply deals with Nvidia and AMD. TrendForce data shows Micron moving toward roughly a quarter of the HBM market with 20% of shipments as production increases; a dedicated Hiroshima expansion could shift that balance further once it comes online.

Japan has been aggressive in courting this kind of investment, offering substantial government incentives to foreign chipmakers as part of a wider effort to rebuild domestic semiconductor capacity. TSMC’s Kumamoto fabs and the state-backed Rapidus project are already part of this strategy.

Micron itself has been a significant beneficiary. Last year, Micron announced plans to introduce EUV-based DRAM production on the same Hiroshima campus, investing 500 billion yen of its own cash and supported by nearly 200 billion yen in subsidies. The first LPDDR5X memory devices produced on its 1γ process at this facility then began sampling in May of this year.

The scale of the planned plant aligns with expectations for the next generation of AI accelerators. Nvidia and AMD are both shifting towards HBM4 and HBM4E, both of which require tighter process control and higher layer counts. Capacity has been thin throughout the current GPU cycle, with long lead times and allocation limits driven by the mismatch between demand and available wafer starts. If Micron’s new plant reaches volume production in 2028, it will arrive just as those next-generation GPUs are.

For Micron, Hiroshima offers political and financial stability at a moment when both geopolitics and the market cause increasing uncertainty, and Tokyo’s willingness to fund a third of the project removes some of the risk from a multiyear build. The long runway to 2028 also gives Micron a clear path to expand its role

Micron has published the final draft Environmental Impact Statement (EIS) for its fabs near Clay, New York, which reveals the final schedules for construction of four fabs starting late 2025 through 2041. Meanwhile, a report from Syracuse indicates that the company is accelerating its Idaho fabs and reallocating CHIPS Act funding to that facility.

"Micron remains focused on bringing leading-edge memory manufacturing to New York, and we appreciate the strong partnership with federal, state, and local authorities," a Micron statement supplied to Tom's Hardware reads.

According to Micron's official draft EIS document released back in June and the latest draft EIS published in November, the construction phase for the first fab (Fab 1) would start from late 2026 (after a year of preparations that start in late 2025, according to the company's U.S. expansion plan unveiled on July 1, 2025) and will last till the second half of 2028, or early 2029. It usually takes 12 to 24 months to fully equip a fab, depending on various factors; hence, it is reasonable to expect the first fab to start DRAM production sometime in 2030, five years later than initially expected. Yet, Micron believes it can partly equip its Fab 1 in three quarters and begin operations in Q1 2029.

The same environmental documentation pins Fab 2's construction start to the second half of 2028, Fab 3's construction start to the second half of 2033, and Fab 4's construction start to the first half of 2039. This way, the Micron Clay campus will be fully built and ramped to full production by 2045, which is five years behind schedule.

"Micron would mobilize for initial site preparation for the Proposed Project beginning in the fourth quarter of 2025, with the first two DRAM manufacturing facilities (Fabs 1 and 2) estimated to be operational by 2029 and 2030, respectively, and the remaining fabs (Fabs 3 and 4) estimated to be operational by 2035 and 2041," a statement by Micron from the EIS submitted in June reads.

Micron reportedly acknowledged an amendment to its $6.1 billion CHIPS Act funding agreement with the U.S. Department of Commerce, as the company is reportedly bringing forward its ID2 facility in Idaho. The two Idaho facilities — one existing and one newly planned — will be completed ahead of those in Clay, which means that there is a strategic reshuffling of project priorities in place.

As part of the alleged realignment, Micron redirected about $1.2 billion of its federal grant from New York to Idaho, reducing Clay's share from $4.6 billion to $3.4 billion. The company reportedly indicated that the update was consistent with evolving project requirements under the federal agreement. Local authorities, including Onondaga County Executive Ryan McMahon, reportedly attributed the delay of Micron's New York campus to widespread labor shortages and the longer construction cycles that have become.

The realignment of the projects in America probably does not affect Micron's ultimate goal to produce 40% of its DRAM output in the U.S. as the company prioritizes one project after another, not delaying new fabs altogether. Meanwhile, prioritization of the fab ID2 will have a positive effect on Micron's output of HBM memory in the U.S., as the company also intends to build an advanced packaging facility for HBM and other types of memory that require stacking and advanced packaging in Idaho.

The DRAM supply chain is choking, and server memory is taking the first hit. According to DigiTimes, major U.S. and Chinese hyperscalers are now receiving just 70% of the server DRAM they order. That’s despite agreeing to contract price increases of up to 50% for Q4, well above the 30% hike many buyers had budgeted for earlier this year.

Naturally, AI sits at the core of all this. While it’s HBM that gets the headlines, demand for conventional DDR5 RDIMMs is also outpacing supply, particularly at advanced nodes where Samsung and SK hynix have diverted capacity toward parts bound for AI acceleration. Samsung’s recent pricing adjustments confirm the reprioritization, with the company having raised server SSD prices by up to 35% and RDIMM contract rates by as much as 50%, citing sustained demand from enterprise and cloud customers.

What’s left is a market where even the largest buyers can’t secure enough memory. Spot prices have surged since late September, and several top-tier suppliers are reportedly refusing to quote for October allocations. DDR5 16 GB modules that traded at $7 to $8 last month are now hovering around $13, with availability tightening further into November. Module makers are bracing for out-of-stock situations by the end of the quarter.

The rest of the market fares worse. Channel players and smaller OEMs are seeing order fulfillment rates closer to 35% to 40%. With hyperscalers locking in fixed allocations, lower-priority customers are pushed to the spot market or told to wait until capacity opens up in 2026.

Micron warned of this in its most recent earnings call, telling investors that DRAM is a “tight industry” and that bit supply growth will lag demand through the end of next year. TrendForce also flagged a potential quote freeze across certain modules, as suppliers shift to day-to-day pricing in China and avoid locking themselves into bad deals.

This is causing retail DDR5 prices to creep upward, with no sign of stabilization before year’s end. DDR4, meanwhile, is in slow decline. China's Nanya Technology recently said standard DDR4 makes up just 20% of the total DRAM market, and it’s no longer being prioritized for volume production. Unless demand unexpectedly cools or yields improve sharply, DRAM allocation for everyone outside the top buyers will be constrained into 2026.