Nvidia and SK Group this week signed letters of intent to formalize their new strategic relationship valued at more than $500 billion. The strategic collaboration is multifaceted and includes a long-term memory supply agreement with SK hynix unveiled in June, SK Telecom's plans to build a 2-gigawatt AI data center based on the latest Nvidia hardware, and future expansions of AI infrastructure.

In addition to the multi-year memory supply and co-development agreement between Nvidia and SK hynix, the key part of the strategic relationship is SK Telecom's planned 2-gigawatt AI data center in South Korea. The installation will rely on Nvidia's DSX AI factory platform and deploy Vera Rubin accelerated computing systems equipped with SK hynix HBM4 memory. The first AI data center is set to enter service in 2027. The companies intend to use this infrastructure to support sovereign AI, enterprise AI, physical AI, and agentic AI deployments across South Korea and the Asia-Pacific region. In addition, the companies will work together on expansion of SK's AI infrastructure going forward, which is a rather vague way to say plans to deploy future AI platforms from Nvidia.

The most important part of the announcement is, of course, the gargantuan value — $0.5 trillion — of the intended strategic relationship. Based on what is disclosed, the figure is best interpreted as the aggregate value of commercial activity expected between the companies over several years, as it bundles together AI infrastructure construction and a long-term memory supply agreement under one umbrella. That activity likely will include the following:

• SK Telecom's purchases of Nvidia GPUs, networking equipment, systems, and other hardware for its AI data centers.
• Supplies of SK hynix memory to Nvidia under the long-term supply agreement.
• Revenue of Nvidia's ecosystem partners involved in building the DSX AI factories (OEMs, ODMs, networking, storage, cooling, power, etc.).
• Potential future expansion beyond the initial 2 GW deployment.

Speaking of the 2 GW AI data center, it is safe to say that it is going to use thousands of NVL72 VR200 racks and hundreds of thousands of Vera CPUs and Rubin AI GPUs. Unfortunately, this is as accurate as we can get with the rather vague announcement.

Nvidia describes DSX as a complete AI factory blueprint that combines its accelerated computing hardware, networking, software stack, and partner technologies into a data center-scale platform designed to deliver the lowest-cost token generation and maximum energy efficiency. Meanwhile, NVL72 VR200 will come with 166 kW – 240 kW per-rack power consumption ratings, whereas DSX can be deployed in various kinds of facilities with different power usage effectiveness (PUE). Since we do not know which NVL72 VR200 configuration SK Telecom plans to use, and since the PUE of the upcoming SK Telecom facility is unknown, it is impossible to estimate the number of racks and AI accelerators with any accuracy.

Jensen Huang joined X last month and used his first post Friday to promote Open Weights and American AI Leadership, a three-page policy letter published the same day and co-signed by 25 companies, including Nvidia, Microsoft, Meta, IBM, Dell Technologies, Palantir, and Hugging Face.

The letter asks Washington to avoid what it calls "premature restrictions on downloadable AI models," and comes just four days after the Trump administration was reported to be reviving a push to ban Chinese models — though the document doesn't directly mention China, Moonshot AI, or DeepSeek. Notably missing from the co-signers are OpenAI, Anthropic, and Google.

The 25 names break down into chipmakers, server vendors, cloud operators, enterprise software firms, security companies, and venture funds: Nvidia, Dell, Microsoft, IBM, Box, ServiceNow, CrowdStrike, Palantir, Telnyx, Replit, Perplexity, Andreessen Horowitz, Y Combinator, and Emergence Capital among them. The model developers on the list, Meta, Mistral, Black Forest Labs, Arcee AI, and Reflection, all publish weights already.

Also present on the list of signatories is the Linux Foundation, which stewards the OpenMDW-1.1 license Nvidia used to release Nemotron 3 Ultra in June, a 550-billion-parameter model that Artificial Analysis scored at 47.7 on its intelligence index against 53.9 for Moonshot's Kimi K2.6.

"The world needs both frontier closed models and frontier open models," Huang wrote in his X post. At Nvidia's CES 2026 press Q&A earlier this year, he put a figure on the shift, saying one in every four tokens generated today comes from an open model. Weights that anyone can download get served from enterprise clusters, regional clouds, and on-premises racks rather than a handful of hyperscaler API endpoints, and those buyers have no in-house TPU or Trainium program to buy instead. The letter's policy section asks for expanded compute access for startups and researchers, alongside public investment in shared datasets and evaluation frameworks.

The letter goes on to urge policymakers not to treat distillation — the practice of training one model on another's outputs — as misappropriation, arguing that unlawful extraction from closed models should be handled through targeted legal frameworks, rather than broad limits on the technique.

Treasury Secretary Scott Bessent said on Fox Business earlier this week that the administration would examine Chinese open-source models for intellectual property theft and could sanction the companies behind them, telling the program that officials had found watermarks from U.S. large language models in Chinese systems. Huang told Axios two days later that American firms should be allowed to use Chinese models, calling claims of Chinese backdoors a misconception. The distillation passage is the only part of the letter that doesn't concern open weights.

On this day in 2006, AMD confirmed its acquisition of graphics chip firm ATI. AMD stumped up a cash and stock deal worth a total of $5.4B for the Canadian PC graphics innovators. With 20/20 vision now 20 years on, we can see the deal helped AMD prosper on three fronts: continuation and innovation of Radeon GPUs, the rise of the APU, and AMD’s dominance in the console business. That’s not all, of course, and it is also interesting to recall that AMD approached Nvidia before it bought ATI.

AMD CEO Hector Ruiz and ATI CEO Dave Orton appeared together in New York on the morning of July 24, 2006, to publicly announce the deal. Ruiz told the press that the deal, unanimously approved by the directors of both companies, would "reinvent our industry." The AMD CEO went on, “We believe AMD and ATI will drive growth and innovation for the entire industry, enabling our partners to create differentiated solutions and empowering our customers to choose what is best for them.” Orton added that “Joining with AMD will enable us to innovate aggressively on the PC platform.”

In the next couple of years, the ATI graphics brand slowly melted away. For example, the ATI R600 (Terascale 1, unified shader architecture) GPU, which was in development at the time of the acquisition, would become the Radeon HD 2900 series under AMD branding. As a transition product, some HD 2900 XT boxes would still carry ATI packaging and branding. Taking the cooling solution off an AMD graphics card, you might still see an ATI GPU under the thermal paste, all the way up to around 2010. In 2011, Tom’s Hardware published its 25 Years Of Graphics History: A Farewell To ATI, In Pictures, which is a must-read for fans of the era.

While graphics card development rolled on in a tit-for-tat battle with Nvidia, AMD’s next fortuitous chunk of synergy came from integrating its Radeon IP alongside its CPU cores to create APUs. It started this journey with the AMD Fusion line in 2011. Nowadays we have APUs that have taken this vision far further, with the Ryzen AI Max / Max+ (Strix Halo and Gorgon Halo) series. The integrated graphics on these processors pack up to 40 RDNA 3.5 Compute Units and can go toe-to-toe with desktop graphics like the RTX 4060/4070, depending on workload. They also benefit from unified memory, allowing users to configure oodles of VRAM, if they have it spare.

As the Radeon developers forged ahead moving from the GCN to RDNA graphics architecture era, AMD saw an opportunity in the console space. From the early to mid 2010s, AMD made inroads into APU development that meant the processors became attractive solutions for console developers. It still holds pretty tightly to that market today, which has spilled over to handhelds. However, Intel looks far more serious in this market now, with Panther Lake and B390 iGPUs. Moreover, Nvidia could surely make a dent on consoles with Arm plus GeForce semi-custom SoCs if it wasn’t living it up in the lucrative AI market.

Red and green would never be seen

Before the AMD and ATI deal was inked, reports indicated there were chances of a similar merger involving AMD and Nvidia. Our 2012 report on this ‘missed opportunity’ suggests Jensen Huang was being quite difficult during the negotiations. Apparently the man in the leather jacket insisted that he become chief executive of the combined company. That made Hector Ruiz pretty cool on the prospect, so AMD’s attention was diverted towards ATI.

Nvidia CEO Jensen Huang thinks that American companies should be allowed to use Chinese AI models, even as Washington is trying to ban them. When Axios co-founder Mike Allen asked Huang in an interview if Americans companies should be allowed to use Chinese AI models, Huang responded with “absolutely.” The answer comes right after Chinese firm Moonshot AI released a 2.8T open-weight model called Kimi K3, which — although it isn’t as powerful as frontier models like Fable 5 — is comparable to GPT 5.5 and Claude Opus 4.8 while costing just a third of these models.

One of the biggest concerns of U.S. leaders have is that these AI models might come with vulnerabilities that the Chinese government can use to attack American interests, but Huang said that this is an incorrect assumption. “There is a misconception that somehow there are backdoors that are somehow connected to China in some way,” said the Nvidia chief. “You download the models, you can fine-tune it, you can enhance it, you can guardrail it as you desire.”

Huang shares the same sentiments about American AI models. Just last month, the U.S. enforced an export restriction on Anthropic’s Mythos and Fable 5, citing security threats — although access was eventually restored after its developer placed a filter to block these tools from identifying software vulnerabilities. OpenAI’s ChatGPT-5.6 received the same treatment, and Washington warned the firm that it should not release its latest model without getting the green light from the government. Huant argues that, instead of restricting access to these powerful models at launch, AI firms should make their models available to all and make them more secure through rapid testing and fixes.

But even as he advocated the need for everyone to have access to closed models, Jensen also noted that various industries, such as the sciences and cybersecurity, need open models as well. He claims that these models make AI more secure, as other people can inspect them to look for weaknesses and fix them as required.

“If everything just becomes one single model, one single point of attack, one single source of failure, I think the world is much, much more vulnerable,” Huang said.

As for the market’s negative reaction every time cheaper, open-weight models become available, the Nvidia CEO says that investors misunderstand their impact. Huang said that this happened when DeepSeek arrived for the first time, and it’s happening again with the arrival of Kimi. He says that these open models, which cost less to run, will encourage more people to use AI. So instead of cutting data center demand, these cheaper, more efficient models are actually good for the industry in general because they will drive demand. (And with higher demand, there’s more incentive to build data centers and buy AI GPUs, which is ultimately good for Nvidia.)

Nvidia invited a group of about a dozen journalists out to the company's HQ to learn more about its Vera CPU, as well as how it fits into the larger Vera Rubin NVL72 rack design at the heart of Nvidia’s next-gen agentic AI platform. Part of that was seeing Vera Rubin in action, not as a disassembled tray on stage or a rack with a few blinking lights at a trade show — real racks running real workloads in a (partially) real data center. And we got to see those racks in action at Nvidia’s Engineering SuperLab.

It’s not a proper data center, or at the very least, it’s a sub-optimal data center. Nvidia was clear that the Engineering SuperLab is built for engineers, allowing them to quickly stand up and swap out racks to see the hardware in action. You could sense a bit of insecurity in the air; if Nvidia were building a proper data center, it wouldn’t look like this. This lab is where the engineers live, and if you’ve ever been around a group of engineers with a lot of hardware to play with, you know that things aren’t always as tidy as you’d expect in a proper data center.

The SuperLab Nvidia showed us is one of four nondescript locations near Nvidia HQ. These locations haven’t, up to this point, been disclosed. Each of the four locations has popped up over the last two years, giving Nvidia some floor space to play with as it rolls out new hardware.

The hardware in question here is the Vera Rubin NVL72 rack, but we saw a few other demonstrations, as well. Most notably, Nvidia showed us a sidecar running 800VDC power into an NVL72 rack. Nvidia also laid out some parts, demonstrating the assembly process for a Vera Rubin tray, which slides together with various retention arms in a matter of minutes.

This is a look behind the scenes of our tour, how the Engineering SuperLab is set up, and some choice data center eye candy. We’ve published a full breakdown of the Vera CPU and how it fits into Nvidia’s larger AI infrastructure, which goes into the technical details of the platform. Here, we’re mainly giving you a peek behind the curtain.

Nvidia Vera Rubin NVL72 running in the flesh

Vera Rubin is in full production, and we’ve seen some short videos of racks being stood up in data centers. But this is our first look at a rack running a real workload in the flesh. Nvidia says the racks here are running some workloads for OpenAI, in fact, and as you can see from the image above, it looks like some trays are running OpenAI’s GPT‑Rosalind model.

On the front of each tray here, you can see the ports for the dual ConnectX-9 NICs, along with the Bluefield-4 DPU in the middle. Around the back is Nvidia’s NVLink spine, an almost mediaeval-looking contraption, with sharp pins that connect the various trays together. It houses 5,000 copper cables that measure over two miles in length, delivering up to 3.6 TB/s of bandwidth per GPU and 260 TB/s of scale-up bandwidth per rack, on Nvidia’s sixth-gen NVLink.

Each Vera Rubin NVL72 rack houses 18 compute trays and 9 NVLink switch trays, the latter of which orchestrate communication between the various trays to function as one large, unified system. Nvidia demonstrated the MGX NVL design for us, which is a single reference rack with 72 Rubin GPUs and 36 Vera CPUs. Nvidia’s MGX ETL design replaces the NVLink spine with either a Spectrum-X Ethernet spine or direct chip-to-chip spine for a scale-out system featuring up to 256 GPUs.

The business-end of things is around the back of the racks, though. Although the back is clear of cabling thanks to the NVLink spine, power and coolant delivery are still a major factor. The organized chaos of the piping and cabling you can see in the images below shows just how much goes into standing up even one rack, let alone dozens or hundreds in a data center.

Nvidia’s previous-gen GB200 and GB300 NVL72 racks featured hybrid cooling, but Vera Rubin trays are entirely cooled by liquid. There aren’t any fans, which Nvidia says could, eventually, lead to much quieter data centers. That wasn’t the case in the lab here, which still called for eye and ear protection. I didn’t have a decibel meter handy — imagine if I carried one around with me casually — but my guess is that it was somewhere around 80 to 90 decibels inside; louder than an A/C unit, but quieter than a motorcycle. That’s a fairly typical noise level for a data center.

Regardless, Vera Rubin trays are entirely liquid cooled, with a process called “dry cooling.” Assuming the inlet temperature of the coolant is 45 degrees Celsius or less, Nvidia says it’s able to cool the entire system with a heat exchanger. If true, that would cut costly (in terms of power, space, noise, water consumption, and actual dollars) chillers out of the cooling equation.

Massive piping brings the coolant in (usually antifreeze or deionized water) at the top, and there are outlets at the bottom of the rack to move the warmed coolant out. Along the way are a series of inlet connections that allow trays to automatically hook into the cooling system, leaving just the main connections at the start and end of the loop. Nvidia has standardized everything on a Vera Rubin NVL72 rack with the Open Compute Project (OCP), even as far as shipping specifications. The company says just 47 minutes passes from when the truck pulls up to powering on the rack.

800VDC power for next-gen AI infrastructure

Nvidia also showed us an 800VDC “sidecar” in action. If you’re unfamiliar, Nvidia (along with other AI infrastructure companies) have been pushing for a new 800VDC power delivery system for modern data centers to reduce AC/DC conversion inefficiencies, as well as deliver the necessary wattage to racks without pushing into current ranges of thousands of amps.

A single Vera Rubin NVL72 rack can easily consume over 200 kW, which is a challenge for traditional power infrastructure in a data center. With current Grace Blackwell racks, power shelves convert the AC power coming into the facility (at 415V or 480V) to 48V/54V Direct Current for distribution within the rack. The problem here is pretty straightforward. If voltage stays constant, and wattage increases, then current also needs to increase. And more current means thicker bus bars, more conversion inefficiencies, and more rack space dedicated to power delivery.

Again, the solution that 800VDC represents is pretty straightforward. If wattage increases and current stays constant, voltage also has to increase. The idea is to convert AC power from the grid to DC power once, and then use a series of DC-to-DC converters within the rack, allowing for denser compute and better power efficiency.

This is not an easy problem to solve, as data centers need to change how power is brought into the facility, not just how it’s converted, stepped down, and moved around. Here, Nvidia showed off a sidecar, which is a rack filled solely with power equipment. This is a “retrofit,” as analyst firm SemiAnalysis calls it, representing the first in a series of transition phases to 800VDC. 415V/480VAC is still distributed throughout the facility, but it flows into this sidecar rather than power supplies within the rack. The sidecar rectifies the 415V/480VAC to 800VDC and feeds adjacent racks.

This is all an explanation to show some pretty interesting power infrastructure at play in this lab. Nvidia isn’t the first, nor only, company pushing toward 800VDC infrastructure, and companies like Google, Meta, and Microsoft have contributed to open sidecar designs like the Mt. Diablo spec. Still, it’s interesting to see one of these sidecars in action.

If you haven’t seen a peek behind the back end of a rack, you can see the large red connectors in the gallery above that bring power into the racks. You can also see the massive power cables and connectors at the rear of the 800VDC sidecar.

Nvidia’s next-gen AI infrastructure laid out

At the front of the facility, Nvidia laid out all of the components of its next-gen AI infrastructure. There’s nothing here we haven’t already seen before, though it's normally seen buried in trade show displays or featured on stage during a keynote.

First is the Vera Rubin NVL72 tray itself, which you can see above sitting next to a GB300 tray. Both are DGX designs, meaning they’re fully built and integrated by Nvidia, and you can see just how stark of a difference there is in assembly right away. The Vera Rubin NVL72 tray features only two cables, no hoses, and no fans. At the rear where the two Super Chip boards live, Nvidia demonstrated a retention arm that allows the boards to slide in and out in a matter of seconds.

The Vera Rubin tray is much cleaner, but it also makes better use of the space. It doesn’t include fans, which you can see take up a significant section in the middle of the tray in the GB300 design. With Vera Rubin, those fans are replaced with the thick midplane you can see above, offering a communication channel between the two ConnectX-9 NICs and Bluefield-4 DPU at the front of the tray.

Holding one of the two cables inside of a Vera Rubin NVL72 compute tray is the busbar, which handles power routing for the different chips inside the tray.

The Vera Rubin NVL72 tray is, of course, not the only deployment of Nvidia’s next-gen AI hardware. The company also showed us a CPU-only tray with eight Vera chips, offering up to 256 chips within a rack. That gives us a closer look not only at the chip itself, but also the SOCAMM2 LPDDR5X memory system, offering similar density and modularity as traditional RDIMMs at a far lower power cost.

Although most of the modules were unlabeled, we were able to snag the picture you can see above showing where the modules came from. These are 128GB SOCAMM2 modules from Micron running at 6400 MT/s, and as you can see from the photo, the slots aren’t all populated. This is the big advancement with SOCAMM2, offering up modularity for a memory standard that is otherwise soldered.

Nvidia’s NVLink handles scale-up communications, split across NVLink switches in the rack and the NVLink spine that you can see above. Nvidia describes sixth-gen NVLink as “putting the oven in the car.” Its goal is to get all of the chips in a rack communicating with each other, ensuring critical operations (like baking the pizza) happen as close to the destination as possible.

Scale-out communication, on the other hand, is handled with ConnectX-9 NICs in the tray and the Spectrum-X CPO (co-packaged optics) switch tray. The Spectrum-X switch tray is massive, and it’s a good illustration of just how much physical space is dedicated to communication (over raw compute) in a modern AI data center.

Of course, the size of the switch tray depends on how wide the scale-out infrastructure is. Nvidia also showed a smaller Spectrum-X CPO tray for smaller deployments. That's all we managed to see at Nvidia's AI data center SuperLab. Vera Rubin is in production, and will roll out in the second half of 2026.

Nvidia's upcoming Vera Rubin platform, set to arrive later this year, will take the stage as the AI world shifts towards an era dominated not by frontier training runs but by the demands of agentic AI inference at massive scale. The hunger for generated tokens in agentic workflows and the demands of delivering them quickly, efficiently, and at low unit cost now dominate the discussion.

We’ve already gone in depth on new performance data around the Vera CPU and how it helps to accelerate agentic AI workloads, but that’s not all Nvidia is sharing today. It’s also detailing some new features of the Rubin architecture and how those features are meant to increase inference efficiency from the GPU level to rack-scale and data-center-scale implementations of this accelerator platform.

The full Vera Rubin NVL72 rack-scale system is built up from 36 Vera CPUs and 72 Rubin GPUs, but our focus today is on the GPU proper. Rubin joins two compute dies onto a single package using the Nvidia High Bandwidth Interface. The resulting chip offers 224 Streaming Multiprocessors (SMs) containing a total of 896 Tensor Cores alongside 288GB of HBM4 memory providing 22 TB/s of memory bandwidth.

As an inference-focused accelerator, Nvidia touts Rubin’s 50 sparse PFLOPS of NVFP4 inference throughput as its headline performance figure, although that’s only one of a dizzying array of data types this chip can handle. Here are some key rates to keep in mind for this chip so far:

Let’s dive into some of Rubin’s refinements for inference workloads to understand how Nvidia aims to keep all of those resources fully utilized.

The Rubin Tensor Memory Accelerator efficiently manages growing MoE models

First up, Nvidia highlights efficiency improvements in the Tensor Memory Accelerator (TMA) that help feed the Tensor Cores with data. The TMA is a dedicated engine built to handle memory address calculations and perform direct loads of array data into a GPU's shared local memory.

Leading AI model architectures have moved from dense models where every parameter is activated per output token to a mixture-of-experts (MoE) architecture where only certain specialized sub-networks are activated per token, based on the guidance of a router that helps judge which experts are best suited to processing a given input.

MoE expert weights can be distributed across GPUs in order to efficiently utilize limited per-GPU HBM capacity. Nvidia says that Rubin's TMA has been improved to deal with the challenges of managing the growing numbers of experts in today’s leading models.

The TMA in Blackwell GPUs needed to maintain separate MoE descriptors in memory for the location of every expert, meaning that the overhead of locating and moving those expert weights requires more compute resources as the number of experts grows.

The Rubin TMA now supports GPU kernels that maintain and update a single unified MoE descriptor directly in the TMA instruction at runtime, reducing computation of MoE descriptor metadata and requiring less calculation overhead for data movement. This approach frees up GPU cycles for inference calculations, which is, of course, the place that you want your expensive AI accelerator spending the vast majority of its time.

Doubled K-dimension throughput, double the Tensor Core output

Rubin also improves the fundamental performance of matrix operations in the Tensor Core by doubling the amount of work those cores can perform on the K dimension, or the shared inner dimension of a pair of matrices to be multiplied. Without going too deep into the math, the size of the K dimension is directly related to the number of times the Tensor Core has to loop over the elements of the two matrices being multiplied.

In Nvidia's example, then, the calculation of a result matrix that would require four loop iterations on Blackwell can be completed in only two on Rubin. Nvidia says this improvement has wide-ranging benefits for throughput-, memory-, and latency-bound kernels, and it’s helpful for both context processing and decode phases of inference.

Softmax on Rubin gets up to a 4X boost versus Blackwell

Rubin also focuses on improving the performance of the attention mechanism that’s foundational to transformer-based LLMs More advanced models now support context lengths of up to a million tokens, and quickly performing attention calculations on such long input sequences quickly is a key driver for improved inference performance.

Softmax is an essential operation in attention calculations, and in order to keep up with the improved Tensor Core throughput in Rubin, Nvidia has once again boosted softmax throughput in the GPU SM’s Special Function Unit (SFU).

Since it relies on the transcendental math capabilities of the SFU, softmax throughput can become a bottleneck for subsequent inference work, and it's a limitation that Nvidia already sought to address with enhancements to the Blackwell Ultra SFU. Blackwell Ultra doubled FP32 and BF16/FP16 exponential throughput compared to the first-gen Blackwell GB200.

Rubin maintains Blackwell Ultra's 2X speedup over Blackwell in FP32 exponential math, and it doubles BF16/FP16 exponential calculations again compared to Blackwell Ultra, leading to a 4X improvement in throughput compared to Blackwell for those lower-precision data types.

Finer-grained dependency management, better Tensor Core occupancy

Rubin also increases Tensor Core occupancy by providing finer-grained opportunities for coordination between dependent kernels than on Blackwell. One case that Nvidia cites where these dependencies arise is the generation of activations for an LLM, where one kernel produces and stores data that is then used by a subsequent kernel as a prompt proceeds through a neural network.

On Blackwell GPUs, a long-running producer kernel on one thread block (perhaps within a CUDA structure like a cluster) might delay the execution of a subsequent consumer kernel on those thread blocks, even as other thread blocks of the producer kernel have finished their work.

Rubin offers finer-grained dependency resolution between kernels, such that a consumer kernel can begin executing on individual thread blocks as soon as the producer kernel’s output from each thread block becomes available, instead of waiting for the entire batch of producer kernel data to become available. This finer-grained management results in better GPU utilization, lower kernel-to-kernel latency, and ultimately increases tokens per second per user.

More efficient inter-GPU communication, lower NVLink overhead

All of the improvements we've discussed so far relate to how work happens on one GPU, but the Vera Rubin NVL72 rack-scale accelerator comprises many GPUs connected over an NVLink fabric within the rack. Model weights, key-value cache data, and inter-GPU synchronization messages all move over this fabric, so keeping overhead and latency low is key to realizing maximum performance.

GPUs running CUDA kernels can directly initiate communication with other GPUs in the rack using Nvidia Collective Communications Library (NCCL) API, lowering overhead. Nvidia notes that because the GPU performs those operations directly as part of the compute kernel, the efficient execution of those communications becomes critical to performance.

On a Blackwell system, an NVLink transfer between GPUs might require data store operations followed by a memory barrier and an atomic flag. The Rubin architecture introduces a feature called counted writes that reduces the amount of coordination and synchronization traffic necessary to share data between GPUs across the fabric.

On Rubin, the memory barrier and atomic operations are replaced by a single write counter update on the receiving GPU, reducing network traffic and latency and improving compute utilization by reducing the time spent waiting for coordination overhead.

All told, in tandem with the high single-threaded performance of the Vera CPU for agent harnesses, tool calling, code compilation, and more, the improvements in the Rubin GPU for performance on critical inference operations, as well as improved efficiency for data movement on-chip and across the rack, promise to help create a rack-scale and data-center-scale system that will both increase inference performance and lower per-token inference costs in the increasingly agentic future that Nvidia envisions. We’re excited to see more of what this GPU can do as deliveries of Vera Rubin systems are set to begin this fall.

Nvidia’s Vera CPU is its first bid to become a key player in the data center CPU market. Although Grace has seen some success (most notably with Grace standalone deployments at Meta), Vera is Nvidia’s first CPU with a custom core design. It’s arriving at an ideal time, as well, with the server CPU market exploding in the last few months on the back of agentic AI demand.

Vera isn’t a chip built to chip away at the market share of AMD and Intel in the cloud. It’s built to grab market share in an expanding market, as hyperscalers look to widen AI infrastructure beyond legacy clouds. As such, it’s designed in a much different way than Nvidia’s x86 competitors, and it even holds some unique architectural design points compared to the swath of Arm-based designs.

Nvidia has slowly revealed more details about Vera as it ramps into general availability, which is on track for the back half of this year. Now, we have a full picture of the chip. Nvidia shared its Vera white paper, along with unofficial SPEC CPU 2026 results comparing Vera to AMD’s Turin-based Epyc 9755.

We’re going to break down the white paper here, including all of the details about the Olympus core and a look at the benchmarks Nvidia ran. At the end of this piece, we’ll also take a brief look at the larger context of Vera and how it fits into Nvidia’s wider AI ecosystem compared to standalone deployments.

But plenty of ink has been spilled about Vera’s technical capabilities and Nvidia’s next-gen AI infrastructure vision. Let’s start with the important thing: the benchmarks.

Nvidia Vera CPU benchmarks

We’ve seen Vera in action before, though only through a series of selected benchmarks ran at Nvidia HQ by Phoronix. In the Vera white paper, Nvidia shared benchmarks for SPEC CPU 2026, specifically the integer suite from SPECrate, against AMD’s Epyc 9755, with both chips running in a dual-socket configuration. Before getting into the results, there are some important notes about how SPEC runs work, and the reporting criteria for them.

Nvidia’s run here isn’t official, as Vera was tested in a reference system due to the fact that it’s not broadly available yet. It’s ramping for general availability in the second half of the year. Due to that, Nvidia is unable to report its results. That’s why you see “estimated” in some of the charts below. Nvidia ran SPEC CPU 2026; it’s not extrapolating expected performance like we’ve seen from AMD so far with its upcoming Venice chips.

SPEC CPU 2026 is split into four suites, but Nvidia tested the SPECrate integer suite, which is focused on system throughput with integer-based workloads. The “rate” result is looking at how much work is completed within a certain amount of time. Here, each thread in the system has a copy of the workload. The score is how much time it takes for those workloads to complete, regardless of thread count, naturally giving chips with more cores an advantage.

If you want more detail on the benchmarks included in the suite, make sure to read our original coverage of SPEC CPU 2026. Here are the overall results:

Nvidia didn’t share the exact results for the 9755 it tested, short of the overall score of 898. Taking that overall score into account, Vera is 3% ahead of the 9755. It’s worth noting that Vera is ahead here despite a large thread disadvantage. An overall score of 898 for a dual-socket Epyc 9755 system isn’t unreasonable compared to publicly-submitted SPEC CPU 2026 runs, though higher results have been published. SPEC CPU ships as source code, which the tester must compile with their compiler of choice, and that can heavily influence results (particularly with vendor-specific compilers). Nvidia used GNU 15.2 with both systems.

Above, you can see Vera’s results stacked up against the 9755, but these aren’t comparing the numbers directly. Nvidia has normalized the per-core performance, which isn’t how SPECrate results are normally shared. According to the overall numbers, Vera is still completing more work within the same amount of time, despite a thread disadvantage, but the margins aren’t in the range of a 70% or 80% advantage as the above chart suggests.

We asked Nvidia about the results given that they're obfuscated by comparison; we could not reverse-engineer the Epyc 9755's scores with the information Nvidia has provided. Here's the response it gave: "Per-core performance under a fully loaded socket is important because agentic AI and RL run many sandboxes concurrently, while each agent step remains sequential and latency-sensitive. It measures how much performance each core sustains amid contention for shared power, memory, cache, and fabric. We therefore normalize by physical core, with SMT enabled on both systems."

The “agentic” workloads Nvidia has highlighted here are code compilation and interpretation workloads, which is something an agent is often doing, querying repos for dependencies and building source code. Below are data science workloads (or Exploratory Data Analysis), and below that are data processing workloads like SQLite database management. The results here align with Nvidia’s overall messaging of Vera, that it’s highly competent at data-rich, backend operations.

Although Nvidia is sharing per-thread results, it argues that SPECrate is still the correct benchmark to run. The per-thread results here are in the context of a fully-loaded socket. Here’s the justification from the white paper: “This metric is non-trivial for agentic AI and RL systems, where many sandboxes, tools, and environments run concurrently rather than as isolated single-thread tests. Fully loaded per-core performance captures how well each core sustains throughput while sharing socket-level power, memory bandwidth, cache, and fabric resources.”

In addition to running the workloads, Nvidia analyzed the code execution for architectural benchmarks, which you can see in the gallery above. Nvidia claims an overall IPC gain of up to 1.9x compared to Turin, up to 2.3x more branch predictions and 3.5x taken branches per cycle, and up to 2.4x higher instruction fetch operations per cycle.

Outside of SPEC, Nvidia shared a few benchmarks highlighting the capabilities of the Olympus core. First up is PageRank, an algorithm developed by Google to originally rank web pages, which highlights Olympus’ prefetch engine. Nvidia scaled this workload to higher core counts, showing Vera maintaining much of its single-core performance up to 32 cores, while the Turin chip hits a wall around 20 cores.

In addition to the above results, Nvidia shared some tests of the Vera memory system compared to Turin. These microbenchmarks are good for validating Nvidia’s specifications, but they’re looking at architectural performance, not application performance. An architectural advantage translates into a performance advantage, but not always in a linear, expected fashion.

Nvidia used internally-developed tools for the memory tests, though they're available on GitHub for anyone to run.

First is loaded memory latency, stressing the memory subsystem as bandwidth usage increases. Vera has much higher bandwidth overall, but you can see the Turin chip hit a latency wall below its maximum, which Nvidia attributes to Non-Uniform Memory Access (NUMA) domain traversal and CCD-to-CCD latency.

Looking at per-core bandwidth, Nvidia claims Vera provides more than four times the bandwidth of AMD’s 9755. The suggestion here is that “real-world” per-core bandwidth is even better than Nvidia’s specs lead on (or perhaps worse than AMD’s).

Maybe the most consequential of these tests is the one you can see above, looking at core-to-core latency. It’s no secret that crossing the CCD on AMD’s chiplet-based architecture incurs a big latency penalty. You can see that in action even in our Ryzen 9 9950X3D2 review, and the penalties compound as you scale up the number of CCDs.

In fairness to AMD here, chiplet-based designs aren’t built for this type of cross-CCD traversal, preferring to keep workloads localized and optimizing for core density. Vera’s design goal is clearly to keep latencies consistent across the entire die and sacrificing core density in the process. Nvidia’s Ian Buck told us that this design trade-off “will come at the cost of the legacy workload,” when we recently visited Nvidia HQ.

That’s important context. Nvidia isn’t gunning to steal existing market share from AMD and Intel as much as it’s trying to grab market share in an expanding market before AMD and Intel can. Some financial institutions (including Morgan Stanley and Bank of America) suggest the server CPU market could double in size (or grow even larger) by 2030. That context is important because there will be a continuing demand for CPUs that can handle workloads Vera is not optimized for, and it’ll be interesting to see how AMD and Intel tackle that dynamic with future products, trying to keep a legacy base of customers while pushing ahead into the expanded market.

Nvidia clearly has a vision of how that expanded market looks, and to that end, hasn’t shared SPEC CPU floating point results. Presumably, this is due to the fact that SPEC’s vectorized suite is focused primarily on HPC workloads, whereas Nvidia focused on what it believes are critical agentic workloads that are integer-based. Vera has a vector engine complete with SVE, but that doesn’t seem like Nvidia’s focus.

In an end-to-end Nvidia system, those vectorized workloads would be offloaded to a Rubin GPU. Still, we don’t have any vector results for Vera yet. Up to this point, we’ve only seen integer results, which is strange given the memory system at play in Vera.

Vera is Nvidia’s first CPU with a core design created in-house, which is the Olympus core. It’s built on Arm v9.2-A, but the design was created by Nvidia, unlike Grace, which leveraged a stock Arm design. Each Vera CPU has 88 Olympus cores on a monolithic die, breaking from the chiplet-based designs available from Nvidia’s x86 competitors.

Nvidia says Vera comes with a 1.5x increase in instructions per cycle (IPC) throughput compared to Grace, and 50% higher performance compared to x86 competitors (it seems that number is per-thread performance with a fully-loaded socket). Nvidia has a single 88-core design with Vera that supports spatial multithreading for 176 threads.

The CPU has a configurable TDP range of 250W to 450W. It uses a SOCAMM2 LPDDR5X memory system with capacity of up to 1.5 TB and speeds up to 9600 MT/s, and comes with 164 MB of L3 cache and 2 MB of L2 per core. Vera includes significantly less L3 than Intel’s highest-specced Xeon 6 and AMD’s Zen 5 chips. It actually has more L2 than L3 overall. This, presumably, is due to Nvidia’s fabric, which distributes the L3 in a mesh across the monolithic die.

Below, you can see a layout of the Olympus microarchitecture. Nvidia has disclosed some of the highlights of the architecture previously, such as the 10-wide instruction decode and neural branch predictor, but we now have a full view of the architecture courtesy of Nvidia’s Vera white paper.

The front end starts with Nvidia’s neural branch predictor that can run two branches per cycle “with zero penalties,” according to Nvidia. Research on neural branch prediction dates back to the late 90s, but Nvidia says it has a “novel” neural branch predictor, perhaps building on previous research such as BranchNet.

The BPU feeds into the Instruction Fetch Unit, which holds 64 KB of L1 instruction cache, and loads into a decode queue that supports 48 instructions (we’ll go into the memory/cache layout later). At the last stage of the front end is that 10-wide decode, feeding more instructions into the execution engine per cycle than the 8-wide decode in AMD’s Zen 5 microarchitecture.

Past the front end, the mid-core rename / allocation engine is built to keep instructions moving while waiting on dependencies. In addition to renaming and allocation, instructions work through value prediction, which can speculatively execute the instruction, and memory renaming, where the instruction can move forward while a load is happening if the data relationship can be determined.

Inside the execution engine, Nvidia includes eight simple Arithmetic Logic Units (ALUs), two complex ALUs, and four branch units for resolution. For SIMD instructions, the execution engine includes a vector cluster for Arm’s Scalable Vector Extension (SVE), including six vector units that support 128-bit SVE instructions at FP8 precision, along with two crypto-enabled vector units that can handle AES, SHA, and SM3, among other prominent algorithms. Keeping data moving through the engine are four load units and two store units.

The cores support spatial multithreading, giving a Vera CPU with 88 cores access to 176 threads. Traditional SMT time-slices execution, giving both threads access to all of the core resources and sharing them as instructions execute in parallel. With spatial multithreading, each thread of an Olympus core has access to dedicated resources, allowing one of the threads to execute with high-throughput while the other thread handles simple tasks, or to operate as two independent execution environments.

The execution resources are partitioned, explaining the wide decode front end. It’s not clear, however, if the SMT implementation can also opportunistically grab resources, particularly in the scenario Nvidia describes where one of the threads is maximizing throughput while the other handles smaller tasks.

There’s a lot going on in Vera between the 10-wide decode, neural branch predictor, and spatial multithreading, but perhaps the most significant architectural design point is Nvidia’s second-generation Scalable Coherency Fabric (SCF). It underpins Nvidia’s approach of using a monolithic die as opposed to a chiplet-based design, distributing last level cache in a mesh across the die and avoiding the cross-CCD latency penalty with localized L3.

The mesh distributes data through a series of Coherency Switch Nodes (CSNs) that serve as routing points between cores and the 164 MB of distributed L3. These routing points further connect the cores and L3 to the memory system, I/O, and NVLink C2C for cache-coherent communication between chips. Nvidia’s benchmarks comparing Vera to AMD’s Epyc 9755 show that AMD can achieve slightly lower core-to-core latencies within a cluster, but Vera maintains significantly better core-to-core latency across the die, as expected.

Nvidia says SCF inside Vera has 3.4 TB/s of bandwidth, enabling faster core-to-core communication, especially when traversing the die. However, Vera also supports Memory System Resource Partitioning and Monitoring (MPAM), allowing portions of L3 to be partitioned in multi-tenant environments.

Vera uses SOCAMM2 LPDDR5X, which is a relatively new advancement that Nvidia’s competitors haven’t had the chance to benefit from. With the use of SOCAMM2, LPDDR5X provides similar modularity and capacity as traditional RDIMMs, but at significantly lower power draw.

The memory can run at up to 9600 MT/s, with aggregate bandwidth of 1.2 TB/s and per-core bandwidth of 14 GB/s, doubling the bandwidth of Grace. The Vera board supports eight SOCAMM2, offering capacity ranging from 256 GB to 1.5 TB. Nvidia claims a “fully populated” memory subsystem consumes between 30W and 40W depending on capacity.

For I/O, Vera supports PCIe 6.4 with 88 lanes per CPU and bifurcation support down to x2. It also supports CXL 3.1.

Unlike Grace, Vera includes Arm’s Confidential Computing Architecture (CCA) and Realm Management Extension (RME), including Device Assignment and Coherent Device Assignment, offering a boon to multi-tenant environments where VM isolation is key. Nvidia also implements TDISP for coherent devices, allowing for encrypted communication between GPUs and PCIe devices.

Nvidia is already sampling Vera as a standalone chip to partners, and it says it will continue to do so, but the vision is an end-to-end solution built on Nvidia’s CPUs, GPUs, switches, NICs, and even rack specifications. Nvidia doesn’t make all of these individually, at least not at scale — just like with desktop graphics cards, Nvidia provides its MGX reference design, which customers can purchase, but partners also offer their own racks, some built solely to Nvidia’s specifications and others with more speciality.

Each tray comes with two Vera Rubin superchips, each of which contain a single Vera CPU to two Rubin GPUs, giving you two CPUs and four GPUs per tray. At the front, Nvidia partitions off three spaces, with the MGX design carrying two NVIDIA ConnectX-9 SuperNIC on either side and a Bluefield 4 DPU in the middle. Critically, this design doesn’t include any hoses or fans. It’s entirely liquid cooled, and it contains just two cables throughout the entire tray.

Nvidia demonstrated this cable-less design, showing the Vera Rubin Superchip sliding in and out of the track with a retention mechanism in a matter of seconds. The company says assembling the rack takes less than a few minutes and is handled entirely by robots, which is a far cry from GB200 and GB300 trays.

GB200 and GB300 trays are dense designs, but they’re also cluttered with cables and hoses. Nvidia says this massively slowed down production time, eventually leading to production issues that delayed Nvidia’s rollout. The company says that won’t happen with Vera Rubin and its largely cable-less design. Whereas a Grace Blackwell tray took around two and a half hours to assemble by a human, the company says a Vera Rubin tray is assembled within five minutes and entirely automated by robots.

Each tray needs to dissipate several kilowatts of heat, which Nvidia says it’s able to do using dry cooling. Liquid cooling is nothing new in the data center, either through an external chiller (essentially an A/C unit) or evaporation, where a fan evaporates water over a mesh and cools without the need for a compressor. With Vera Rubin, Nvidia uses “dry cooling,” with a maximum inlet temperature of 45 degrees Celsius.

Nvidia says it’s able to get the full performance out of a tray given an inlet temperature of 45 °C, allowing trays to operate without an additional water consumption in environments up to 100 degrees Fahrenheit. The tray essentially uses a large closed-loop similar to what you find from a consumer AIO, just scaled up. Water moves out of the tray and outside the data center, and it passes through a radiator where fans dissipate the heat. There’s some extra power consumption from water pumps and fans, but not nearly on the scale of evaporation methods or chillers.

The result is a tray completely free of fans, essentially noise-less in operation, and doesn’t strain local water infrastructure. That’s what Nvidia says, at least. In many locations around the U.S. where data centers are located (Texas and Virginia chief among them), temperatures easily climb above 100 °F during the Summer, prompting some sort of backup method of cooling. Nvidia says the external temperature ceiling can go higher depending on different factors — running at lower power, for example, and using more efficient heat exchangers — but under normal conditions, 100 °F is the ceiling.

It’s worth noting that nothing about a Vera Rubin tray explicitly requires this method of dry cooling; the hardware is just capable of offering full performance with an inlet temperature of 45 °C.

In addition to an NVL72 design, Nvidia has a Vera standalone deployment that compacts each tray into a series of SOCAMM2 slots and Vera chips. In Nvidia’s 48U MGX design, a standalone Vera deployment can include up to 256 CPUs in a rack.

Underpinning scale-up communication is Nvidia’s sixth-generation NVLink, which is deployed as switches in the rack and connected to compute trays using Nvidia’s NVLink spine. You can see the spine on its own in the image above, which features over two miles of thin copper wire to allow every tray in the rack to communicate with each other.

Localizing storage, networking, security, and telemetry operations is Nvidia’s BlueField-4 DPU. A Vera Rubin NVL72 compute tray includes a single DPU and two ConnectX-9 NICs to maximize CPU/GPU utilization. You can read more about Bluefield 4 in our original coverage from GTC.

Nvidia’s Ian Buck, vice president of hyperscale and high-performance computing and the inventor of CUDA, says the company has “shipped... let's put it in the hundreds of thousands of Grace standalone servers.” In May, Nvidia disclosed that it had shipped over 2.5 million Grace CPUs in total, and the company announced a partnership with Meta to deploy standalone Grace servers in February. Buck’s comments suggest the scale of deployment may be even larger, however, as Nvidia tries to compete in a market dominated by other players.

It’s an interesting comment, though not a surprising one. Nvidia has become the dominating force of Silicon Valley as demand for its GPUs skyrocketed during an unprecedented data center buildout for AI inference. Since peaking earlier this year, however, around $1 trillion in Nvidia’s market cap has been wiped away as investors rally behind CPU makers like Intel. Evolving agentic AI workloads have changed the hardware balance, shifting away from as many as eight GPUs per CPU, toward a one-to-one ratio in some cases.

Nvidia wants to ride that train with its new Vera CPU, which was architected specifically for those types of workloads. Even before the recent rise of agents, however, Nvidia says it has seen demand for its CPUs for data-hungry workloads. “They weren’t running a web server [with Grace]… or they aren’t being used for, what the cloud uses, of cheap, dollar-per-core,” Buck said. “They were being deployed for the backend, data-rich operations, like the data processing.”

Grace represents an on-ramp for Nvidia into data center CPUs. It uses 72 stock Arm Neoverse V2 cores, but it’s differentiated by Nvidia’s Scalable Coherency Fabric (SCF). Vera uses an updated SCF, but it also features Nvidia’s first custom core design, called Olympus. Grace cracked the door, and Vera represents Nvidia's big entrance into the market against AMD and Intel.

Regardless of where Vera ends up in the battle of next-gen data center CPUs — which is heating up now, as AMD is expected to launch its Zen 6 Venice CPUs this week — the design is vastly different from what we’ve seen out of Intel and AMD. Most notably, Vera is monolithic, placing all of its 88 cores on a single piece of silicon. AMD and Intel, years ago at this point, pivoted away from monolithic dies in favor of chiplets, allowing an extremely high density of cores at the cost of latency and coherency issues. Vera is radically different in that regard, not only being built on a single die, but also dedicating significant die space to the fabric.

“One of the reasons we don’t have 128 cores is because we’ve dedicated so much of the die area toward the fabric,” Buck said. “It’s 3.4 TB/s of bandwidth inside of that CPU that is dedicated toward allowing every core to talk to every cache, every memory [controller] at full speed without any collisions.”

For clarification’s sake, Buck is referencing 3.4 TB/s of core-to-core bandwidth in Vera. There’s up to 1.2 TB/s of aggregate memory bandwidth (14 GB/s per core) through the LPDDR5X interface.

But just as chiplet-based designs made trade-offs in per-thread performance, Vera will likely make trade-offs for its unique architecture. The majority of data center workloads are still “legacy” tasks that hyperscalers have built for, and even with seemingly insatiable demand for AI infrastructure, that is unlikely to change for several years.

Buck recognizes this trade-off, asking: “Can Intel and others build rich fabrics? Do they have the IP and the ecosystem to do it and connect it all the way through to LP memory? They need to tell you when they’re going to do it… but that trade-off will come at the cost of the legacy workload.” Earlier this year, at GTC in March, Buck was even more clear. “The world is not going to be served by one SKU of CPU, and that is not our intention,” the executive said in a news conference at the time.

Still, it’s clear Nvidia has ambitions with data center CPUs beyond what headlines are floating around on the New York Stock Exchange. Nvidia says CPUs represent a $200 billion TAM (Total Addressable Market) opportunity for the company, a rather rosy forecast compared to the rest of the industry, which sees a TAM of around $120 billion by 2030 (though recent estimates have climbed as high as $170 billion). And agentic AI is expanding that market, with Morgan Stanley in April estimating that agents could add as much as $60 billion to the data center CPU market.

Vera is in full production alongside Nvidia’s next-gen AI infrastructure, including Rubin GPUs, ConnectX-9 NICs, SpectrumX Ethernet switches, and the various components that go into building a Vera Rubin NVL72 rack. The company says there are around 1.3 million components that go into a rack, and it has a list of over 300 partners globally to build them. As part of our visit to Nvidia HQ last week, we saw a Vera Rubin NVL72 rack in action, running workloads for OpenAI.

Our local AI testing in 2026 has focused on large language models that can fit entirely into the 128GB of unified memory on Nvidia GB10 and AMD Strix Halo systems. Useful as those smaller open models can be, there is sometimes no replacement for displacement. Today, we’re exploring what’s possible from a local AI cluster with a pair of Nvidia GB10 systems, namely Dell’s Pro Max with GB10 (henceforth Pro Max), which gives us 256GB of RAM for a local AI sandbox.

Quantizing an AI model from higher-precision to lower-precision data types involves tradeoffs for performance and accuracy. And even in quantized form, some advanced open models are still too large to fit within 128GB. But those models can be distributed across multiple local systems using the network as a scale-out backbone, just as they are in the data center.

Why scale out GB10 systems (or Strix Halos, or Macs)? Local token factories with large VRAM pools built up from discrete GPUs can get crazy, fast. Scaling one to even 128GB of VRAM requires a costly host system with enough PCI Express slots and bandwidth to feed those cards, and going beyond 128GB means spending $20K or more in Nvidia GPUs at a minimum, even if you're building up from older 48GB Ada cards.

The preferred recipe for this kind of setup typically includes a Threadripper Pro or Epyc platform, which means a costly CPU, motherboard, and DDR5 kit even before you start adding graphics cards. The power requirements for such a system can quickly get beyond the capabilities of a standard USA 15A circuit (1,800W maximum).

And having four discrete GPUs running their blower fans at high speeds under load, along with whatever other active cooling you might need for what is essentially a GPU server, is not going to make for the most pleasant company if you’re sharing a space with it.

While a GPU server with four RTX Pro 5000 or RTX Pro 6000 cards is useful for getting the absolute best performance for a given application, those potentially high costs, platform challenges, and quality of life concerns have led local AI enthusiasts to explore other ways of achieving large local memory pools with acceptable LLM inference performance, like the GB10 cluster we’re building today.

Nvidia made the DGX Spark and its Spark-alikes scalable, cluster-able systems right out of the box thanks to their built-in ConnectX 7 200Gbps NICs. These high-end interfaces support Remote Direct Memory Access over Converged Ethernet, or RoCE, so two (or more) GB10 boxes can use them as the backbone for a distributed AI computing cluster.

We didn't have multiple Sparks to test RDMA clustering during our initial review, but Dell sent us a pair of Pro Max GB10 systems along with the QSFP cables necessary to join them together.

These systems still aren’t anywhere near cheap, but at $6332 each as of the time of this writing for the tested configuration with 4TB SSDs, you can build a complete, turn-key cluster with 256GB of RAM for less than the cost of the four 48GB or 72GB GPUs you’d need to scale a similar GPU server build.

If you need to save cash and can trade off absolute performance in the bargain, there’s no cheaper way to get into big local models right now, period, but especially not with the level of networking performance that the DGX Spark platform offers.

Dell’s Pro Max with GB10 closely follows the Spark template, but it adds an extremely handy power LED to the front panel that the DGX Spark lacks, and the hexagonal grilles on the front and rear panels doesn't catch on clothes or microfiber cloths like the metal foam front and rear panels of the DGX Spark do.

Dell also provides a large 280W USB-C power adapter with each Pro Max GB10 system, or 40W more capacious than the adapter included with the reference DGX Spark. However, there’s nothing to suggest this system has a higher TDP or clocks than the reference Spark design as a result.

Dell does drop the Pro Max with GB10 back to a PCIe Gen 4 SSD compared to the launch DGX Spark’s Gen 5 drive, but it appears that the ongoing NANDpocalypse has forced Nvidia to source Gen 4 drives for its reference systems to keep costs down, so we’re not holding this decision against Dell here.

Setting up

We’ve already covered the DGX Spark reference design in its own review, so if you’re unfamiliar with the basics of this platform, we’d suggest reading that coverage first. We’ll keep the focus today on the specific challenges and hurdles of clustering two of these systems together.

While the ConnectX 7 NIC on these systems supports both Infiniband and Ethernet protocols in its add-in card form, Nvidia has stated on its official DGX Spark forums that GB10 systems exclusively support Ethernet, and therefore, RoCE for clustering. Don’t buy multiples of these systems hoping to connect them through any Infiniband switches you might have lying around.

The ConnectX 7 NIC on the Spark and Spark-alikes like the Dell Pro Max is also connected to the GB10 SoC in a somewhat weird way due to some possible platform limitations. In short, the largest PCIe bus width one can apparently get off GB10 is a PCIe 5.0 x4 link, so to achieve 200Gbps on any one QSFP port, the two x4 links to the ConnectX 7 have to be teamed behind any one physical port. As a result, each physical port on the NIC is presented to the system as two logical interfaces.

To achieve the full 200Gbps bandwidth available from the ConnectX 7, you have to configure your networking topology carefully. Nvidia has a Spark playbook on how to do this, and the spark-vllm-docker project also offers its own guide on how to set up these interfaces. I’d recommend following them closely unless you have good reason to roll your own configuration.

After connecting my Dell Pro Max boxes together using the same QSFP cages on their back panels, configuring their network interfaces according to the spark-vllm-docker guide above, configuring passwordless SSH on my second node, and running the recommended NCCL bandwidth test on the link, I found that I was only getting a small fraction of the expected RDMA bandwidth, despite both boxes reporting that they were fully up to date through the DGX Dashboard app.

Community wisdom suggested that a firmware version mismatch was to blame, so I verified that the head Pro Max node in my cluster was fully up to date, both through the DGX Dashboard app and through the command line using the apt package manager.

But even though the DGX Dashboard reported that my second Pro Max system was fully up to date, running the recommended command-line apt checks revealed that there was an update for the fwupd package stuck behind a phasing fence, so I force-installed it.

Once this forced update was complete, it unlocked a new round of firmware updates for the second Pro Max, which I dutifully applied. After rebooting both systems and re-running the recommended NCCL bandwidth tests, I was finally getting something approaching the full 25GB/s one would expect from a proper 200Gbps link.

While none of the issues I had getting my Pro Max GB10 systems clustered were show-stopping, it's also far from a plug-and-play experience. But once both systems were settled in, I didn't see the bandwidth over the ConnectX 7 ports drop back to the degraded performance levels I first observed, even across multiple reboots of the cluster.

Cluster management and performance

If you're thinking about clustering Sparks, you want an inference engine that can handle tensor parallelism, or the distribution of model weights across GPUs during computation. vLLM is an easy choice for doing this on the DGX Spark platform thanks to actively maintained community tools like spark-vllm-docker and sparkrun, but you can also achieve these results with SGLang if that’s your platform of choice.

The spark-vllm-docker project comes with several handy scripts that make starting the cluster and distributing models across it easy, and the sparkrun project provides similar functionality. We focused on spark-vllm-docker for this round of tests, but you have options in this space if you want to explore them.

With our inference engine settled, we went off in search of an advanced model that would utilize a decent chunk of the 256GB of VRAM available from our cluster.

DeepSeek v4 Flash is one such model. It’s a 284-billion-parameter mixture of experts model with 18 billion active parameters per token, and it claims to support a context window of up to 1 million tokens. (vLLM gave us a 400K-token cap on this setup). spark-vllm-docker offers a prebaked vLLM recipe for it, so we downloaded it, deployed it across our cluster, and got to benching.

The DeepSeek v4 Flash vLLM recipe we used takes advantage of this model’s built-in multi-token prediction capabilities, so decoding throughput remains essentially the same even as time to first token climbs with context lengths up to 200K+ tokens, or about 333 pages of A4 text. That’s impressive and usable performance for a model of this size and capability.

We also loaded up CyanKiwi’s four-bit quantization of MiniMax M2.7. This is another large mixture-of-experts model with 230 billion total parameters and 10 billion active parameters, and it supports a context window out to 200K tokens, which is exactly what vLLM gave us after initialization on our Spark cluster.

This model doesn’t have the built-in MTP advantage of DeepSeek v4, so even with the four-bit quantization we used for this test, its time-to-first-token and tokens-per-second throughput follow a more familiar curve. Throughput starts in a relatively usable range, but falls off quickly as we approach the limits of the context window.

Our experience running DeepSeek v4 Flash and MiniMax 2.7 shows that even though a Spark cluster isn’t fast, it can still produce enough tokens per second to be a useful sandbox with these demanding models.

Power and thermal notes

As we discussed in our intro, a major advantage of a cluster like this is that it doesn’t require exotic power and cooling to run, and you also don’t have to banish it to a garage or server closet to keep it quiet.

Imeasured peak wall power draw of about 375W to 415W across my cluster during inference performance testing, which is just a bit higher than the TGP of a single RTX 5080 without its host system.

That figure bodes well for adding even more Spark-alikes to a local cluster if you need to, as even four of them running all-out are likely to need less than 1kW from a circuit (before any outboard networking gear is factored in, at least).

Noise levels from my dual Dell Pro Max setup under load were also well controlled, measuring about 40 dBA at 18 inches away. If you need to keep these systems in an inhabited office space or cubicle, they’ll be perfectly tolerable to be around.

If you’re expanding beyond two GB10 systems, I’d guess that any 200G/400G networking gear that you’d need to throw into the mix will likely be far louder than even four of these systems under load, as it’s likely built for a server closet, not a continuously inhabited space.

Bottom line

If you're a local LLM trailblazer and need more VRAM for large, capable models, and don't want to fiddle with or don’t have the cash for a from-scratch GPU server build with more than 128GB of memory, the Dell Pro Max with GB10 cluster we’ve built here exemplifies how clustering Nvidia GB10 systems is a straightforward, space-efficient, low-power, low-noise, and relatively cost-effective way to scale up your local AI sandbox beyond 128GB of VRAM.

"Relatively" is doing a lot of work here because a pair of Dell Pro Max with GB10 boxes as tested here rings in at $12,664 right now, plus another $50 for the QSFP cable you'll need to hook them together. For organizations or institutions with departmental budgets to spend and existing Dell accounts and support contracts to work within, that dollar figure is likely secondary to the ROI on whatever proposal might drive a purchase order.

But for individuals who just want to build a bigger AI sandbox in their home lab and don't have those relationships to worry about, it's still possible to construct a similar cluster with Asus's Ascent GX10 from stock for under $10K, even at current prices. And as we explained in the intro, going above 128GB of local memory by using multiple discrete GPUs will cost you far more than such a cluster, even before you factor in the cost of a host system.

Not everybody needs to connect multiple Sparks, of course, but if that possibility does intrigue you, the ConnectX 7 NIC in every GB10 box means that there isn't a cheaper way to achieve a 256GB (or larger) distributed memory pool with this class of networking performance behind it.

Some AMD Strix Halo mini-PCs offer PCIe slots for expansion, but they're limited to PCIe 4.0 x4 speeds, so even the funky teamed PCIe 5.0 x4 links to the ConnectX 7 NIC inside GB10 boxes means you're getting far higher potential RDMA bandwidth than you would from adding an aftermarket NIC to a Strix Halo system.

Even though Apple's Mac Studio briefly enjoyed a turn in the spotlight as a cluster-friendly alternative for local AI thanks to the massive memory pools and high bandwidth available from Apple Silicon, along with RDMA over Thunderbolt 5, that star has dimmed, as the company no longer offers memory options larger than 64GB with M4 Max Studios or 96GB with M3 Ultra models. And the lead times on either of those systems are currently over three months out, which is an eternity in the rapidly evolving local AI market.

So Nvidia sort of has this field to itself right now, as GB10 boxes remain readily available from stock with 128GB of RAM at prices that aren't completely bonkers. And if you're a novice to distributed computing concepts, the active community, actively developed tools, and ecosystem software support around GB10 systems are all invaluable for getting your AI cluster running quickly. All that makes Dell’s Pro Max with GB10 (and other Spark-alikes) hard to beat for building a big local AI sandbox to experiment with.

TSMC intends to raise base quotes on advanced chip production services by up to 10%, according to Nikkei, which cites people with knowledge of the matter. The price hike reflects increased demand for sophisticated processors by the AI sector, raising costs of tools and materials, as well as amplified investments in new production capacities.

For advanced process technologies — which TSMC considers 7nm-class and below — TSMC plans to raise baseline prices by 5% to 10%, depending on the particular production node and customer, the report claims. Furthermore, customers that need additional HPC chip capacity beyond their original volume requirements will reportedly have to pay another 10% to 15% premium on top of the standard increase, which means that some services will get a price hike of around 25%, if the report is accurate.

TSMC also intends to increase prices for mature manufacturing technologies, including its 12nm, 16nm, and 28nm-class nodes as well as other legacy fabrication technologies, the report claims. Increases could reach 10%, although certain nodes will reportedly see smaller adjustments, according to Nikkei.

Advanced technologies generated around 77% of the foundry's revenue in Q2 2026, whereas mature nodes accounted for 23%, which essentially means that TSMC is hiking prices on all of its services.

The company reportedly began discussing the new pricing with customers around June and completed negotiations in July. Rather than introducing higher rates immediately, TSMC opted to implement them from the beginning of 2027 to give clients like Apple, AMD, Nvidia, and MediaTek additional time to accommodate the changes and adjust their prices accordingly.

Since TSMC produces the lion's share of advanced processors for AI, HPC, networking, and smartphone applications, its price hikes will inevitably create a ripple effect in the industry and will make almost all electronics more expensive.

TSMC is not alone in raising prices these days. Vanguard International Semiconductor has also raised prices, while UMC began implementing increases in July. Also, memory makers have increased prices significantly, making TSMC management jealous. Intel also recently increased prices of its client and data center CPUs, citing market demand.

"I am really jealous about memory companies' 86% gross margin," said C.C. Wei, chief executive of TSMC, during the company's earnings call with financial analysts and investors. "86% [margin at memory makers] – 68% [margin at TSMC], I will be happy about that."

TSMC rarely comments on its prices to a large degree because they vary based on volumes and relationship with a particular client. Nonetheless, the head of the company stressed that the company has no intentions to increase prices suddenly or dramatically.

"So we do not suddenly increase our price by which I like to have 4x or 5x," Wei said. "You cannot survive for that kind of... for your customer to survive for that kind of price increase. So we earn our value, and we make sure that our profit, our gross margin, is enough for our long-term sustaining expansion, that is to the benefit of my customers and TSMC also, that is our philosophy."

A PC gamer has DIYed a passive Nvidia GeForce RTX 4060 graphics card system. Perhaps unhappy with the Palit GeForce RTX 3050 KalmX 6GB still being the pinnacle of commercial passive graphics cards in 2026, Bilibili user NexFrame (h/t Fanless Tech) has bolted a hulking finned aluminum heatsink onto an RTX 4060.

NexFrame appears to be a small or up-and-coming ‘brand’ with a penchant for passive PC systems, from what we can understand from their Bilibili bio (machine translation). Unfortunately, we don’t have a lot of information about this passive 5.5-pound (2.5kg) aluminum heatsink-wearing RTX 4060, like whether it is tuned to run cooler than a standard model for fanless operation.

Squinting at the Bilibili video source, a system monitor window seen towards the end of the video appears to show that the GPU is running in a gaming scenario at 58C, with a 71C hotspot. Meanwhile, the graphics fan is running at 0 RPM, which seems accurate. However, the modder doesn’t seem to be taking it easy on the GPU. Further down the system info screen, we see the GPU reportedly pulling 198W. A standard actively cooled RTX 4060 would consume far less than that under load, more like 115W to 120W, so some data must be mangled here, or being misreported.

Elsewhere in the images shared by NexFrame, we can see that the CPU is also being cooled passively. It looks like a hexacore Intel CPU has been combined with a Noctua NH-P1 Passive CPU cooler. This commercial passive cooler was capable of keeping a CPU consuming up to 75W cool and stable enough over extended periods during our review testing. The system monitor tool overlaid on NexFrame’s game testing session shows the CPU sipping between 35 and 50W.

Passively cooled PCs are of interest to a significant number of enthusiasts for eliminating what is typically the noisiest component of a modern PC – fans. In a standard gaming PC, there will be fans built into the CPU cooler, on the GPU shroud, in the PSU, and also arranged at strategic places around the case. Even so-called liquid cooling systems usually rely on their CPU or GPU contact heatsinks being attached to an array of fans cooling a radiator in the case. Just think how blissfully peaceful your computing experience could be if all these moving parts were eliminated.

We live in an age where artificial intelligence increasingly dominates the internet, making it harder to distinguish real content from fake news. Any picture or video you see today could be AI-generated and the traditional markers that would give it away are fading rapidly. There are tools that help identify if something has been made with AI, and Nvidia — arguably the main beneficiary of the AI race — has just released its own, called the "Synthetic Video Detector" (SVD).

SVD is an Nvidia Inference Microservice (NIM) part of the company's AI for Media Private Access Program, so it's not publicly available to consumers, but a demo exists. Anyhow, SVD's job is simple: detect whether a video is real or if was generated using AI. It can analyze videos at scale, breaking them down frame-by-frame to spot anomalies. It's based on cutting-edge research that won awards at computer vision conference ICCV.

Instead of looking at the video file as a whole, SVD splits it into cropped frames, each carrying a 504x504 resolution. These frames are then passed through two powerful Vision Transformers made by Meta: DINOv2 and DINOv3. A job of a vision transformer is to learn to form patterns without needing human-labeled data. They're commonly used for image classification, image retrieval, object detection, and depth estimation.

As such, once the frames go through these transformers, their distinct spatial features are quickly assessed, and each one is assigned a score between 0 and 1 — 0 representing a fully real image and 1 representing a completely fake image. The scores are tallied at the end to form an average, which tells the user whether the video is real or not based on a percentage score out of 100.

This way, news agencies, broadcasters, and media outlets can authenticate footage they receive much quicker and with better certainty. SVD is even designed to work with the reality of social media compression since videos uploaded online will have their imperfections masked. But the transformers can still detect patterns that the human eye cannot, seeing past surface-level anomalies to instead focus on intrinsic artifacts.

As visible in AI GVD bench above, uncompressed video still delivers the best results with SVD showing an insane 92% accuracy rate. At 15% compression, the model drops down to 87% accuracy, while a 50% compression rate still achieves a very impressive 82% accuracy in detecting AI-generated content. Since this is a microservice, it has exceptional latency as well, processing 1080p video in just 22ms on Nvidia RTX GPUs and 30ms on Nvidia's workstation models.

That being said, SVD requires the NVENC encoder, so datacenter cards like the B100 cannot run it natively. Nvidia said it's already working with Wowza to bring real-time synthetic video detection into livestreaming workflows. A demo version is available to try right now at build.nvidia.com but beware that it takes a long time to process since it happens in the cloud, the max file size limit is only 100MB, and it often just times out.

TrashBench recently decided to test whether adding more and more fans to what used to be one of the best graphics cards would improve its performance. The result wasn’t significantly faster performance, sadly, even when the thermal headroom was used for overclocking (vs. stock OC). Nevertheless, lessons were learned, and the self-described “punk-rock GPU death lab” was still proud of the temperature reductions, plus the GPU contraption's “awesome” looks and sounds.

The experiment began with an overview of the Asus ROG GeForce RTX 3080, a nice example of the breed. But it was a choice that would perhaps end up making the 11-fan wonder look like less of an accomplishment. TrashBench stated the goal was to add more and more fans, plus duct tape and cable ties, then see whether the reduced temperatures from the boosted airflow result in more frames.

After cleaning and repasting the guinea pig GPU, a baseline was set with the stock cooler. Running 100% fan speed on the Asus ROG resulted in a stable temperature of 63°C (down from 70°C) during stress testing with the Unigine Heaven benchmark.

Replacing the Asus ROG cooling shroud with a trio of Arctic case fans dropped the reported GPU temperatures to a stable 52 degrees Celsius. That’s a decent result. Next, the trio of case fans was swapped for thicker server fans, shaving another 2 degrees Celsius off the GPU temperature, bringing it to 50 degrees Celsius precisely. Duct tape was added to prevent air venting from the sides of the server fans. Oops, the GPU temperature actually stabilized at a warmer 54 degrees Celsius.

So, that was the end of fans-at-the-front modifications. TrashBench next looked at adding a quintet of tiny Arctic server fans that run at up to 15,000 RPM along the top of the card. This jet-engine-soundalike configuration didn’t shift the needle, though. The RTX 3080 still wouldn’t hold below 50 degrees Celsius when tested for any length of time.

Trying backplate fans was the next idea. After another ineffective endeavor, though, TrashBench decided to upgrade the backplate fan to an AiO 360mm cooler. Wow - a new best was recorded with this setup, with the GPU reporting a top stable temperature of just 41 degrees Celsius in Heaven.

Momentarily happy with this low-temperature achievement, the tech tinkerer decided to check whether benchmark runs in Shadow of the Tomb Raider showed any benefit. There were some performance uplifts charted, but only very modest, as you can see from our results table, which even includes cases where the newfound overclocking headroom was taken advantage of.

TrashBench concluded with some positives. “It nearly cut the temperatures in half. It looks awesome. It sounds awesome,” underlined our hardware hacking hero. However, the tech tinkerer kept it real by adding “And it got me 2 FPS. So, not worth it.” In some ways, then, the good quality of the stock triple-fan Asus ROG RTX 3080 graphics card detracted from the 11 extra-fan hijinks.

The upcoming Super refresh of the Nvidia RTX 50-series GPU is reportedly on hold due to the high cost of 3GB GDDR7 memory chips. A VideoCardz source confirmed that one board partner already has RTX 50 Super GPUs on hand, but Nvidia has allegedly told the company that the products are on hold because of the price of 3GB GDDR7 memory chips.

This means that the AI GPU giant has already set an internal release date but is reportedly pushing it back because of memory pricing. If the cost of GDDR7 chips becomes too high, then the RTX 50 Super GPUs would either have a selling price that’s way above Nvidia’s targeted MSRP or, if it forces its partners to stick with or remain close to its set prices, GPU board manufacturers wouldn’t just make any units at all, as they’re going to lose money with every sale.

The RTX 50 Super GPUs are rumored to have 3GB GDDR7 chips, which offers 50% more capacity than the 2GB found in current-gen RTX 50-series graphics cards. This would allow the upcoming GPUs to have more memory without needing to increase or change their memory bus configurations.

According to the publication, the cards expected to be released soon include the RTX 5080 Super, RTX 5070 Ti Super, RTX 5070 Super, and RTX 5050 9GB. The first two will each receive 24GB of GDDR7 VRAM with a 256-bit bus width, while the RTX 5070 Super will have 18GB of VRAM with a 192-bit bus width. Unfortunately, these chips cost twice or thrice as much as their 2GB variants, which will likely push the retail price of these cards beyond Nvidia’s envisioned MSRP.

Nvidia used to supply VRAM chips alongside GPU dies to its board partners, but it changed this policy in late 2025 as the memory chip crisis unfolded. Because of this, the companies that complete the final assembly of the graphics cards are forced to source their own memory chips in an increasingly competitive market. SK hynix, one of the big three memory chip manufacturers, even says that 2027 is set to be the “worst year” for the memory shortage and said that the crunch will last until 2030.

Even Nvidia, one of the biggest winners in the AI race, has been affected by the RAMpocalypse, with the company not announcing a new GPU at CES 2026. This is the first time this has happened in five years, with Jensen Huang releasing the 30-series, 40-series, and their respective mid-generation refreshes despite supply chain limitations and several other issues that arose during that period. Its latest AI systems are now more expensive than ever, with memory accounting for 25% of the BOM, as costs have soared by nearly 500%.

It’s still unclear what Nvidia and its board partners plan to do about the memory situation, especially as things don't seem to be improving. While it could delay the launch of the RTX 50 Super, it can only do so for so long, especially if it’s true that its dies are already in the hands of its board partners.

‘The Jensen Jacket: Jensen Huang's Tom Ford Leather Jacket’ achieved a hammer price of $960,000 this weekend. High-end auctioneer Sotheby’s listed the leather garment, which was claimed to have been worn at least once by the Nvidia CEO, with a far lower price estimate of $40,000 to $60,000. Happily, the bountiful proceeds of the auction are going to charity.

Bidders could be quite confident that this Tom Ford jacket was genuinely worn by Jensen Huang at one or more landmark product launches, thanks to the work of the PSA [Professional Sports Authenticator]. Specifically, PSA photomatched this jacket and its unique leather wrinkles to the Hon Hai (Foxconn) Tech Day in Taipei on October 18, 2023, where Huang wore it on stage and met with other execs. Various close-up photos in the sales catalog showed telltale signs that this was/is the real deal. Separately, a signature on the garment was authenticated by James Spence Authentication.

The near $1M hammer price achieved is many multiples of the estimate. In our earlier reporting on the sale, we guessed this would happen for a number of reasons. Firstly, we thought Sotheby’s ‘low’ estimate was intentional to draw in the crowds and stoke excitement. Secondly, we mustn’t neglect the importance of the not-so-secret ingredient - Jensanity. And, right now, the AI boom with Nvidia at its center is still growing apace.

You can buy a brand new Tom Ford SS2023 menswear collection jacket, like the one shown, without any infusion of genuine Jensanity, for around $9,000. However, we can’t begrudge the success of this auction as the proceeds are earmarked for charity. The Sotheby’s page says that the auction was organized by Long Journey Ventures to benefit the Edge Institute, a non-profit that convenes people working at the frontiers of tech, science, culture, and society in pop-up villages (Edge Cities) to live together and experiment towards a brighter future. Fellowships, grants, and residencies for the next generation of young builders will be funded by this bumper lump of cash.

Nvidia today announced that it's working with Japan's Noetra Corp. to build a 140-megawatt AI factory packing 27,500 Rubin GPUs and 13,750 Vera CPUs, the compute foundation for FRONTia, the Japanese government's state-funded physical AI program. The facility will be built from Vera Rubin NVL72 racks on Nvidia's DSX reference platform, connected with Spectrum-X Ethernet, and will train open multimodal foundation models for robotics, digital twins, and industrial automation, with pretrained weights shared broadly with domestic developers.

"Japan invented modern manufacturing. Now, it is building the AI factories that will power the next industrial revolution," said Jensen Huang, founder and CEO of Nvidia, in the announcement.

The chip counts divide exactly into 382 Vera Rubin NVL72 racks, each housing 72 Rubin GPUs and 36 Vera CPUs. Neither company disclosed the project's cost, but VR200 NVL72 systems are currently quoted at $5 million to $7 million apiece, which puts the rack hardware alone somewhere between $1.9 billion and $2.7 billion. Morgan Stanley estimates Nvidia will charge $55,000 per Rubin GPU in volume, pricing the GPU silicon at roughly $1.5 billion before memory, networking, and cooling.

No deployment timeline was given in the announcement, but Rubin racks are only expected to reach volume production in the second half of this year, and Nvidia said the facility will support trillion-parameter model training "as the AI factory expands," suggesting a phased ramp.

Noetra is a new consortium founded by SoftBank Corp., Sony, NEC, and Honda, with investment from 44 companies and organizations, NEC said in a press release also published today. Noetra and the national research institute AIST won a NEDO public tender on June 30 to run the FRONTia project from fiscal 2026 through fiscal 2030, with ¥387.3 billion (roughly $2.4 billion) in first-year funding and up to ¥1 trillion (roughly $6.1 billion) over five years, Asia Times reported. Funding beyond the first two years is subject to annual stage-gate reviews, so the full amount isn't guaranteed.

Noetra's roadmap targets a reasoning foundation model in fiscal 2026, an omni-modal model that processes text, images, video, and audio by fiscal 2028, and "real-world native AI" capable of spatial awareness by fiscal 2030, per NEC.

The AI factory follows SoftBank's Blackwell-based DGX supercomputer, announced in 2024, and FugakuNEXT, the $740 million RIKEN, Fujitsu, and Nvidia zetta-scale system due around 2030, but it's the first that's state-tendered national infrastructure rather than a corporate or scientific machine. Japan's AI Robotics Strategy, released in March, targets more than 30% of the global AI robotics market by 2040, an opportunity the government estimates at $133 billion.

Jensen Huang, chief executive of Nvidia, denied reports about delays of the company's next-generation AI platform and said that production volumes of the upcoming Vera Rubin platforms are 'giant.' He didn't address reports about delays of Vera Rubin Ultra-based rack-scale systems carrying 144 AI GPUs.

"[The reports about Vera Rubin delays are] not true," Huang told reporters on the sidelines of an event in Japan, reports Bloomberg. "Vera Rubin is already in production. Giant amounts of production incoming."

Nvidia confirmed production of its Vera Rubin platform in January and then sampling in February, so the current comment reiterates what we already know. Nvidia stressing that 'giant amounts of production' are incoming is meant to reassure investors that the company is on track to sell a boatload of its next-generation Vera CPUs, Rubin GPUs, and Vera Rubin NVL72 systems in the coming quarters, which means more record-setting quarters.

What Huang did not address — or perhaps he wasn't asked — is Nvidia's rumored delay of its Kyber NVL144 rack-scale solution with copper interconnects due to the system's complex PCB midplane by more than a year from 2027 to 2028. An alternative dual-rack design has reportedly been canceled and an even larger CPO-based NVL576 configuration may also face delays or limited availability, the same report from SemiAnalysis claimed earlier this month. The setback could leave Nvidia's Rubin Ultra platform with a smaller NVLink scale-up domain than originally envisioned. Nvidia says its roadmap is intact.

The Kyber NVL144 architecture was designed to connect 144 Rubin Ultra GPUs using a copper-based NVLink 7 scale-up fabric, so the machine required a sophisticated PCB midplane to carry high-speed electrical links between the system's components. SemiAnalysis claims that this midplane was challenging to manufacture, leading to a delay. The report does not identify defective chips or problems with particular components mounted on the board, but specifically points to the manufacturability of the PCB infrastructure itself.

"Our roadmap is intact," a spokesperson for Nvidia told Tom's Hardware.

Nvidia's statement on the matter neither confirms nor denies the report, but indicates that the company will be able to offer products mentioned in its roadmap without revealing whether they also remain on their previously announced launch schedules.

Nvidia reportedly considered another copper-based design, called NVL72x2, as an alternative to Kyber. The system would have placed two Oberon racks back-to-back to expand the size of the NVLink scale-up domain without using optical interconnects. However, SemiAnalysis says customers rejected the unusual design and operational requirements, but does not specify their individual objections that could include serviceability, cooling, cabling, and data-center layout.

Meanwhile, the planned NVL576 rack scale solution that was supposed to combine eight Oberon racks interconnected using co-packaged optics between NVSwitches has also been postponed, or shipped in relatively small quantities because of 'ongoing CPO challenges,' SemiAnalysis claims.

The existence of the planned NVL576 configuration suggests that Nvidia had been developing some form of CPO-enabled NVSwitch connectivity for the Rubin generation. In theory, similar optical switch-to-switch connectivity could potentially be used to join smaller GPU groups into an NVL144 system and bypass Kyber's problematic copper midplane. However, the available information does not clearly indicate whether the CPO technology intended for NVL576 could reproduce Kyber's topology, bandwidth, and latency characteristics, or whether it was sufficiently mature for high-volume deployments by potential NVL144 customers.

The reported Kyber delay comes on the heels of another report saying that Nvidia had canceled quad-compute-chiplet version of its Rubin Ultra in favor or a dual-compute-chiplet design that is projected to deliver 2X lower performance. With Kyber NVL144 delayed and NVL72x2 cancelled, Nvidia will only be able to offer 72-way scale-up systems till sometimes in 2028, meaning that AMD and Google may end up with more competitive scale-up systems in 2027 – 2028. AMD's Mega Pod based on the Verano CPUs and Instinct MI500-series accelerators, is expected to pack up to 256 accelerators. Google's TPU 8i can provide roughly 1,024–1,152 accelerators within one low-latency domain, whereas the TPU 8t goes much further and can get to 9,600 chip packages per domain.

Nvidia's RTX Spark platform arrives later this year, and the company is hard at work building the partner ecosystem around the GB10 Superchip to ensure that Windows and applications are ready for its agentic AI PC vision. As part of that groundwork, the two companies announced today that Sega will support the RTX Spark platform with its upcoming Virtua Fighter Crossroads, coming in 2027.

The two companies also committed to RTX Spark support for "future Sega titles,” meaning that we might see official support for other evergreen franchises like the Yakuza series, the Persona games, and the upcoming Alien: Isolation 2 and Total War: Warhammer.

Although the companies didn’t go into detail about exactly what full support for the RTX Spark means for Sega games, one would expect that the developer’s titles will be natively compiled for Windows on Arm instead of relying on the Prism x86 emulator for compatibility.

It also seems safe to expect that future Sega titles will incorporate DLSS technologies like upscaling and Multi Frame Generation in order to deliver the best possible experience on RTX Spark systems. Despite having GPU compute capabilities similar to those of a desktop RTX 5070 on paper, the unified memory architecture and relatively limited memory bandwidth of the GB10 Superchip behind the RTX Spark platform present challenges for gaming performance that are likely to make the incorporation of DLSS tech important for the best experience.

The relationship between Nvidia and Sega spans over 30 years, tracing its roots to the ultimately abandoned development of the GPU for the Dreamcast console. Despite its eventual decision to use an NEC-produced PowerVR GPU for that system, Sega offered Nvidia a $5 million lifeline that gave the company the runway that it needed to develop and deliver the Riva 128, its first DirectX-compatible GPU.

That investment proved to be historic, as Nvidia now has a market cap of over $5 trillion and is in the process of shifting the very foundations of computing through its Grace Blackwell and upcoming Vera Rubin AI platforms for the data center.

Whether the RTX Spark platform reshapes the PC when it arrives in the fall of this year remains to be seen. But if you’re a fan of Sega’s IP, this partnership means that you can at least look forward to a first-class experience with its games on RTX Spark systems.

The Sino-American chip wars have resulted in many back-and-forth salvos and negotiations as the countries try and strike a balance between technology access and trade. Currently, both sides have set respective import and export controls, letting specific companies on a case-by-case basis. Today, Reuters reports that Chinese telecoms giant ZTE and server firm Maginfra have received U.S. approval to buy Nvidia's last-gen H200 "Hopper" chips.

ZTE joins a club that counts Alibaba, Tencent, ByteDance, and JD.com among the roughly 10-strong group of Chinese companies with U.S. clearance for those purchases. Additionally, an apparent subsidiary of Kingsoft Cloud got approval to buy AMD accelerators equivalent to Nvidia's H200, presumably Instinct MI300X-class chips.

Over on the Chinese side of the table, Reuters remarks that there's no word on whether the respective authorities will give ZTE the go-ahead for import, as the country has taken on a protectionist stance as it tries to grow its own chip industry. The country has discouraged firms from purchasing foreign tech and has instead pushed companies to acquire homegrown accelerators. Huawei in particular has made great strides both technologically and financially.

But even with those domestic production initiatives, the Chinese hunger for AI silicon is so deep that six months ago, Reuters said the nation's tech firms had more than two million H200 chips on order, far more than what Nvidia had on hand at the time. We'd venture that hunger has barely subsided.

ZTE might not be a familiar name Stateside, but the corporation is one of China's largest telecommunication conglomerates, and among many other ventures, it sells all sorts of carrier network gear that's installed worldwide, along with corresponding client-facing equipment, including phones and IoT equipment. Like most any sizable technological venture, ZTE has joined in on the cloud computing and AI push, so it needs accelerators to make those ambitions reality.

The current status of the AI chip trade situation is roughly that the U.S. allows Chinese firms to buy AI chips up to and including the Hopper family (meaning no Blackwell chips), with a 25% export tariff, though final decisions are made on a case-by-case basis. Over on Chinese shores, Beijing's authorities play their cards close to their chest and dole out approvals as they see fit, with no clear rules seemingly set. But China is, of course, a global power with trade connections to most everyone, so interested firms were able to get their hands on Blackwell chips through various creative (and potentially illicit) means.

Whether this change will actually clear the way for any great volumes of H200 accelerators to make their way into ZTE's data centers remains to be seen. CNBC cites a U.S. trade official who today stated that "very few shipments against licenses for H200s and equivalents have taken place. It’s a very small quantity of chips" during a congressional hearing. If H200 shipments become material to Nvidia's bottom line, we'll almost certainly hear about it in future comments or earnings reports.

AI tech giant Nvidia, which builds some of the most coveted AI chips in the world, has reportedly created a new “whitelist” of verified companies to help prevent its products from getting smuggled into China. According to the Financial Times, this roster cuts the number of authorized clients by more than half, with those remaining having passed tougher compliance inspections to ensure that they are genuine businesses, not shell companies designed to forward Nvidia GPUs and servers into China. Some of the steps that Nvidia took to help safeguard its chips reportedly included sending staff to customer data centers, contract verification, and interviewing end users.

Sources told the publication that the company made this move after Washington pressured it into tightening its legal compliance, which comes months after the arrest of Supermicro co-founder Yih-Shyan “Wally” Liaw, alongside two other suspects, for allegedly smuggling $2.5 billion worth of Nvidia hardware into China. This clampdown also extended into Singapore, which saw the seizure of a $42-million mansion tied to alleged AI GPU smugglers, and Taiwan, where authorities raided the offices of Supermicro and two supply-chain partners as part of a chip smuggling probe. Nvidia was not immediately available for comment on the news.

Although the U.S. has banned the latest AI GPUs for export into China since 2022, various investigations showed Chinese companies could still easily get their hands on these coveted chips until recently. Washington’s and its allies’ crackdown on AI GPU smuggling have cut supply in China, which is now making it harder for AI companies to procure the processors they need. President Donald Trump took a 180-degree turn in December 2025 and finally allowed Nvidia to export its H200 GPUs to select customers in the region, which would have alleviated the situation. However, Beijing refused to allow Chinese companies to buy these AI processors — instead, it’s banking on domestic semiconductor manufacturers to make up for the shortfall, but it’s apparently still not enough. One tech executive even told the Financial Times that all domestic suppliers are sold out and that they’re even considering less powerful chips, as long as they could be put to use.

As Nvidia reportedly cleaned up its verified list of clients and made it harder for non-vetted companies to acquire its chips, the company has also told its partners to fix their export control compliance. “We insist our partners are compliant,” Nvidia CEO Jensen Huang told the media last May after Taiwan started its operations against AI chip smuggling into China. “We hope that they will enhance and improve their regulation compliance and prevent that from happening in the future.”

When the RTX 50 series launched, reviewers quickly discovered that the hotspot temperature was being misreported in standard diagnostics tools such as HWiNFO or MSI Afterburner. Eventually, people realized that Nvidia had outright removed the option to monitor hotspot temps, but it seems like the hardware was never removed from the GPU. New testing by Brazilian repair specialist Paulo Gomes has revealed that the sensor is still present and readable with special tools.

In the video, the host shows a Gigabyte variant of the RTX 5070 Ti that was sent to him due to overheating issues. Within Windows, the monitoring tools showed no abnormal signs, as the "average" temperature was reported at 67 to 68 degrees Celsius. However, when diagnosed with a specialized tool called "MODS," the hotspot temperature reached 107 degrees Celsius almost immediately under load.

MODS stands for Modular Diagnostics Software, and it's an internal Nvidia tool used to test GPUs before they hit the shelves or during the RMA process. It's not available to the public and doesn't work on Windows because the OS keeps intercepting calls from the hardware monitoring APIs. You need a Linux distribution that boots directly into a command line, from where MODS (and MATS, for memory testing) can run as intended.

Some repair shops have been known to get access to MODS, such as in this case, which unlocks the hidden hotspot temperature sensor on Blackwell gaming GPUs. Keep in mind that Nvidia ships much more comprehensive diagnostic utilities for its server-grade and workstation GPUs that can actively monitor all aspects of the card. It's unknown why the company decided to keep some sensors locked out of gamers' reach.

Perhaps we can infer the rationale from last year, when Igor's Lab tested several RTX 50-series GPUs and found a "hotspot issue" affecting all of them. The reason was poor PCB manufacturing — not using heavy-duty materials to build the PCB layers, causing certain parts of the substrate to heat up even when the core was relatively cool. This was exacerbated by Nvidia's own guidelines, which told AIBs to compensate for ideal conditions instead of worst-case scenarios.

Anyhow, as Paulo Gomes and his team discovered, the RTX 5070 Ti's hotspot was hitting 107 degrees Celsius, and the card throttled and dropped its clock speeds right away. Nvidia mandates 107 degrees Celsius as the upper limit for RTX 50-series, so it was clear that the card was slowing down to prevent damage. To inspect what was actually wrong, they opened up the card and found poor thermal contact between the cooler and the componentry.

The TIM (thermal interface material) application was inadequate; the paste had accumulated around the perimeter of the core while the center was mostly dry. The repair personnel removed the old material and replaced it with SnowDog Husky paste, which was enough to drop the hotspot temperatures to 100 degrees Celsius. Now, it was within the safe operating range and no longer thermal throttling under load.

What would've been a simple fix on the consumer's end was turned into a repair job solely because Nvidia hid the GPU's hotspot temperature, literally misreporting the card's internal condition. Had this RTX 5070 Ti just run at 107 degrees Celsius continuously, the silicon would wear down incredibly fast, and the customer would never even know why. Not to mention some manufacturers' insistence on voiding warranty upon breaking the GPU's "seal," which is an illegal and unenforceable practice in the United States.

Nvidia and Sega have scheduled an event next week to celebrate their history and longstanding friendship. The invitation-only shindig takes place at GiGO Akihabara, Tokyo (you can apply via Twitter/X). Nvidia CEO Jensen Huang will star at the July 15 event, officially unveiling the RTX Spark for the first time in Japan. Attendees will also get a chance to win a GeForce RTX 5090 FE in a raffle.

If you will be in Tokyo on July 15, it might be worth pitching for an invite, and if you’re exceptionally lucky, you might visit the event, then go home with one of the best graphics cards available in 2026. The GeForce Japan social media managers are asking for comments that encapsulate 'memories of Nvidia or Sega' with photos, videos, anecdotes,” and so on (machine translation). You have until sometime on July 12 to concoct your invitation pitch. Remember, Japan time is about half a day ahead of the mainland US time zones.

Though it is clearly spelled out what the Nvidia side of the celebration will present on the day (the RTX Spark and a raffle RTX 5090 FE), no such specific teases have come from the Sega camp.

The lack of any teaser might make you think that Sega isn’t going to reveal anything new at the event, or conversely that something big is on the horizon. But if Sega were to pull a hardware surprise out of the bag, it could make quite a splash.

The Japanese gaming icon exited the console race back in 2001, when it ceased production of the Dreamcast. However, it released rehashed mini consoles like the Genesis Mini and Game Gear Micro at the beginning of the 2020s. More recently, some Mini Arcades (like Sonic, OutRun, and Golden Axe) have been released in partnership with MyArcade. It would be great if Sega could do something ambitious again, or even come out with a mini console capable of handling Saturn or Dreamcast titles. With some kind of lightgun support, please.

Nvidia and Sega – an enduring bond

As mentioned in the intro, Nvidia and Sega are old buddies. Nvidia nearly collapsed in 1996, just three years after its founding, and only the belief and generosity of a senior Sega executive at the time saved Nvidia from the graveyard. This is according to Huang’s recollections of a very difficult time for Nvidia, shared in interviews in 2024.

The story goes that Nvidia’s work to design a GPU for a next-gen Sega console fell through largely due to incompatibility with the emerging DirectX API. Sega’s management appreciated the efforts, though, and believed in young Mr. Huang enough to invest $5M in the green team. This investment gave Nvidia the breathing room to pivot from its previous graphics architecture and come out with the DirectX-friendly RIVA line (1997), followed by the unstoppable GeForce series (1999).

Only a little while back, Phoronix got the chance to test-drive one of Nvidia's upcoming Arm-based Vera CPUs. In certain approved workloads, the chip put up an impressive showing, nipping at the heels of its Xeon and Epyc x86 competitors. In specific single-threaded scenarios, Vera "absolutely dusted the competition" (our words). But AMD had some things to say about the Phoronix test, firing back with its own metrics of a 3.3x performance gain over Vera for the projected output of a 100 kW rack of its hardware.

And Nvidia is already thinking about this future. It revealed that its next-gen Rigel Arm v9.2 CPU core, shipping as part of its Rosa CPU, will deliver even higher per-core performance than Vera's Olympus core within the same silicon footprint via "better instruction delivery," more L2 cache, and better memory handling.

Now, Nvidia is reasserting Vera's advantage for AI work by describing it with a new product category: a "max single-threaded CPU at scale" rather than a parallel-processing beast. Instead of simply maximizing the core count per socket, Nvidia says Vera's monolithic 88-core design is meant to provide strong performance per core under load, enough memory bandwidth per core to keep active cores supplied with data, and predictable latency.

Nvidia describes AI inference workloads as being bound by single-thread speed. For example, a reasoning AI will run the model for one step, and will run the model again as many times as it takes until the answer is generated. Since each step needs the output from the previous one, no amount of parallelism will help — the speed at which one thread can run is most important. The situation is similar in agentic workloads, as agent B can't get its work started without knowing what happened with agent A.

Vera's design, then, appears to be one aimed at both having and eating the proverbial cake: high single-thread speed with a large number of available threads. Vera is an 88-core design with SMT support for 176 total threads. And to supply each of those cores with adequate bandwidth, Nvidia says Vera talks to LPDDR5X RAM at 1.2 TB/s, and that its monolithic compute die keeps cores well fed and avoids bottlenecks thanks to 3.4 TB/s of core-to-core bandwidth. The company says the latter figure is 3x that of "any other data center CPU."

There are many ways to measure inter-core bandwidth, so direct comparisons are tricky at best, but given the bespoke design of Vera for AI inference tasks, the claim is at least plausible.

The company's latest blog post about the new silicon reiterates this point, claiming its new silicon delivers 1.8x higher performance versus its x86 competition in "loaded CPU workloads that represent agentic execution," 1.5x higher perf in coding workflows, and 3x faster work in database analytics.

The numbers Nvidia touts purportedly come from real-world scenarios, starting with those from Perplexity, whose usage of Vera in coding agent work delivered a claimed 1.5x performance increase over x86, and a 1.9x speedup running concurrent sandboxes.

The claimed speed increases are wider still in database workloads, with Starburst (federated database firm) clocking a 3x uplift in large-scale SQL analytics, while Redpanda's real-time analytics saw a claimed 6x latency drop. According to Nvidia, all this purported performance is delivered by Vera's particular architecture, one that aims to deliver maximal single-thread performance with high thread counts.

We should note that vendor-approved benchmarks should always be taken with a bucket of salt, particularly those for hardware in a field that can shuffle trillions of dollars in a single day. The company doesn't say which precise x86 chips it tested Vera against, but it's a fair guess that they're mid- to high-end Intel Xeon and AMD Epyc models.

Nevertheless, in the blog post, Nvidia describes a conundrum that's familiar to most any server administrator: big-iron server chips can pack obscene amounts of cores, making them ideal for processing many tasks at once. However, the more cores you add, the slower they need to be to keep thermal performance and power draw in check. But that scale is an obstacle for tasks that need to be done now, parallelization be darned.

And the architectural decisions involved in using chiplets to scale to high core counts aren't free, either. Nvidia calls this "chiplet tax", and it says that scaling using chiplets creates memory access and performance inconsistencies that Vera's monolithic design is specifically meant to avoid.

We've long emphasized the importance of high single-threaded performance for a fast and responsive experience for client PCs, and it seems like AI agents are going to end up placing similar demands on hardware as they do their thing. If that's how the agentic AI future plays out, Nvidia's particular design optimizations for Vera make greater sense than prioritizing core count above all, as it might be for a general-purpose server chip meant to satisfy different economic and customer demands.

We'll have to see if Intel and AMD respond with "max single-threaded CPUs at scale" of their own.

Update 7/6/2026 4:10pm PT: An Nvidia representative responded with a short statement to Tom's Hardware: "Our roadmap is intact." Nvidia provided no further details in response to our follow-up questions. As such, it is unclear if Nvidia's statement refers to its original roadmap, planned delivery schedules, and hardware, or if those particulars had already been changed and the statement refers to a newly updated roadmap.

Original Story:

Nvidia reportedly won't ship its Kyber NVL144 rack until 2028, a delay of more than 12 months that pushes the cabinet meant for 2027's Rubin Ultra GPUs into the following year, according to a SemiAnalysis thread on X. The holdup is ostensibly being caused by manufacturing challenges with a PCB midplane that connects eight Oberon racks between the NVSwitches, which Nvidia calls the orthogonal backplane. Nvidia is also understood to have killed NVL72x2, a stopgap rack designed to tide customers over, and that no proven alternative is now available to widen Rubin Ultra's scale-up in 2027.

The orthogonal backplane sits between Kyber's vertically mounted compute trays and the switch trays behind them, replacing the cable harnesses of earlier racks with a rigid board that carries the all-copper NVLink fabric. Kyber runs liquid cooling by default and stacks 144 Rubin Ultra packages, double the 72 packages in a current Oberon NVL72 rack. Every GPU-to-GPU link inside the cabinet runs through that board, and copper traces lose signal integrity as layer counts increase, alongside power delivery and thermal design challenges. Jensen Huang held up the gray backplane on stage at GTC back in March.

Trade analyses of the board describe three 26-layer sections laminated into one 78-layer stack close to a square meter in area, with trace spacing at or below 25μm and impedance held within a tolerance of 5% to keep 448 Gb/s-class signaling intact. A cabled version of the same interconnect would need upward of 20,000 discrete cables, which is why Nvidia is moving the wiring onto a single passive board.

NVL72x2 would have bolted two Oberon racks back-to-back to reach Kyber-class density over copper NVLink, per SemiAnalysis, which said Nvidia abandoned the stopgap after its largest customers balked at running two linked cabinets as a single unit. NVL576, a separate configuration tying eight racks together through co-packaged optics, is likely to slip too or ship in low volume until that optical technology matures.

These cancellations leave Nvidia with "no proven solution to expand the scale-up world size for Rubin Ultra," meaning the largest single Rubin Ultra domain in 2027 could match, but not exceed, what Oberon already delivers.

Nvidia dropped the quad-chiplet Rubin Ultra GPU for a dual-chiplet part last week over manufacturing execution concerns, halving the accelerator's per-package compute. SemiAnalysis has also placed a fully production-ready co-packaged optics NVSwitch no earlier than the Feynman generation that follows Rubin, which leaves copper as the only near-term solution for linking Rubin Ultra at rack scale and thereby puts even more weight on the PCB midplane.

The delay only applies only to the Rubin Ultra phase and its Kyber rack. Nvidia's 2026 Rubin GPUs, which reuse the current Oberon rack, aren't part of the reported delay. We've reached out to Nvidia for comment.

Nvidia shouted proudly in a recent blog post that its network of American manufacturing partners and suppliers now spans 43 states, that TSMC's Phoenix plant is producing Blackwell wafers at volume, and that it plans to produce up to $500 billion of AI infrastructure in the U.S. over four years with partners including TSMC, Foxconn, Wistron, Corning, Coherent, and Amkor. Intel has made its own case in an America 250 post presenting end-to-end U.S. capabilities across design, manufacturing, and advanced packaging.

Both accounts hold up at the wafer stage but omit the same downstream step: every Blackwell die that leaves TSMC's Arizona fab still crosses the Pacific to be packaged, no HBM is manufactured or packaged on U.S. soil, and the facilities intended to close those gaps won’t start production until 2028 at the earliest.

Lofty projects

Foxconn is building a Houston factory to produce GB300 tray modules for Nvidia, and Wistron will assemble and test Nvidia AI systems at a new facility in Fort Worth, Texas. Coherent broke ground in June on an expanded Sherman, Texas, plant that the company describes as the first volume-production 6-inch indium phosphide fab, supplying the lasers and optical components that link AI systems together.

Corning is adding more than 3,000 jobs across optical manufacturing sites in North Carolina and Texas. The post also cites an estimate from consultancy Public First that Nvidia-driven AI demand will contribute $485 billion to U.S. GDP in 2026 and support over 100,000 jobs. “AI is driving a once-in-a-generation opportunity to reinvigorate American manufacturing and supply chains,” said Nvidia’s Jensen Huang in the post.

Meanwhile, Intel's post lists R&D and manufacturing across Oregon, Arizona, New Mexico, and California, describes Ohio as “a planned site,” and devotes most of its length to workforce programs, K-12 AI education, and the company’s America250 partnership. Neither post addresses where the most advanced AI processors are actually assembled into finished chips.

The Pacific round-trip

Nvidia and TSMC produced the first Blackwell wafer at Fab 21 near Phoenix last October, and the site has since moved to volume output of Blackwell silicon on TSMC's 4NP node, the custom 4nm-class process built for Nvidia. On the other side of the Phoenix metro area, Intel's Fab 52 became fully operational in the same month as the first high-volume home of Intel 18A, and Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is capable of more than 10,000 18A wafer starts per week. Panther Lake reached broad availability in January, Clearwater Forest is due in the first half of this year, and 18A yields are expected to reach industry-standard levels in early 2027, which I covered in my examination of Intel's fab roadmap.

This ultimately means that leading-edge logic wafers are now being fabbed in the U.S. by two companies on two competing nodes. That’s a genuine change and, by any measure, a monolithic achievement when compared to the start of the decade, and neither company overstates that in their corporate blogs.

However, a Blackwell data center GPU pairs two reticle-sized compute dies with eight stacks of HBM3e on a silicon interposer using TSMC's CoWoS-L packaging, and all of TSMC's CoWoS capacity is located in Taiwan. TSMC’s U.S. facilities currently send 100% of their chips to Taiwan for packaging, including wafers fabbed in Phoenix. A Blackwell die fabbed in Arizona therefore travels roughly 7,000 miles to be diced, stacked, and mounted, then travels onward through system assembly before any of it returns to a U.S. data center.

As for HBM, every stack in production today comes out of SK hynix and Samsung facilities in South Korea or Micron's fabs in Taiwan and Japan, and the ABF substrates beneath the interposer are similarly concentrated in Japan and Taiwan. No U.S. facility currently manufactures or packages HBM. The one company running advanced packaging at scale on U.S. soil is Intel, whose Foveros operation in New Mexico handles its own 3D-stacked products and has started attracting outside interest; Google has reportedly booked Intel to package more than 3 million TPUs in 2028. Intel doesn’t currently appear anywhere in Nvidia's list of manufacturing partners.

Nothing before 2029

Amkor also broke ground on its Peoria, Arizona campus last October, a $7 billion, two-phase project with up to 750,000 square feet of cleanroom, roughly $400 million in CHIPS Act funding, and Apple and Nvidia signed as lead customers. Its first factory will be completed in mid-2027, with production beginning in early 2028. TSMC formalized the relationship on June 16th, signing a 10-year agreement under which it will procure packaging and test services from Amkor, while TSMC executives said in April that the foundry's own Arizona packaging facility will bring CoWoS and 3D-IC capacity online before 2029.

SK hynix began initial work in April on its $3.87 billion advanced packaging plant in West Lafayette, Indiana, targeting mass production of HBM4E and HBM5 in the second half of 2028, the same window Amkor’s aiming for. The timing means the entire Blackwell family, and likely the first Rubin generation, will complete their product lifecycles without a fully domestic manufacturing path. The first AI accelerators that can be fabbed, packaged, and fitted with U.S.-packaged memory without leaving the country will be HBM4E-era parts arriving around 2028 to 2029.

Unfortunately, the Section 48D advanced manufacturing tax credit, raised to 35% last July, doesn’t apply to projects whose construction begins after December 31st, 2026, which gives Coherent's June groundbreaking, SK hynix's April piling work, and Amkor's October start a shared fiscal deadline if they want to benefit from it.

As for Foxconn and Wistron’s Houston and Fort Worth plants, they’ll receive GPUs packaged in Taiwan and assemble them into trays, racks, and systems on U.S. soil. It’s that type of assembly work that’s carrying most of the $500 billion figure, which counts the value of AI infrastructure produced rather than capital spent on factories. Wafers are American, racks are American, but everything in between isn’t. Whether that changes on schedule is a question for 2028, and it depends highly on two packaging campuses in Arizona and one in Indiana meeting their deadlines.

A Chinese reviewer on Bilibili by the name of 杰某 (Jie Mou) got his hands on a special RTX 4080 graphics card that uses a mobile core instead of a desktop one. These GPUs emerged after the Trump admin banned the sale of RTX 4090s in the region, which forced local sellers to resort to strange alternatives, one of which is the supposed "RTX 4080M." It's a custom, modded GPU that doesn't come with a warranty or official drivers, and the benchmarks show it doesn't offer world-beating value either.

The reviewer paid 2,000 RMB (~$300) for the tested card but remarks that it now costs close to 2,700-2,800 RMB (~$400) due to the ongoing component crisis caused by the AI rush. At that price, it's almost as expensive as AMD's RX 9070 GRE or Nvidia's RTX 5060 Ti in China, both of which will be brand new, warrantied cards. However, a similarly-modded RTX 4090M in China would cost an absurd 10,000 RMB (~$1,470).

Before we go over the benchmarks, the test bench used here was comprised of an Intel Core Ultra 270K Plus mounted on a Maxsun Z890-A motherboard alongside 32GB of DDR5-8200 RAM. In 3DMark TimeSpy, the 4080M scored 18,600 points, which is a respectable result in and of itself, but underwhelming when you take its price into account. Someone in the comments showed the same card netting 19,500 points as well.

During the benchmark, the card only pulled around 100W, which is significantly lower than even the mobile RTX 4080's TGP. The mobile core can be pushed up to 175W as per Nvidia's own spec and you'd expect that in a discrete GPU form factor, but it's likely that the custom BIOS or the drivers are holding it back. Speaking of which, the drivers can be easily configured with one-click installers developed by the community.

Moving toward gaming, the reviewer compared the 4080M against the aforementioned RX 9070 GRE because of their similar price brackets in China, and both come packing 12GB of VRAM. PUBG was the only game where the 4080M was clearly superior, achieving a 100 FPS lead over the AMD option at 1440p resolution with Ultra settings. In Delta Force at 1440p Ultra, both cards performed the same, but the 4080M did manage to net 10 more FPS at 4K.

The reviewer then tested AAA titles where the RX 9070 GRE basically smoked the 4080M as the resolution scaled upward. We'll add a table below so you can see the exact numbers, but the closest the 4080M came to dethroning the Red Team was in Shadow of the Tomb Raider. Running at 1440p with Low settings, the 4080M pushed 286 FPS on average, while the RX 9070 GRE still won with 274 FPS.

At the end, the verdict ultimately turns out to be boring: the RTX 4080M is not a sensible purchase at the current Chinese market prices because similarly-priced new GPUs outpace it with ease. However, since it only drew 100W in games, there's an argument to be made for SFF builds. There's limited thermal headroom in an ITX system and that's where the RTX 4080M could thrive.

Nvidia's rich driver suite and superior upscaling tech also add value to the proposition. At roughly $400 converted, perhaps the 4080M can power a DIY Steam Machine that truly undercuts Valve's pricing while delivering much better performance. After all, it's made from salvaged laptop GPUs and qualification samples that are cheaper to acquire, so a MacGyver-ed, console-busting rig is where it can meet its natural match.

One of Jensen Huang’s used leather jackets is up for auction, posted with an estimate of $40,000 to $60,000. Sotheby’s, better known as a purveyor of blockbuster fine art and historic artifacts, is auctioning this item of worn clothing. The storied auction house asserts this is a genuine article, as worn by the Nvidia CEO at an event in Taipei in 2023. It has also made sure the signature within the garment has been professionally authenticated. Having watched a few tech memorabilia auctions lately, I’d say the official estimate is on the low side.

Sotheby’s auction is titled ‘The Jensen Jacket: Jensen Huang's Tom Ford Leather Jacket.’ Its catalog notes that this signature black leather jacket has been Huang’s standard attire for more than a decade and has become “associated with some of the most consequential moments in modern technology.” This jacket, or one like it, has been on stage helping to define the rise of artificial intelligence. It may also have been worn by the Nvidia CEO visiting a humble street food vendor in a Taiwan night market.

So, it is important to understand that this is one of many jackets Huang has sported during keynotes, announcements, and special events over the years. Like any good auction house, Sotheby's has thus certified the provenance of this particular garment.

“The Jacket has been photomatched by PSA [Professional Sports Authenticator] to Jensen Huang, co-founder and chief executive officer of Nvidia Corp., during the Hon Hai [Foxconn] Tech Day in Taipei on October 18, 2023,” writes Sotheby’s in its auction catalog. A very specific array of creases and deformities in the right-breast pocket flap appears to confirm that this jacket was worn by the Nvidia CEO at the Hon Hai [Foxconn] Tech Day in Taipei in October 2023. Sotheby’s also states that “The signature has been authenticated by James Spence Authentication.”

Any readers interested in grabbing this jacket will likely be interested in the condition of the garment. There are a few pictures on the catalog page, including a close-up, which was used to ‘photomatch’ this particular 2023 Tom Ford-made sample. As a Sotheby’s account holder, I also read the condition report, which begins with the assertion that “The Jacket and signature are in pristine condition.” But there follows a lot of legal jargon which can be summed up as – the actual condition and appearance of the jacket might not be perfect, nor look exactly like the photographic representations of it.

If you do splash your cash on this old jacket, you should be pleased to know that your hard-earned money will be going to charity. Sotheby’s says that the sale was organized by Long Journey Ventures to benefit the Edge Institute, described as “a non-profit that convenes people working at the frontiers of tech, science, culture, and society in pop-up villages (Edge Cities) to live together and experiment towards a brighter future.”

A low estimate to attract bidders?

Does the $40,000 to $60,000 estimate take into account the jacket's Jensanity factor, or AI inflation? Also, we are in an AI boom right now, with skyrocketing prices and valuations, yet people might have spent more than the top estimate for a mere NFT of this jacket a few years ago.

On a cautious note, though, we aren’t sure how many of these jackets the Nvidia CEO has in his wardrobe. And if there were another 10 or 20 that may someday be released for sale, then the expected price could slide dramatically.

A brand new Tom Ford SS2023 menswear collection jacket, without a sprinkle of genuine Jensanity, costs around $9,000. In that context, Sotheby’s estimate puts only a modest premium on this verified genuine Jensen Huang-worn and signed artifact.

Nvidia has announced a new business model under which it’ll be able to double-dip for revenue on the same silicon: once when its partner AI clouds use its hardware, and again as an ongoing percentage of the revenue that hardware generates. In a blog post co-authored by CFO Colette Kress, the company pitched the “revenue-sharing and credit-support model” as a way to open compute access to startups that can’t finance it themselves. In practice, cash-poor AI companies trade a slice of whatever they eventually earn for tokens today, while a supplier already running roughly 75% gross margins reaches into its customers’ income statements for a second helping of cash. Australia's Sharon AI and Singapore-based Firmus Technologies are the first named partners.

Under the structure, participating AI clouds procure Nvidia infrastructure and sell Nvidia-powered cloud services to end customers. Nvidia collects its usual product revenue on the hardware plus a percentage of the cloud income earned on that capacity, which the blog post describes as a recurring, usage-linked earnings stream. Per Bloomberg, developers receive token credits in exchange for a slice of their future sales, but neither Nvidia nor its partners has disclosed the revenue-split percentages.

It’s no secret that the credit-support side of this model will help to address a financing gap that Nvidia itself has identified. Even signed, long-term customer commitments have failed to convince lenders to fund large-scale deployments, leaving smaller clouds unable to borrow against the demand they had already generated.

In an 8-K filing dated June 12th, Sharon AI disclosed that the agreement runs for six years and covers 72 MW of new Australian data center capacity built to Nvidia's DSX AI factory design, scaling to as many as 40,000 Grace Blackwell GB300 GPUs. The Nasdaq-listed neocloud separately holds a revenue-share facility of up to $200 million with investor Digital Alpha, disclosed in its CY25 results, meaning portions of its income are now pledged in two directions. Meanwhile, Firmus is building a DSX-aligned campus in Batam, Indonesia, that’s expected to scale to 360 MW and house up to 170,000 Nvidia GPUs.

Nvidia has spent much of the last year funnelling cash directly to its customers, including a $30 billion participation in OpenAI's $110 billion funding round and backing for xAI's $20 billion Colossus 2 financing, arrangements that drew repeated circular financing criticism. The new model inverts that: rather than investing capital that returns as GPU orders, Nvidia extends credit support and collects a royalty on its partners’ sales for years afterward.

That royalty also ties a slice of Nvidia's income to utilization instead of hardware sales. If partner clouds can’t keep racks rented, the usage-linked stream shrinks, a live concern given the depreciation pressure already building on operators paying off hardware that Nvidia refreshes pretty much every year.

Taiwanese authorities have been stepping up their investigation into the alleged AI GPU smuggling by some Supermicro employees, and it was recently reported that the police “raided” the company’s Taipei office. However, Digitimes reports that the firm is pushing back against this characterization, with Supermicro insisting that it’s cooperating with the investigation. Instead, it voluntarily gave investigators access to the workstations and electronic devices of the employees suspected of violating U.S. export controls while also placing them on administrative leave.

“Supermicro’s offices in Taiwan were not raided by any government authorities,” Supermicro Chief Revenue Officer Matt Thauberger told customers and partners in a written statement. He also confirmed with the Taiwanese government that the company was not the target of any investigation and that it has been cooperating since May of this year. "We have zero tolerance for anyone who violates the law or our internal policies," he also wrote in the letter.

Supermicro insists that it is cooperating with officials in the investigation and even gave them access, and as such the police intervention wasn't technically a “raid.” It remains unclear, though, how long the company knew about the pending police action before the authorities arrived on the premises.

This investigation is part of Taiwan’s push to investigate the alleged smuggling of Nvidia AI chips into China through its territory. The island does not have any laws that echo the U.S.’s export controls, so it’s using a loose interpretation of other regulations. This is similar to what Singapore is doing, which recently seized a $42 million mansion and $772k stashed in a bank account that are owned by alleged AI GPU smugglers. But because it also does not have export control laws like Taiwan, the accused are instead charged with fraud and money laundering.

Aside from the case brought against Supermicro employees in Taiwan, three other individuals linked to the company, including its co-founder, Yih-Shyan “Wally” Liaw, have been arrested in the U.S. on charges of conspiring to violate the Export Controls Reform Act. They allegedly used a hairdryer to soften the glue on thousands of serial numbers on the banned servers and moved them to dummy units to make them harder to track. They were then reportedly shipped via a Thailand-based government-related entity before landing in Chinese tech giant Alibaba’s warehouses.

Although Supermicro isn’t directly accused in these two cases, the fact that many of its employees are being investigated and charged is probably raising concern among its partners and customers. It has even gotten to the point that Nvidia CEO Jensen Huang has urged it to fix its export compliance controls. This is likely the reason why the company has taken moves to clarify the situation, which has already caused its stock price to slide by 8% in U.S. trading.

Valar Atomics activated its Ward 250 nuclear microreactor on stage during a live event, where it announced its partnership with Nvidia to power an AI factory. The company shared a portion of the live stream on its LinkedIn account, where one of its team members plugged an Nvidia RTX desktop unit into the reactor, which was then turned up to 37% of its full power to activate the Blackwell-powered PC. The company then showed off the nuclearwebsite.com page, which it says is solely run from a server that’s powered by that reactor. Its CEO, Isiah Taylor, claims that anyone can go to the website as long as the reactor is running.

“The Nvidia chip that Gabriel was just holding on stage is now plugged into a circuit in the OCS. That circuit runs through a cable into the reactor hall. In the reactor hall, 10 to 15th power uranium atoms are fissioning every second, producing 100 kilowatts of thermal energy,” Taylor said on the stage. “That thermal energy is being extracted by our cooling loop, the pressurized helium system, and the hot helium is flowing into a thermal electric generator (TEG). That TEG is creating the electrical current, which is right now powering Nvidia’s Blackwell chip, which is currently serving this website.”

Although the company claims that it’s the first startup to achieve power production, the Department of Energy says that two other firms, Deployable Energy’s Unity and Antares Nuclear’s Mark-0, have also achieved criticality, meaning these players are also on their way in making electricity using small modular reactors. Many AI tech giants and hyperscalers, like Amazon, Google, Microsoft, Nvidia, and Oracle, have invested in nuclear technologies as early as 2024, as they projected that AI data centers would require massive amounts of power.

This has become a major national issue recently, with data centers being blamed for massive increases in power and utility costs, as well as increased water consumption and a reduction in the quality of life in the communities that surround these developments. These problems have caused Americans to push back against these projects, with 7 out of 10 saying that they do not want a data center in their backyard. This resistance has led to the delay or cancellation of at least 75 projects in just the first quarter of 2026.

The public’s pushback and the resulting actions of local and state governments against power- and water-hungry data center projects are forcing both the private and public sectors to innovate. Aside from these SMRs, which will deliver the electricity demands of these data centers and other sites without affecting the national and local grid, Amazon, Microsoft, and Nvidia are also working on technologies that will cut down data center water use by up to 100%.

Two individuals, Lim Jenny and Woon Guo Jie Aaron, have been charged with money laundering by Singaporean authorities in line with their investigation of AI chip smuggling into China that used its port as a transshipment point. Nikkei Asia reported that the people have accrued more than USD 926k (SGD 1.2 million) in each of their bank accounts as proceeds of criminal activity. Alongside the accusation, the police also seized a mansion worth $42 million (SGD 55 million) that was bought using the laundered funds and froze USD 772k (SGD 1 million) kept in a bank account. Aside from that, Woon, alongside fellow Singaporean Wei Zhaolun Alan and Chinese citizen Li Ming, face fraud charges for their role in purchasing AI servers and then forwarding them to China.

The U.S. started the investigation when it looked into DeepSeek after it released its groundbreaking frontier model in late 2024. American officials were checking if the Chinese AI company used third-party firms based in Singapore to acquire Nvidia GPUs that were banned from export to China at that time. The probe showed that even though Singapore accounted for about 28% of Nvidia’s revenue, only 1% of those are actually delivered to the country. The investigation eventually led to the arrest of Woon, Wei, and Li in the first quarter of 2025. The Singapore government said that although they were not legally obliged to enforce the export controls of other nations, it said that it expects businesses operating within its borders to honor these laws.

"The police hold a zero-tolerance stance towards such offenses and will act resolutely against those, whether businesses or individuals, who violate our laws, and safeguard Singapore's integrity as a trusted global financial and business hub underpinned by the rule of law," the Singapore police said in a statement.

Since Singapore law does not cover the U.S.’s export controls, prosecutors charged them with fraud and money laundering instead, saying that the four individuals had roles in misrepresenting the end users of the servers they bought from Dell, Supermicro, and Asus. Wei is also facing a different money laundering charge with regard to the USD 4.5 million (SGD 5.8 million) stored in his personal bank accounts, which were allegedly proceeds of criminal conduct. The suspects could face imprisonment of up to 20 years each and multiple fines of up to USD 385k (SGD 500k) if they are found guilty.

In a bid to offer unbeatable performance, Nvidia had planned to use four GPU chiplets in its Rubin Ultra AI accelerator due in 2027. However, due to concerns about the manufacturability of such a solution, the company decided to cancel it in favor of a dual-GPU design that is easier to produce, according to SemiAnalysis.

Nvidia's Rubin Ultra GPU with four compute chiplets was arguably one of Nvidia's most ambitious projects in recent years, as it not only doubled performance compared to the original Rubin (which uses two compute chiplets), but also increased the complexity of Nvidia's data center GPUs to levels never seen before. However, connecting four near reticle-sized dies using existing advanced packaging technologies is a tremendous engineering challenge, and cooling four complex dies and 16 HBM4E modules is hard and costly. As a result, due to 'manufacturing execution concerns,' Nvidia reportedly canceled Rubin Ultra in its four compute dies form in favor of a design with two compute chiplets. Note that the information is unofficial, so take it with a grain of salt. We've reached out to Nvidia for comment.

As a consequence, Nvidia's 'new' Rubin Ultra would be around half as powerful as the original one, which would certainly make it less competitive against contending offerings, namely AMD's Instinct MI500-series. Of course, Nvidia will still likely optimize its Rubin Ultra design to squeeze some additional performance out of the AI accelerator to justify the upgrade.

Also, keep in mind that Nvidia's Rubin Ultra uses HBM4E memory instead of HBM4 used by the original Rubin. Furthermore, starting with Rubin GPUs, Nvidia plans to offer liquid-cooled Kyber rack-scale systems that increase GPU count per scale-up domain to at least 144 packages, which will increase compute performance that Nvidia will sell to its customers.

SemiAnalysis notes that the impact of the cancellation of an AI accelerator with 16 HBM4E packages could have an impact on the HBM market in general, as the 'new' Rubin Ultra will only use eight HBM4E modules.

The purported cancellation of Rubin Ultra with four compute chiplets would also mean that one Rubin Ultra GPU with two compute chiplets will cost less than the original one. Meanwhile, since Nvidia is mostly focused on selling rack-scale solutions rather than on individual GPUs, it remains to be seen how this impacts the actual spending of Nvidia's partners, since if they have to buy more systems to get more GPUs, they will likely spend more than they would if they had to buy fewer systems with the same number of compute chiplets.

There's bittersweet news from the shore of the open-source Zluda project, a long-running effort to create a CUDA emulator for AMD GPUs. The project's latest blog post for version 6 shows off the fresh 32-bit PhysX support and improved Windows support. Additionally, there are a number of PyTorch-driven fixes. Unfortunately, the project has again lost commercial funding, and it's now back to being a hobby for developer Andrez Janik.

Zluda 6's 32-bit PhysX support is still in a pre-alpha stage, but the results are promising. Janik showed off multiple cloth and deformation demos running at speed, and even a screenshot showing a 3x performance uplift of 2010's Mafia II running with PhysX effects turned on. Given the pre-alpha nature, Janik notes that "fluid simulations can be glitchy, and the current method of loading ZLUDA into Steam games is poor." One of his goals is to have better support for Windows, and v6 includes a refreshed zluda.exe loader that now loads required performance libraries automatically.

Last but by no means least, Zluda v6 includes a host of PyTorch-driven enhancements, composed of compiler fixes and improvements to performance libraries. As a silver lining of sorts, Janik notes that since there's now no funding, the priorities for the project have shifted to things "[he] finds the most entertaining," justifying the addition of PhysX and the revamped Windows loader.

The project was initially started in 2020 to get CUDA running on Intel hardware, but has since then turned to AMD cards. After being abandoned in 2021, it was brought back from the dead around 2022 thanks to AMD pulling out the checkbook to make it happen — presumably because one of the main obstacles (if not the primary one) is that most all the AI software ecosystem revolves around Nvidia's GPUs.

Unfortunately, AMD also cut the funding to Zluda in 2024, and in August even forced Janik to rebuild the code the company paid for. He thankfully found an undisclosed sponsor in late 2024; likely an AI company to whom the translation layer would be valuable, letting them run CUDA AI workloads on Instinct cards. Said funding is now sadly gone once again, and Janik says Zluda is back to being a "weekend project."

For end users, it's nice to have a fully open-source drop-in replacement for CUDA binaries. As for large-scale conversion for AI usage, though, there are a number of alternative projects that look to accomplish the same end results via different means. These include AMD's HIP source code porting, Spectral Compute's Scale, and MooreThreads' Musify toolkit, to name a few.

Hardware enthusiasts, server administrators, and all regular readers of this site will be well aware of the ongoing "RAMpocalypse," the memory and storage shortage affecting nearly every market and raising prices across the board in the tech sector. If you were hoping for relief, don't hold your breath; at the International Supercomputing Conference this past week, Lenovo reportedly said "it will never be like it was last year." Underlining the point, one of Lenovo's presentation slides was titled "The 5 Step RAMaggeddon Survival Guide."

That comes to us by way of our German friends over at ComputerBase, who note that "never" was said with a smirk, thus implying that it wasn't meant to be taken literally. Instead, the message from Lenovo is that memory prices were unusually low in early 2025, and it will be a long time before we see comparatively low prices on RAM, flash memory, and other components, as the #1 worldwide PC OEM expects AI demand to continue growing.

According to ComputerBase's report from ISC 2026, Lenovo's broader message is that the economics of the memory industry have fundamentally changed. The company reportedly argued that even as significant new manufacturing capacity comes online beginning around 2028, demand from AI infrastructure is expected to absorb much of that additional output, preventing DRAM and NAND prices from returning to the lows seen over the past two years.

The report points to SK hynix's recently announced plans to triple its memory production capacity by 2034 as supporting evidence. Lenovo's reasoning is straightforward: the notoriously profit-hungry memory manufacturers would be unlikely to invest so heavily in expanding production if they expected a return to the razor-thin margins and oversupply that characterized parts of the market in early 2025.

In case you needed extra evidence for its argument, Lenovo also suggested that memory capacity itself is becoming an increasingly important consideration when designing and purchasing servers. While vendors have traditionally advertised the maximum supported memory capacity of new platforms, actually populating those DIMM slots has become far more expensive. New dual-socket servers are on the way next year with 16 memory channels per processor, meaning that even a relatively modest configuration can require around 1 TB of installed memory to fully utilize the available bandwidth.

Lenovo is far from the only company predicting a prolonged memory crunch, although the industry's incentives are worth keeping in mind. Micron recently told investors it expects supply to remain constrained through at least 2027, with only gradual improvement beginning in 2028, while SK hynix has warned the shortage could persist until around 2030 as AI infrastructure continues absorbing wafer capacity. Those forecasts are backed by multi-year supply agreements worth roughly $100 billion that Micron has already signed with customers, underscoring how seriously hyperscalers are treating long-term memory availability.

Even companies that traditionally wield enormous purchasing power are feeling the squeeze. Apple reportedly has sought permission from the U.S. government to source DRAM from Chinese memory maker CXMT, a Pentagon-blacklisted company, illustrating just how valuable additional memory supply has become as prices continue to climb. At the same time, memory vendors are enjoying some of the strongest pricing power (and profit margins) they've seen in years, giving them little incentive to accelerate a return to the boom-and-bust pricing cycles that once defined the DRAM market.

Ironically, one consequence of the ongoing memory shortage is that HBM is becoming more economically attractive relative to conventional system memory. DRAM manufacturers have redirected significant production capacity toward higher-margin HBM for AI accelerators, reducing the supply of commodity DDR5 and LPDDR5 while demand for both remains elevated. As a result, the premium for HBM-backed computing has narrowed, not because HBM has become inexpensive, but because traditional system memory has become dramatically more expensive. Hyperscalers were going to buy the GPUs anyway, so maximizing their utilization to reduce DDR5 requirements suddenly becomes an attractive proposition.

That shift helps explain Lenovo's suggestion that GPU-accelerated computing may now make more financial sense for some workloads. If an application can keep much of its working set in GPU-attached HBM, it may require significantly less DDR5 installed in the host system. With system DRAM now representing a much larger share of overall server cost than it did just a year ago, reducing memory capacity requirements can materially lower the price of deploying large-scale infrastructure.

Obviously, we don't know whether Lenovo's long-term outlook will prove accurate, but memory pricing has historically been cyclical, with periods of oversupply often followed by sharp corrections. With hyperscalers continuing to pour billions into AI infrastructure and memory vendors increasingly prioritizing high-margin enterprise products, the company believes the unusually inexpensive DRAM and NAND prices of 2024 and early 2025 may prove to have been an anomaly.

Chinese companies are paying as much as 600,000 Chinese Yuan ($82,000) for servers built around Nvidia's five-year-old A100 accelerator and modifying gaming GPUs to run AI workloads, as a U.S. smuggling crackdown and a Chinese customs freeze on legally approved chips choke off every other supply route at once, according to the Financial Times. The price of an A100 server has roughly tripled since late last year, while Nvidia's flagship DGX B300 system has doubled to more than 8 million ($1.1 million) on the black market over the past six months.

Servers built on the A100, a data-center GPU Nvidia launched in 2020, have climbed from about 200,000 Chinese Yuan ($22,300) to as much as 600,000 ($67,000) since late last year, the FT reported, citing chip traders. Demand has also pulled in gaming processors that can be modified to run inference.

Nvidia's restricted Blackwell hardware sits at the top of the same market: the RTX 6000 Pro workstation card has risen from roughly 50,000 Chinese Yuan ($5,580) at the start of the year to as much as 130,000 ($14,500), and the DGX B300, which retails in the U.S. for nearly $400,000, now trades above $1.1 million. Renting is no cheaper, with an FT survey finding that GPU rates inside China now match or exceed U.S. prices, reversing the discount that the abundant smuggled supply once provided.

Washington tightened enforcement at the end of last year, and in March, a Supermicro co-founder was charged over an alleged $2.5 billion scheme to route Nvidia AI servers to Chinese buyers. Authorities in Taiwan and Malaysia subsequently opened their own smuggling investigations, drying up the re-export routes traders had relied on. Building data centers from smuggled chips is a "dead-end," Nvidia told the outlet, adding that it provides no support or repairs for restricted products.

Beijing itself closed legal channels from the other side. After the Trump administration approved H200 exports to China, Chinese customs were instructed to block the chips at the border, and Commerce Secretary Howard Lutnick later confirmed that Nvidia hadn't sold a single H200 to a Chinese company months later. Both moves push buyers toward the same destination: Huawei, which has positioned its Ascend 950PR, launched in March, as the inference chip of choice for domestic firms.

It’s understood that the 950PR is currently undergoing testing at large data center clients in China, but output is still limited, and its native CANN software stack substantially trails Nvidia’s CUDA, so domestic supply can’t yet absorb the demand the import freeze has redirected.

Rising memory prices are only compounding all this, with one trader saying that moving away from Nvidia hardware had become harder as component costs climbed, a knock-on from the DRAM and HBM shortage now working through every tier of the AI hardware stack. Until Huawei scales the 950PR, which will take some time, or Beijing greenlights H200 imports, which is highly unlikely, prices for the remaining A100 inventory in China will continue to rise.

AI GPU maker Nvidia just announced a “hotter than a hot tub” liquid cooling system that it says will cut water and electricity use. According to the company, this new solution will run coolant — composed of 75% water and 25% propylene glycol — at 113 degrees F (45 deg C). By comparison, the water in hot tubs hovers at 100 to 104 degrees F (38 to 40 deg C). This feels counterintuitive, but the company says that the “cool” water is enough to handle the heat generated by Nvidia’s Rubin chips and exit the system at 131 degrees F (55 deg C).

Traditional water-cooling methods, especially those that use chillers, often account for nearly 40% of a data center’s power consumption. Aside from that, these systems must often deal with water loss through evaporation. On the other hand, air-cooled facilities also use a considerable amount of electricity, plus they also generate noise pollution. On the other hand, Nvidia says that this new solution uses a lot fewer resources because of its higher base temperature.

Since 113 degrees F is often higher than ambient temperature, data centers can simply rely on outdoor dry coolers to expel the heat to the environment. This is also a closed-loop system; Nvidia claims an up to 100% reduction in water consumption — it’s “filled once and runs closed for the life of the facility.” This solution is most effective in regions with cooler climates, but it should still be effective in warmer areas as long as the ambient temperature is below 113 degrees F.

Data centers that face occasional temperature swings that exceed this limit may still be required to turn on their chillers. Nevertheless, this should still reduce resource consumption, as it only needs to run them a few times per year. Aside from that, this should also allow these systems to run more efficiently, as the chillers don’t have to work as hard to hit the target temperature. It’s estimated that increasing a chiller plant’s target temperature by 1.8 degrees F (1 degree C) would reduce electricity costs by 4%. This means that data centers would save significantly on power consumption if they set their chiller units to the 70 to 75 degrees F (21 to 24 degrees C) that traditional chillers run, according to Vertiv, to the 113 degrees F (45 degrees C) that Nvidia recommends for its Rubin chips.

This solution addresses several of the issues that many local governments raised that led to the delay of more than 75 data centers earlier this year. However, it will likely take time for this cooling system to roll out to new and existing projects, so we expect the delays and resistance to continue until Nvidia’s liquid cooling system gains wider adoption. Furthermore, this only addresses the water use of the data center itself — the GPU servers themselves still require massive amounts of electricity.

Unfortunately, most of the power used by data centers, at least in the United States, comes from fossil fuel power plants, which themselves consume a lot of water. Developments that aren’t tied to the grid and get their electricity from natural gas turbines may not need as much water, but residents are concerned about the pollution they generate. Still, this new cooling solution is a step in the right direction to help make AI more sustainable.

Nvidia's GeForce RTX 5070 Ti recently earned our pick as the best all-around enthusiast graphics card for gaming in 2026 thanks to its strong baseline performance for both raster and RT gaming at 1440p and 4K.

• Get this RTX 5070 Ti deal at Newegg

The one catch is that the price for that all-round excellence has been quite high of late. We found that you can expect to pay $1099 or so at the midpoint of RTX 5070 Ti prices during our recent research for our guide to the best graphics cards in 2026, as well as our work for the 2026 GPU Benchmarks Hierarchy.

But as Amazon Prime Day rolls around, both Best Buy and Newegg are making Asus' Prime RTX 5070 Ti available for just $900 — the cheapest we've seen one of these cards go for in a long time.

Update: This RTX 5070 Ti is sold out at Best Buy, but you can still get it at Newegg.

We use the OC Edition of this Asus card for our own testing in the Tom's Hardware labs, and its clean design, quiet triple-fan cooler, and full-length metal backplate all make for a fine example of the 5070 Ti. The base Prime 5070 Ti on sale here sacrifices only 45 MHz of stock clocks to the OC Edition—a difference you'll never notice in games.

But you'll definitely feel the extra $50 to $100 in your pocket compared to the next-cheapest 5070 Tis out there, and this Asus Prime card offers an all-around nicer build than most board partners' most attainable product lines.

Beyond its strong baseline performance and 16GB of GDDR7 memory, the RTX 5070 Ti's support for superior DLSS 4.5 upscaling and Multi Frame Generation makes it easy to achieve fluid, responsive gaming across a broad range of resolutions, target frame rates, and quality settings. Especially for cutting-edge path-traced games, you'll want DLSS 4.5 and MFG at your disposal for the best experience.

If you've been waiting for an RTX 5070 Ti upgrade to elevate your gaming PC and missed out on lower prices late last year, this Asus card is the best opportunity that we've seen so far during the Prime Day stretch. Don't wait.

If you're looking for more savings, check out our Best PC Hardware deals for a range of products, or dive deeper into our specialized SSD and Storage Deals, Hard Drive Deals, Gaming Monitor Deals, Graphics Card Deals, gaming chair, or CPU Deals pages.

Servers running x86 processors from AMD and Intel used to rule the market, both unit and money-wise, less than a decade ago, but fast forward to today, Arm-based machines command well over 45% of the server market, according to data released by IDC. While technically x86 machines still control 52% of the market in terms of revenue, the real winner is a different category altogether: GPU- and ASIC/FPGA-accelerated systems, which generated over 70% of the global server revenue in the first quarter of 2026.

Server market reaches $122.6 billion in a single quarter, Dell leads the game

IDC estimates that the global server market generated a record $122.6 billion in revenue in the first quarter of 2026, up 30.4% year-over-year, as spending on AI infrastructure remained particularly strong.

Sales of ODM Direct servers — custom machines ordered by hyperscalers that run merchant or custom silicon — accounted for 50.2% of the revenue (down from 64.1% in Q1 2025) and reached $61.53 billion, up modest 2.1% year-over-year*. By contrast, sales of standard servers from well-known brands grew at a much higher pace, which suggests that branded vendors such as Dell, HPE, Supermicro, and others won a larger portion of AI infrastructure deployments than they did a year earlier. That was probably made possible by accelerating enterprise AI deployment and sovereign AI projects, which tend to buy machines from branded vendors, as well as hyperscalers increasingly turning to well-known suppliers for AI hardware.

When it comes to vendor rankings, Dell remained the largest server supplier by revenue with a 16.5% share of the market after its revenue surged 244.1% year-over-year to $20.3 billion, which was driven by exceptionally strong AI server demand. Supermicro remained in second place with $9.3 billion in revenue and a growth of 128.9%.

Lenovo ranked third with $5.6 billion and 36.5% growth, while IEIT Systems (which is a part of the sanctioned Inspur Group) dropped to fourth after revenue declined 7.0% to $4.0 billion. HPE was No.5 with $3.7 billion in revenue, up 17.2%. Other vendors — from Asus to Atos and from ASRock Rack to Gigabyte — commanded 14.8% of the market with $18.11 billion in revenue, up from 13% and $12.21 billion in the same quarter a year ago.

Arm-based machines rapidly gain revenue share

As AI servers dominated the market in Q1 2026, systems with various types of accelerators accounted for over 70% of the revenue. However, the rise of Arm-powered machines is the elephant in the room that is hard to miss, as it represents a tectonic shift in the whole market, both to the Arm instruction set architecture (ISA) in general and custom-built Arm CPUs designed by hyperscalers.

Non-x86 platforms generated $58.7 billion in revenue, a 107.6% increase year-over-year, which lifted their share of the market to 47.9%. Most of the non-x86 systems are Arm-based AI machines (think Nvidia's NVL72) as well as systems running custom CPUs, AWS, Google, and Microsoft, just to name a few. Still, also keep in mind IBM Z mainframes and IBM Power Systems (including storage) that use CPUs featuring proprietary non-x86 and non-Arm ISAs and which still generate $1 billion or more in revenue. IDC claims that Arm-based machines accounted for more than 95% of non-x86 revenue, so it is safe to say that Arm-based machines commanded over 45% of server revenues in Q1 2026.

One of the reasons why Arm-based machines now command a huge chunk of the server market is because they are used inside such systems as Nvidia's NVL72 'Blackwell' that sell for up to $6.5 million per unit. Each NVL72 rack-scale solution carries 36 compute trays with two Blackwell GPUs and one Grace CPU per unit, so while unit-wise each we are only talking about 36 processors, dollar-wise one NVL72 machine is as expensive as 928 entry-level 1P server (for $7,000) for cloud or edge applications or 433 higher-end 2P servers (for $15,000) for cloud or virtualization applications.

Given the fact that Nvidia will continue bundling its own Arm-based Vera CPUs with NVL72 'Vera Rubin' machines that will be more expensive than their Blackwell ancestors, we will not be surprised that Arm-based machines will account for well over 50% of the server market revenue in the second half of this year or in 2027. Also, keep in mind that Nvidia plans to sell server racks featuring only Vera CPUs for agentic AI applications, which will further drive sales of Arm-based machines.

Accelerated servers: The real winner

Since AI servers dominate server sales, it is not surprising that sales of accelerated servers are increasing. Systems equipped with GPUs produced $68.9 billion in revenue during the quarter (up 24.8% compared to the same period a year earlier) and accounted for 56.2% of all server sales. Servers based on other accelerator types, including custom ASICs and FPGAs, expanded to $17.7 billion, up 122.1% YoY. As a result, accelerated servers earned $86.6 billion in Q1 2026, which is around 70.6% of all server revenue.

X86 servers remain unit volume champions, but suffer from shortages

In contrast, x86 server revenue declined 2.9% to $63.9 billion, though IDC attributes this weakness to supply limitations rather than deteriorating demand. The market research firm claims that the industry's primary constraint is no longer customer appetite for general-purpose servers, but rather the availability of key components, including CPUs, DRAM, NAND memory, and hard drives.

Without any doubt, x86 servers remain working horses for the industry. In fact, many of them use accelerators, including ASICs, FPGAs, and GPUs, as they are used for a wide range of workloads, including AI, supercomputing, simulations, encryption, video transcoding, and many more.

AMD and Intel shipped nearly 20 million EPYC and Xeon SP processors for data center systems in 2025, according to Dean McCarron, the head and principal analyst at Mercury Research. He believes Nvidia is on track to ship four million Grace and Vera CPUs this year, which is considerably lower compared to shipments of AMD and Intel. It is hard to estimate how many custom Arm-based CPUs are deployed by AWS, Alibaba, Google, and Microsoft, but it is safe to say that we are talking millions of CPUs here; otherwise, the companies would not be able to justify development and production of custom silicon.

From a volume perspective, x86 servers remain the most popular machines, and it will probably take some time before ARM can challenge x86 in mainstream general-purpose servers. Nonetheless, it is safe to say that Arm-based data center CPUs are catching up with x86 parts in terms of volumes.

Summary

The global server market hit a record $122.6 billion in the first quarter of 2026 as AI infrastructure spending continued. Accelerated systems powered by GPUs, custom ASICs, and FPGAs generated more than 70% of server revenue, while Arm-based platforms — including Nvidia's Grace Blackwell as well as custom CPUs from Arm, Google, and Microsoft — captured nearly half of the market.

Although x86 servers based on AMD EPYC and Intel Xeon processors remain dominant in shipment volumes, supply shortages of CPUs, memory, and storage components constrained revenue growth, which further enabled Arm-powered AI-optimized systems to gain share. But while at 20 million data center processors per year, x86 volumes are untouchable for Arm today, things may change in the coming years. Nvidia is on track to ship 4 million CPUs in 2026, and other developers of custom Arm-based CPUs are certainly not standing still.

*There is one significant difference with IDC's 'ODM Direct' classification. IDC classifies revenue according to which company invoices the customer, not necessarily who manufactures the hardware. As a result, while many AI servers are built by ODMs like Compal, Foxconn, or Quanta, they are sold under brands like Dell or HPE. As a result, while the latter get more business from enterprises or sovereign AI deployments, this does not mean that big ODMs are losing business; they are actually gaining it, as the appetites of hyperscalers like AWS, Google, Meta, or Microsoft are not going anywhere, just demand from new entrants emerges.

NVK, the community-built open-source Vulkan driver for Nvidia GPUs in Mesa, has gained experimental DLSS support, with the code landing in Mesa 26.2-devel, as reported by Phoronix. The driver doesn’t reimplement the upscaler but instead loads Nvidia's own pre-compiled CUDA binaries and runs them, a workaround that keeps the feature behind an experimental flag and ties it to whether compatible bytecode exists for a given card. Nvidia's proprietary Linux driver has of course handled DLSS for years, so the change closes one of the bigger gaps between the closed driver and its open-source counterpart, rather than bringing the technology to Linux for the first time.

DLSS runs on NVK through VK_NVX_binary_import, a Vulkan extension that lets an application load Nvidia CuBIN files, the pre-baked CUDA binaries Nvidia, and loads them on the GPU. Autumn Ashton opened the original pull request for the extension last year, and Thomas Andersen revived it roughly two months ago to clear merge conflicts and finish the work, with the path sitting behind the NVK_EXPERIMENTAL=dlss environment variable because known bugs remain.

The catch is the reliance on pre-compiled binaries; NVK can only run DLSS where compatible bytecode already exists for the GPU in use. The proprietary Nvidia driver avoids that limit with a route that compiles PTX, Nvidia's intermediate assembly, down to GPU bytecode at runtime. NVK has no equivalent, because it can’t translate Nvidia PTX into NIR, which is the intermediate representation Mesa drivers compile from.

Support for DLSS across the broader Linux graphics stack has been uneven, to say the least. As of late last year, Nvidia's DLSS 4 was still unsupported in Valve's VKD3D-Proton translation layer, which converts DirectX 12 calls to Vulkan for games running through Proton.

NVK began in 2022 as a from-scratch Vulkan driver led by Collabora's Faith Ekstrand alongside Karol Herbst and Dave Airlie at Red Hat, and it supports Turing (RTX 20-series and GTX 16-series) and newer architectures. In late 2024, it became the first open-source Vulkan driver for Nvidia hardware to pass Khronos conformance, reaching Vulkan 1.4 provisional spec. It runs on the Nouveau kernel driver and is separate from Nvidia's own open-source kernel modules, which the company ships with its proprietary user-space software stack.

At the XDC2025 conference in November, Ekstrand said NVK runs at around 50% of the official Nvidia driver's speed in many titles, that ray tracing is still in progress, and that the team is "barely keeping the lights on" with current developer resources, according to Phoronix.

Nvidia has just released a new update for RTX Remix, its modding platform designed to retrofit old games with modern lighting and materials. RTX Remix 1.5 brings a bunch of improvements, but the highlight feature is the improved RTX IO storage compression that can cut down on the size of modded games. The update also adds agentic AI in the form of RTX Remix Skills, along with Smooth Normals for more natural-looking geometry.

Let's start with RTX IO, which is by no means a new technology — it was introduced back in 2020 with the RTX 30 series — but it's now integrated in RTX Remix. Upgrading old games with fully ray-traced lighting, along with sharper textures, skyrockets their sizes. The original assets aren't replaced either since RTX Remix intercepts the game at runtime and simply injects the new assets on top while suppressing the older ones.

Now, thanks to new compression options in the packaging workflow, RTX IO can help reduce those ballooning file sizes considerably. Currently, Portal with RTX, Portal: Prelude RTX, and Half-Life 2 RTX demo support this feature. As such, the Half-Life 2 RTX demo has shrunk down from 80GB to just 50GB, constituting a 37.5% decrease, while Portal with RTX is now only 17GB instead of the 27GB it was previously.

RTX Remix 1.5 also brings a highly requested community feature called "Smooth Normals." Basically, once older geometry was upgraded with modern lighting, some elements would look blocky, almost as if anti-aliasing was turned off. Smooth Normals fixes this by making those assets look smoother and more lifelike. Traditionally, this is a manual process, but the new update now generates smooth normals automatically.

Lastly, RTX Remix Skills is now available in the modding platform, where you can use agents to help you accelerate your workflow. Nvidia pitches this as a lower barrier to entry for modding, even without coding skills or experience, and for remastering modern games that don't have fixed-function pipelines. Apparently, Dark Souls, Dragon Age: Origins, and Titanfall 2 are already in the process of being upgraded thanks to "this streamlined approach."

Today, RTX Remix is publicly available and open source, so you don't even need an Nvidia GPU to enjoy these modded games, and there's actually a pretty solid selection of them over at ModDB. You definitely, however, need an Nvidia GPU to develop/make the mods; you can grab RTX Remix right from the Nvidia App. The Remix agent instruction files for your preferred coding agent are available on GitHub.

Nvidia has showcased agentic robots that can teach themselves high-precision and dexterous tasks in the real world. As part of the demo reel for this ENPIRE technology, we see a room full of robots do things like pick up and slot a graphics card in a motherboard, as well as sort metal pins in a container, and manipulate and correctly cut zipties. Jim Fan, Nvidia’s Director of AI & Distinguished Scientist, said that this demo shows researchers can “enable AutoResearch in the physical world for the first time!”

Fan explains that the ENPIRE project gave 8 Codex agents a fleet of robots, an allocation of GPUs, and a generous token budget. Then the agents were given a task to solve as quickly as possible, without making mistakes. Once instructed, “The robot fleet starts to come alive: they learn to look for visual clues, reset the scene, practice novel skills, tinker with control stack, read papers online, debate, reflect, get stuck, and try again directly on the hardware,” explains the Stanford-based scientist. “All we did is giving Codex an API to the world of atoms, and the rest is emergence.”

We were most interested to see a robot “installing GPUs all by itself.” In the brief recording of this particular PC DIY task, you can see one robot arm select and pass a graphics card to another with a motherboard in front of it. The second arm then carefully positions the PCIe slot of the card to align it with the motherboard slot, gently descends, and pushes it into place. It seesawed a bit on insertion, but we guess it would have been fine. Other AutoResearch projects the robots were set to do included organizing fine pins, plus tying and cutting zipties.

In the associated ENPIRE: Agentic Robot Policy Self-Improvement in the Real World research paper, you can learn more about the techniques behind this demo. You can also see the comparison test results when different coding agents were used, including Codex with GPT-5.5, Claude Code with Opus 4.7, and Kimi Code with Kimi K2.6. The researchers also tested scaling up the robot fleet, concluding that “eight robots exploring in parallel solves the task significantly faster than fewer ones.” Fan joked that the goal is to train up the robots, then everyone goes on holiday, “and Jensen wouldn't even notice ;)”

While hyperscalers rush toward expansion amid the swelling demand for AI data centers, Marvell last week shared its vision for an optical interconnect solution that can theoretically pool resources between discrete data centers across thousands of kilometers.

Optical interconnections are steadily being deployed across the industry, over both short and long-distance connections, and we're going to be seeing much more in the future, according to Matt Murphy, Chief Executive at Marvell, speaking at Computex 2026.

"Imagine future data centers, a globally optically interconnected data infrastructure," Murphy said. "These rigid boundaries we have today, and the systems we have, they begin to disappear. Compute can now be pooled, memory can be pooled, and infrastructure can be composed dynamically at scale."

Constrained by distance

Murphy says that workloads no longer fit within one data center, which is why hyperscale cloud service providers increasingly need to build entire campuses consisting of multiple data centers connected by high-speed links, as clusters are becoming larger than a single data center.

Today, connecting multiple data centers within a single campus is not easy or cheap, but relatively straightforward. However, Marvell envisions that in the future it will need to connect data centers that are located at considerable distances from one another.

This is why Marvell is working on coherent optics and long-haul scale across optical networking technologies, which will connect data centers separated by thousands of kilometers. Marvell already has products which enable such connectivity today, including the Colorz 1600 1.6 Tb/s coherent optical solution based on a 2nm DSP, which targets inter-data-center connectivity and will sample later this year.

In addition, Marvell says it will offer the Ara 1.6 Tb/s family of interconnect solutions for data centers (with 3nm DSPs) as well as the Teralynx T100 102.4 Tb/s Ethernet switch, which supports 512 ports running at 200 Gb/s or 64 ports running at 1.6 Tb/s.

Murphy argues that today's architectures are constrained by distance because of copper interconnects: CPUs sit near memory because latency matters, GPUs sit near memory because bandwidth matters. As a result, workloads must be partitioned according to those physical limits. The head of Marvell claims that once optical interconnects penetrate scale-up interconnects, scale-up domains will not be limited by copper cable lengths, and those constraints will begin to disappear.

Nowadays, scale-up AI solutions, such as Nvidia's NVL72, are connected using copper wires, but scale-out connections tend to use optical interconnects. Once the number of AI accelerators within scale-up systems increases, they will also have to move to optical links, according to Marvell. This means that virtually all data center-grade interconnections will become optical, which might inspire hardware developers to reconsider the architecture of data centers.

Pooling resources

Murphy presented a rather interesting vision: firstly, optics will expand scale-up domains from 72 or 144 accelerators to 1,000 or more. But after that, optical connectivity will enter servers themselves. This will enable developers to disaggregate CPUs, accelerators (Marvell calls them XPUs), and memory into separate pools as distance will no longer matter, enabling better configurability and utilization.

"It is a data center without distance, where compute, memory, networking, and photonics operate as one unified system, where millions of resources across the data center can work together as if they were one machine," the head of Marvell said.

Keeping in mind that hyperscalers deploy hardware worth billions of dollars, even a 10% higher utilization will save a lot of money, and companies like Nvidia are clearly paying attention.

"In today's systems, the ratio of CPU and XPU or GPU is fixed, so these ratios have to be defined at the time the system is built and deployed, but no two workloads require exactly the same ratio," Murphy stressed. "Imagine a completely disaggregated architecture, XPUs in one system, memory in another, generic CPUs in another."

Today, companies buy something like an NVL72 system and get a fixed ratio of CPUs, GPUs, and memory, which may be efficient for certain workloads and inefficient for others. In the future, operators will be able to assemble a virtual machine from shared pools of systems, allowing for customization and flexibility, based on the type of workload. If a workload needs more memory than compute, operators often have to buy additional GPUs just to get the extra HBM, but they may just get memory in the future if Marvell's vision comes to pass.

"Once we decompose the system into separate pools of compute, memory, and they are all optically interconnected, we can then compose dedicated systems on the fly, which are then optimized wherever the workload is," Murphy said. "For the first time, architects can begin designing AI systems around the needs of the model, not around the limits of the interconnect."

One detail

While Marvell has the know-how to interconnect data centers across thousands of kilometers and technologies that enable pooled data centers, these visions do not necessarily intersect. Data centers located thousands of kilometers away cannot share resources — a 1,000 km round-trip takes light 10ms — which makes such long-distance resource sharing inefficient from a latency point of view.

However, Marvell's technologies enable hyperscale CSPs to synchronize AI campuses, access distributed storage, replicate data, and perform other operations that do not depend on latency. Meanwhile, the synchronization of AI campuses on different continents in a matter of hours could be a killer app for hyperscalers.

China's Supreme People's Court on Friday upheld an injunction prohibiting Infineon from selling the disputed gallium nitride (GaN) products in mainland China, the final word in a patent case brought by Suzhou-based rival Innoscience, SCMP reports. Both companies sit on Nvidia’s approved supplier list for 800V AI-rack power delivery, and the judgment caps a year of litigation that has handed each side a win in different jurisdictions.

The court upheld a May 27th judgment from the Suzhou Intermediate People's Court that found Infineon infringed two Innoscience invention patents, ordering it to stop selling, offering, and importing the products and to pay 10 million yuan (roughly $1.48 million) in damages.

In May, the full U.S. International Trade Commission affirmed an earlier determination that Innoscience infringed an Infineon patent and ordered import and sales bans, pending a 60-day presidential review period. Innoscience disputes this the impact of this, stating that the same ITC determination cleared its redesigned current products and that its U.S. shipments continue uninterrupted. A German case at the Munich District Court I added a third front, where judges found infringement by Innoscience in 2025, with further patent and utility-model trials scheduled for this month.

"This decision once again highlights the robustness of Infineon's intellectual property," said Johannes Schoiswohl, senior vice president and head of Infineon's GaN Systems business line, in a May statement on the ITC ruling.

GaN is the underlying material that’s powering Nvidia’s shift away from 54V rack distribution toward an 800 VDC architecture for racks pushing past 200kW toward a megawatt. Raising rack voltage to 800V cuts current and copper across the conversion chain, and GaN's faster switching shrinks the power stages between the rack and the GPU core. Both Infineon and Innoscience appear on Nvidia's silicon-provider roster for that transition, alongside Texas Instruments, Navitas, and onsemi.

Innoscience led the global GaN power-device market in 2024 at 29.9% according to TrendForce data, with Infineon fourth at 10.3%. Infineon counters with its 300mm GaN-on-silicon manufacturing and around 450 GaN patent families against Innoscience’s 8-inch fabs in Suzhou and Zhuhai. Mainland China, Hong Kong, and Taiwan together accounted for 38% of Infineon's fiscal 2025 revenue, per its annual report.

Innoscience's Hong Kong-listed shares rose 16.6% on Monday on the back of the ruling, while Shanghai-listed compound-semiconductor makers Silan Microelectronics and Sanan Optoelectronics each hit the 10% daily limit, and power-chip maker China Resources Microelectronics climbed about 13%.

Nvidia has told Chinese clients that its Arm-based Vera server CPUs could be available as soon as August and that orders can be placed now, Reuters reports, citing three sources familiar with the matter. Meanwhile, shipments of H200 AI GPUs to China remain frozen, months after CEO Jensen Huang said Nvidia’s market share in the country had effectively fallen to zero.

This August timeline runs in sync with what was said at GTC Taipei during Computex, when Nvidia indicated that Vera systems would reach customers through system builders and cloud partners starting this fall. Telling Chinese buyers they can have silicon in August, during a global server CPU shortage, suggests they’re sitting near the front of the allocation queue for a product line Nvidia expects to generate $20 billion in revenue by the end of its fiscal year in late January.

According to the report, Chinese cloud companies are already testing more than 300 Vera servers, and at least one major cloud provider plans to place an order. Initial deployments will be restricted to those companies' overseas data centers, one of the sources said.

If this goes ahead, Vera will reach Chinese buyers where Nvidia’s GPUs can’t. Server CPUs face far lighter U.S. export restrictions than the accelerators that underpin Nvidia's data center business, and the company's recent history in China shows that Washington is no longer the only obstacle. The U.S. licensed roughly 10 Chinese firms to buy the H200, but not a single unit has been delivered because Chinese officials, intent on nurturing domestic chipmakers, withheld approval on their side.

That dynamic helps to explain why the deployment of Vera CPUs will be restricted to overseas data centers: Chinese cloud providers want the hardware, but putting U.S. silicon into domestic data centers will obviously invite scrutiny and potential action from Beijing officials.

Vera began life as the CPU half of the Vera Rubin superchip, first shown at last year’s GTC event. Nvidia broke it out as a standalone product at GTC San Jose this March, launching it alongside a rack design that packs in 256 liquid-cooled Vera CPUs and sustains more than 22,500 concurrent CPU environments. Then, at Computex, Nvidia said the chip had entered full production, claiming 1.8 times faster task completion than x86 processors on agentic workloads. Its predecessor, Grace, has shipped nearly 2.5 million units to date.

Meanwhile, server CPUs are being tightly squeezed by the shift of AI workloads from training toward inference and agentic execution. Agentic AI leans heavily on host processors for tool calls, code execution, and data handling, and CPU demand has outrun supply as a result of the agentic explosion.

Intel has quoted Chinese customers lead times of up to six months, while AMD has said that the global CPU market is tight, with demand outpacing its forecasts and supply constraints expected to persist.

Last week at Computex 2026, Wiwynn showed off one of the industry's first Nvidia SCADA (SCaled Accelerated Data Access) servers. Devices such as this are built to handle the extreme data demands of AI data center-focused inference and training workloads, which operate with massive models and datasets, therefore requiring large, fast, and connected devices to serve as the backbone for complex, high-throughput tasks that AI workloads depend upon.

Wiwynn's SCADA server packs up to 96 liquid-cooled solid-state drives and therefore offers petabytes of storage space using currently available E3.S drives, and massive I/O performance. The machine is based on Nvidia's Vera CPU, four RTX Pro 6000 Blackwell graphics cards, four PCIe 6.x switches, and four ConnectX-9 SuperNIC cards.

Storage architecture for AI

Modern AI inference and training workloads often deal with massive datasets that exceed the memory capacity of an AI accelerator's onboard memory, which is why AI applications need to access rapid storage.

While AI training is typically dominated by large sequential transfers, AI inference workloads such as vector search, retrieval-augmented generation (RAG), graph analytics, and KV-cache retrieval often rely on fine-grained random accesses (that frequently involve data blocks smaller than 4KB) with extreme parallelism, as the system deals with thousands of GPU threads.

Traditional CPU-centric I/O cannot efficiently handle such workloads and creates bottlenecks because the CPU must issue commands, manage requests, and control data transfers. Even in advanced solutions like GPUDirect Storage, which allows data to be transferred directly from SSDs to GPUs, the CPU still owns the control path and can become a bottleneck.

The SCADA platform, previewed in late 2025, is designed to allow GPUs access to very large datasets directly and efficiently without involving a central processor. This is impossible to do on conventional machines, as SCADA lets GPUs themselves initiate and control storage I/O operations and the data path.

SCADA runs on PCIe 6.x hardware from partners like Broadcom and Micron, and customers can now build their own SCADA machines with commercially available components. However, SCADA servers have not yet been popularized. In fact, Wiwynn seems to be among the first server makers to even showcase a SCADA server.

Wiwynn's SCADA server

Wiwynn's SCADA server can indeed be a panacea for the problem that is AI storage. It supports up to 96 liquid-cooled E3.S SSDs, meaning that the drives will perform as expected even under high loads. When equipped with 96 30.72 TB Micron 9650 Pro drives with a PCIe 6.0 interface, the server can store 2.949 PB of data.

On the performance side of things, Wiwynn claims an aggregated random read speed of 528 million 4K IOPS, as well as sequential read/write speeds limited by the performance of PCIe switches and/or network cards rather than the drives themselves. As manufacturers expand the capacities and performance of their E3.S SSDs, servers like the one Wiwynn demonstrated at Computex will gain capacity and performance as well.

Architecturally, Wiwynn's SCADA server is an Nvidia MGX rack-compliant system in an 6RU form-actor that has a maximum power consumption of 9 kW. All key components of the machine are liquid cooled, the drives are cooled by six separate cold plate modules that are integrated into the system's liquid cooling loop so to inject coolant to all SSDs simultaneously in order to ensure consistent performance of all drives.

Positioning

Nvidia clearly positions SCADA as tier 3.5 storage servers located behind local SSDs, but ahead of tier 4 remote storage servers that often rely on hard drives.

SCADA machines are meant to feed data to actual compute servers at a very high data transfer rate in small blocks, so its RTX 6000 Pro GPUs act more like very sophisticated storage processors that initiate and handle storage transactions, millions of small storage requests on behalf of AI applications, and pass them to the compute server via the ConnectX-9 cards, while the SSDs and their controllers still perform the actual storage functions.

In general, SCADA is a part of Nvidia's Storage Next vision, which is a collection of technologies aimed to make storage behave more like an extension of GPU memory for AI workloads.

For obvious reasons, Wiwynn does not disclose pricing of its SCADA storage server as it depends on multiple factors, including pricing of 3D NAND, DRAM, and SSDs, not to mention purchase volumes. In any case, an Nvidia Vera-based server equipped with four RTX Pro 6000 Blackwell graphics cards will not be cheap.

The memory drought continues to affect manufacturers of the best graphics cards and everyday consumers hoping to upgrade their systems. However, it seems to have impacted some vendors more severely than others. Manli (via VideoCardz) has expanded its arsenal with two new custom GeForce RTX 3060 and GeForce RTX 3050 graphics cards. The silent launch comes six years after the debut of Nvidia's Ampere architecture.

It may be perplexing to some that graphics card manufacturers are re-releasing products that are two generations old. However, it makes a lot of sense if you look at it since Ampere comes from Samsung’s mature 8nm (8N) manufacturing process. The process node should now be producing excellent yields, making it far more cost-effective to produce Ampere silicon than to produce Ada Lovelace or Blackwell silicon.

The choice to pick the GeForce RTX 3060 and GeForce RTX 3050 for an Ampere revival isn't by chance, either. While everyone dreams of playing AAA games at 4K and maximum settings, mid-range graphics cards ultimately drive the majority of sales. If we look at Steam, the world's largest gaming platform by player count, the GeForce RTX 3060 still reigns as the most popular graphics card despite being five years old. You can say what you want about the GeForce RTX 3050, but it's still sitting comfortably in fourth place.

The memory shortage has disrupted the supply chain for graphics card manufacturers, making it challenging to secure memory inventory, especially the latest GDDR7, at reasonable prices. The fact that the GeForce RTX 3060 and GeForce RTX 3050 use slower-binned GDDR6 memory chips (15 Gbps and 14 Gbps, respectively) and sometimes fewer chips somewhat helps preserve the vendor's profit margins. They're more affordable to produce and move than a GeForce RTX 4060, which uses faster, more expensive 17 Gbps GDDR6 chips, or a GeForce RTX 5050 or GeForce RTX 5060, which use 20 Gbps GDDR6 and 28 Gbps GDDR7, respectively.

The Manli GeForce RTX 3050 6GB Nebula Twin and GeForce RTX 3060 (M2521+N630) are your typical no-frills Ampere graphics cards that target consumers who value affordability over flashy features. They stick to the old tried-and-true dual-slot design with a dual-fan cooler. They conform to Nvidia’s reference specifications, meaning these graphics cards do not feature any factory overclocks.

Manli’s popularity is mainly in the Asian market, so it's highly unlikely these Ampere graphics cards will make their way to the U.S. market. Manli’s decision to re-launch two-generation-old Ampere models lends further credence to a recent rumor that Nvidia's board partners, including Asus, Colorful, Galax, and MSI, are reportedly restarting GeForce RTX 3060 production in July.

Overall, the return of the GeForce RTX 3060 and GeForce RTX 3050 to the market is not necessarily a bad thing, since these Ampere-powered graphics cards remain popular among gamers for their price-to-performance ratio. The true benefit lies with the pricing, though. Custom GeForce RTX 3060 and GeForce RTX 3050 graphics cards start at $299.99 and $239.99, respectively, which are close to their original MSRPs. Time will tell if the resurrection improves pricing on Ampere offerings.

Nvidia and SK hynix have inked a multi-year collaboration agreement under which the companies will co-develop next-generation memory technologies for Nvidia's upcoming platforms, and SK hynix will supply them to Nvidia. The deal is designed to ensure that Nvidia will get the memory it needs from a prominent supplier and will guarantee that SK hynix will be able to sell its output in a predictable manner.

The key part of the agreement is indeed the co-development of advanced memory products designed for Nvidia's future platforms. Currently, Nvidia uses HBM, LPDDR5X, DDR5, and 3D NAND memory in various systems, so going forward, SK hynix will develop its new memory with Nvidia in mind. The joint press release says nothing about customization of memory for Nvidia, and while we cannot exclude such a possibility, it looks like the companies will continue to co-develop industry-standard solutions, but will ensure that they are compatible with Nvidia's processors.

In addition, the agreement is intended to address the increasingly long lead times and massive capital expenditures required for the production of advanced types of memory. The two companies will coordinate roadmaps over multiple years. Nvidia will gain greater visibility into future memory availability, while SK hynix secures a guaranteed role in Nvidia's next-generation platforms (i.e., guaranteed demand).

The initial part of the cooperation covers memory destined for NVIDIA Vera Rubin AI systems (HBM4, LPDDR5X, 3D NAND), standalone Vera processors (LPDDR5X), RTX Spark-powered personal computers (LPDDR5X, 3D NAND), and Jetson Thor robotic computing systems (LPDDR5X, 3D NAND).

The deal also extends to semiconductor research and design. SK hynix is deploying Nvidia's CUDA-X libraries to speed up complex chip development workloads, such as technology computer-aided design (TCAD) and computational lithography (CuLitho). In addition, the memory maker is adopting Nvidia PhysicsNeMo to accelerate proprietary simulation software as well as AI-driven physics models used during semiconductor development. In addition, the companies see an opportunity to expand these capabilities into general electronic design automation (EDA) and simulation ecosystems and potentially create tighter relationships within the industry.

Last but not least, SK hynix is creating digital twins of its semiconductor fabs using Nvidia Omniverse and OpenUSD technologies. These virtual facilities enable engineers to model production lines, test changes, and optimize operations before making adjustments in real fabs. The company also plans to use Nvidia's cuOpt and Metropolis platforms to improve the movement of autonomous robots and other factory equipment. In the future, SK hynix aims to connect these digital twins with existing manufacturing software and AI systems and enable them to analyze fab data, automate routine tasks, and help make production decisions.

Next-gen gaming GPUs from both AMD and Nvidia are expected to be announced sometime next year, following the (roughly) biennial release cadence of these cards. Tweakers, a Dutch publication present at Computex 2026, asked a few manufacturers at the show about RDNA 5 and got varying responses. In general, the AIB partners suggested that we should see new GPUs about a year from now, but some thought hardware may not hit the shelves until late 2027 or early 2028.

One manufacturer said it expects next-gen AMD graphics cards in the second or third quarter of 2027, while another said it could be pushed outside 2027 entirely and into early 2028. But there's still a chance for a late 2027 release. Keep in mind that the announcement and actual launch differ; AMD could introduce RDNA 5 in late 2027, but the GPUs might actually make it to market in early 2028, for example.

AMD showed off RDNA 4 for the first time at CES 2025, while the initial models — RX 9070 and RX 9070 XT — didn't ship until March. RDNA 3 was a bit better in this regard with a November 2022 announcement and December 2022 launch period. RDNA 5 is rumored to be a major upgrade for Team Red with features like dual-issue execution in the works, so the company wouldn't want to deliver an undercooked product hastily.

Nvidia debuted the RTX 50 series at CES 2025 as well and current rumors point to Rubin-based gaming GPUs coming in late 2027, with the same early 2028 murmurs heard for the RTX 60 series as well. If true, both GPU makers would be closely aligned in their launch schedules, but it's simply too early to tell. The PC hardware industry is going through a turbulent time, and the volatility caused by the AI boom means that gaming GPUs are the least of these companies' concerns right now.

While we're here, Intel is still in the business of making gaming-focused GPUs. It just launched the new Arc G3 family for handheld consoles featuring Panther Lake silicon, but, unfortunately, the future for dedicated graphics cards is looking a bit dire. On the console side, Xbox Helix and Sony's PS6 are still expected to at least be announced next year as, by then, it will have been seven years since the current generation launched. These systems will also be powered by next-gen AMD silicon.

A potential "Super" refresh for Nvidia's Blackwell 50-series GPUs has been part of the news cycle for almost a year at this point, with the last substantial sighting coming from Seasonic's PSU calculator nine months ago. Since then, the rumor mill has been mostly silent due to an AI boom-sized component crisis that engulfed all production lines. But now, it seems like the RTX 50 Super series is "back on track," with leaker MEGAsizeGPU claiming that there's even a new SKU in the works.

We've already heard the RTX 5070 Super, RTX 5070 Ti Super, and RTX 5080 Super mentioned before, but this time, there's also an RTX 5060 Super in the mix. This rumored GPU could come with 12GB of GDDR7 RAM, according to the leak, possibly using 4x 3GB modules saturated across the same 128-bit bus that the regular RTX 5060 has. This card could also just be called RTX 5060 12GB, as Nvidia has named a few SKUs like that previously.

The leak doesn't mention other GPUs specifically, but through prior rumors, we can infer that the RTX 5070 Super might feature 18GB of VRAM, while both the RTX 5070 Ti Super and the RTX 5080 Super are suggested to rock 24GB pools — all enabled by 3GB GDDR7 chips. One of the replies in the post above claims that specs for these three SKUs apparently remain unchanged.

*= unconfirmed models based on leaks and rumors

We don't know when these GPUs will actually be released, but the leaker says he expects them to still launch in 2026. With DRAM being as expensive as it is right now, and GPU prices affected by the AI boom, these new RTX 50 Super SKUs may not exactly be good value. Back in November of last year, there were murmurs of these GPUs even being cancelled due to just how valuable 28Gbps GDDR7 modules had become.

To add fuel to the fire, Nvidia itself quashed rumors of an RTX 50 Super series announcement at CES 2026 earlier this year. Add to that the leaked RTX 5050 with 9GB of VRAM, highlighting the sheer desperation of the moment, and any hope left was killed. An overpriced RTX 50 Super series launching in these circumstances was unlikely. So, a single churn of the rumor mill isn't enough to reignite excitement; we'll have to wait and see if the frequency of these leaks once again picks up.

When not being spotted at night markets or meeting crowds of adoring fans, the hardware industry’s biggest celebrity, Nvidia CEO Jensen Huang, spent most of his time at Computex this week making the case that computing as we know it is collapsing into one repeatable pattern built for AI agents; a blueprint that now runs across the cloud, the PC, the car, and the robot.

"There's a new computing pattern," the Nvidia CEO told reporters at a press gaggle the day after his GTC Taipei keynote, describing an agent architecture he calls a harness that orchestrates reasoning, memory, and tool use the same way whether it sits in a data center or a laptop.

He tied that claim to every product Nvidia detailed at the show, from the Vera data-center CPU now in full production to RTX Spark, its first Windows PC platform, shipping in laptops this fall.

One pattern, every machine

Huang told the room that he repeats the same keynote structure on purpose. "Every time I give you a keynote, it's like Top Gun 17, and it's exactly the same architecture," he said, "because I want you to know that the future of computing is this." The pattern begins with training and inference in the cloud and pushes outward to everything else: "Every edge device will become autonomous. Every edge device will have agentic systems."

He ran that blueprint through self-driving cars, humanoid robots, Nokia base stations, and imaging satellites, casting each as the same agent profile on different hardware. Curiously, the self-driving car got quite a bit of airtime, with Huang describing Nvidia's Alpamayo driving stack as a system that reasons in language rather than reacting to images, one that could read a "skill file" and watch a tutorial video to operate unfamiliar machinery the way a person would. "That's how autonomous vehicles are going to work in the future," he said. "It's essentially that agentic computing pattern with a physical AI model."

A CPU that generates tokens, not cores

Vera, on the data center side, is an 88-core Arm processor that Nvidia is now in full production with, pitching it as a chip built for agents rather than human users. "We built Vera for agents to use," Huang said. "Until six months ago, there were no agents, so that's the definition of a $0 billion market."

A hyperscale CPU piles on cores because humans lease them by the hundred, where an agent, Huang argued, "doesn't want to rent the CPU core, the agent wants to generate tokens." That pushed Nvidia toward single-thread speed and memory bandwidth over core count, and Huang claimed Vera offers the largest step up in single-threaded performance he has seen "in 25 years." His reasoning ties back to latency: "Humans are more patient than agents. Agents, they're working at nanosecond scale, not second scale."

Nvidia claims 1.8 times faster task completion than x86 and a 1.5 times instructions-per-clock gain over its Grace predecessor, with a 256-chip liquid-cooled Vera rack it says reaches six times the throughput of a conventional CPU rack. The chip ships on the back of nearly 2.5 million Grace units sold, and Anthropic, OpenAI, xAI, ByteDance, CoreWeave, and Oracle are named as early customers. CFO Colette Kress told investors on Nvidia's latest earnings call that the company sees "nearly $20 billion in total CPU revenue this year".

Phoronix's first public Vera benchmarks in May measured it roughly 10% ahead of AMD's 64-core EPYC 9575F and about 55% ahead of Intel's 128-core Xeon 6980P across selected Linux workloads. Nvidia ran those tests on pre-production silicon at its own headquarters, limited them to workloads it considers relevant, and, by Phoronix's account, switched off CPU power and frequency monitoring for the session.

Reinventing the PC after 40 years

As for RTX Spark, Huang says that it’s the first real rethink of the PC in four decades. "We have an opportunity after 40 years to go reinvent it for the age of AI," he said, predicting the machine shifts "from your PC being a tool to now really your PC being your system." He pushed even further: "Your laptop is going to be your R2-D2."

The top RTX Spark part, internally N1X, pairs a 20-core Arm CPU built by MediaTek (10 Cortex-X925 performance cores and 10 Cortex-A725 efficiency cores) with a Blackwell GPU carrying 6,144 CUDA cores, up to 128GB of LPDDR5X unified memory, and a 600 GB/s NVLink-C2C link, all on TSMC's 3nm node. Huang justified these specs with the same impatience he applied to Vera, arguing that an agent driving the machine won’t wait, so the software it touches, from Adobe to Blender, "cannot be slow."

The platform is launching in a market that Qualcomm had effectively dominated until its Windows on Arm exclusivity with Microsoft lapsed. Fall 2026 laptops are confirmed from Microsoft, Dell, HP, ASUS, Lenovo, and MSI, with Acer and Gigabyte to follow, and Nvidia says anti-cheat engines, including Easy Anti-Cheat and Denuvo, run natively on the chip. Asked why Nvidia would enter a low-margin business it has steered clear of for years, Huang said, "We don't really have to choose. The real question is, can we make a contribution?"

Vera's 88 cores are Nvidia's own custom Olympus design, its first ground-up server core since the Denver and Carmel projects, while RTX Spark's 20 cores are Arm's off-the-shelf Cortex reference designs licensed through MediaTek, one of them already a generation old. Huang's "same pattern everywhere" runs, at the silicon level, on two different CPUs.

When asked whether the Olympus cores would come to Windows PCs, Huang declined to commit. "Our preference is to use off-the-shelf cores whenever we can, because Arm also builds good cores," he said, adding that Olympus was pushed toward single-thread speed in a way standard many-core Arm parts weren’t: "We wanted to push single-threaded performance as far as we could push it." The first PC chip using Nvidia's own cores isn’t expected until 2028. Meanwhile, Morgan Stanley estimates Vera at around $5,000 per socket inside a vertically integrated rack.

What about memory?

DRAM contract prices have climbed sharply through 2026 as makers divert wafers to high-bandwidth memory, and Nvidia remains short of supply even as it locks in capacity, by Huang's own account: "We have enough supply for very robust growth. However, we are supply constrained."

"One of the best ways to improve memory use is to use extremely, extremely low precision," Huang said, pointing to NVFP4, Nvidia's 4-bit floating-point format that scales between four, eight, 16, and 32 bits and roughly doubles the parameters that fit in a given memory pool, the trick that lets RTX Spark hold larger models in its 128GB. He paired it with neural texture compression that cuts game texture memory by up to eight times in Nvidia's demos. At SK hynix's booth during the show, Huang signed an HBM4E wafer with the words "Please Make More."