As Apple and other American companies seek to use memory chips from China-based CXMT and YMTC amid massive supply constraints, U.S. lawmakers want to ban exports of Chinese memory chips to the U.S., citing concerns of weakening domestic and allied suppliers and indirectly supporting the development of 3D NAND and DRAM by Chinese companies, reports the Financial Times.

John Moolenaar, Republican chair of the U.S. House China Committee, and Democratic Congressman George Whitesides asked Commerce Secretary Howard Lutnick to prevent U.S. companies from purchasing semiconductors from businesses included either on the Pentagon's Chinese Military Companies blacklist or the Commerce Department's Entity List. They also called on the administration to add CXMT to the Entity List and impose additional restrictions on YMTC.

"Dependence on Chinese memory manufacturers creates an unacceptable risk for U.S. national security, economic security, and supply chain security," the letter by Moolenaar and Whitesides reads.

Apple has been seeking approval from the Trump administration to source memory from CXMT amid a severe global DRAM supply crisis caused by the rapid expansion of AI infrastructure. Corsair, Patriot Memory, and some other suppliers of branded memory modules and SSDs have been using DRAM from CXMT and 3D NAND from Yangtze Memory for some time now.

"We are alarmed that Apple and other U.S. tech companies seek to purchase memory from Chinese semiconductor manufacturers, including those with ties to the Chinese military," the U.S. lawmakers wrote.

DRAM maker CXMT is already on the Pentagon's Chinese Military Companies list, whereas 3D NAND producer YMTC is already in the DoC's Entity List. Their presence in the lists does not outright prevent American companies like Apple from buying their products, but at a significant political risk.

Technically, American companies could buy chips from CXMT and YMTC to use inside products bound for China or other countries and continue to use memory from traditional suppliers in products aimed at the U.S. market. To prevent this, Moolenaar and Whitesides also urge the American government to coordinate with Japan, South Korea, and the EU to prevent CXMT and YMTC from taking advantage of the current supply shortage to establish themselves in allied supply chains, which they believe could ultimately leave the West strategically dependent on Chinese memory.

Moolenaar and Whitesides argue that purchases from Chinese memory manufacturers could indirectly support technologies applicable to China's military.

"Leading Chinese memory manufacturers are all closely intertwined with the Chinese military; thus, every memory purchase by a U.S. company will directly subsidize the People’s Liberation Army's development of this critical dual-use technology," the letter stresses.

The lawmakers argue that CXMT and YMTC could repeat China’s playbook in solar, steel, telecom, and EV markets: use state subsidies to undercut foreign rivals, weaken their investments, and ultimately exploit the resulting dependence for strategic leverage. That said, using Chinese memory now could permanently weaken Western production capacity and leave the West strategically dependent on China for a critical component of AI infrastructure, Moolenaar and Whitesides believe.

Homegrown DDR5 memory from China, manufactured by ChangXing Memory Technologies, has been making the rounds lately as more and more vendors start legitimizing it. However, new testing from overclocker Safedisk, shared by Uniko's Hardware, purportedly shows that it actually carries inferior performance compared to similar options from SK Hynix, alongside significant variance in the silicon between different batches.

CXMT began producing DDR5 in late 2025 despite lacking any cutting-edge EUV lithography tools. Fast forward to today, and reports of the company matching Micron's memory capacity by this year are now floating around. If true, China would become the second-largest memory maker in the world. At such scale, it's no wonder that many companies in China have already started sourcing CXMT-made RAM to fill the gap in the consumer market.

Throughout 2026, we've seen motherboard manufacturers verify CXMT's DDR5 with official BIOS optimizations that allow it to run beyond 8,000 MT/s at this point. OEMs such as Dell and HP are using CXMT RAM in their region-bound systems, and even proper PC hardware companies like Corsair are using CXMT modules. Lexar, Kingbank, Netac, Asgard, Gloaway and more are also producing retail DDR5 kits with CXMT chips.

As such, the testing features a Kingbank 48GB (2x24) DDR5-6000 kit running at CL36 and found several weaknesses despite successfully achieving an 8,600 MT/s overclock at CL44. The first revelation is that CXMT modules don't scale with voltage, meaning you can't just increase voltage in hopes of achieving higher clocks. CXMT's DDR5 apparently doesn't respond well to tuning sub-timings either, forcing you to remain stuck with baseline CAS latency (or higher, like in this case).

Different batches of CXMT-equipped memory perform differently, too, so silicon lottery plays a much bigger role than it would with other vendors. Speaking of which, SK Hynix-made DDR5 modules allegedly performed better at identical clock speeds, while CXMT's modules were less susceptible to overclocking in general. We didn't get any comparative benchmarks for any metric, so take these claims with a grain of salt.

Overall, if the testing is to be believed, it serves as counterprogramming against the popular narrative forming around China as the savior of consumer interests. CXMT's strength lies in the fact that it doesn't have to cater to opulent AI clients as much as the Big Three, which reduces opportunity cost, allowing CXMT to produce more DDR5 memory. That doesn't mean it would be cheaper, though, or at least no evidence has suggested that so far.

CXMT has remained limited to the Chinese region for now, and breaking through to the Western market would mean impressing a lot of skeptics. Not only would pricing play a big factor, but the reliability of a new DRAM manufacturer would raise serious concerns. Stories like these certainly don't help, but with CXMT's IPO on the way, it's only a matter of time before it becomes a serious mainstream contender.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

SK Hynix CEO Kwak Noh-jung says that 2027 will be the "worst year" for the ongoing memory shortage in comments shared with Reuters. The remark comes on the heels of SK Hynix successfully marking the largest-ever IPO for a foreign company on the U.S. stock market, raising $26.5 billion. Although Kwak points to next year being the worst for RAM shortages, the executive expects the memory crunch to last until 2030.

"We forecast that next year will be the worst year in the industry's history from the supply perspective," Kwan told Reuters. "We still forecast that customer demand will remain higher than our ​supply capacity even beyond 2030. But we are doing our best to solve the problem."

In March, SK Group chairman Chey Tae-won also suggested shortages would last until 2030, and the company has previously pointed to 2027 as a key shortage point, alongside Samsung. DRAM demand is largely driven by the HBM used in AI accelerators, which require far more sophisticated manufacturing and packaging processes compared to consumer DDR5. On top of advanced manufacturing, HBM also consumes more wafer capacity than DDR5, forcing major memory brands to reallocate supply and double down on an already sticky supply situation.

Forecasts like this are tricky. It's in SK Hynix's financial interest for memory shortages to continue, even well beyond 2030. SK Hynix has set a record for quarter-over-quarter revenue, and rival Micron has seen its stock value increase 213% this year, pushing its share price to around $990.

However, Kwan's remarks aren't just a bid to rally behind SK Hynix stock. Over the past few months, we've seen Micron and SK Hynix ink long-term supply agreements (LTAs). These agreements commit supply over multiple years to particular companies and define a price floor and ceiling during the agreement term. Although LTAs don't directly influence market prices, they secure demand, and we've seen a lot of LTAs over the past several months to bind DRAM supply.

Although memory (and NAND) prices will remain elevated for at least the next several months, we've seen some signs of the market cooling. Earlier this month, a TrendForce report showed DRAM contract prices up 15% to 18% quarter over quarter for Q3 2026. That's a large increase, but far lower than the QoQ increases we've seen previously.

We're nearing some semblance of stability in the memory market, just stability at vastly elevated prices. How long that lasts is anyone's guess. Although memory brands like SK Hynix have visibility into market trends, those can rapidly change. Just this year, we've seen a massive pivot toward AI spending going toward CPUs, pushing Intel's stock to record highs while shedding around $1 trillion in Nvidia's market cap; a year ago, that would've been almost impossible to predict.

Researchers in Korea and Japan have presented two separate memory-integration proposals that aim to increase HBM (High-Bandwidth Memory) capacity and bandwidth without trapping more heat inside ever-taller DRAM (Dynamic Random Access Memory) stacks, one of the most pressing challenges facing future AI accelerators. Presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits held in June, the two approaches — V-Die from a Korean research collaboration and MOSAIC from a University of Tokyo-led group — both explore the same broad idea of standing DRAM memory dies on their edges instead of stacking the memory dies only upward like conventional HBM.

The Korean proposal, called Vertical-Die (V-Die), was presented by researchers at the Ulsan National Institute of Science and Technology (UNIST). The design rotates custom DRAM dies upright, drops through-silicon vias to free die area for more memory cells, gives each die its own bottom-edge I/O, and runs liquid-cooling channels between adjacent dies. In simulations against an HBM4 system at equal capacity, the V-Die system reportedly achieved 540 tokens per second on a GPT-3-sized workload, compared to 296 tokens per second for HBM4.

The Japanese project, MOSAIC, takes a similar “sideways stack” idea but focuses on the practical difficulty of connecting so many vertical dies to a GPU or package substrate. Presented by University of Tokyo researchers, the MOSAIC work uses orthogonal die stacking and a contactless die-to-die interface, in which data is transferred through tiny inductive coils rather than requiring every signal pad to land perfectly on a physical contact. The researchers say the prototype interface achieved up to 4 Gbps per channel, while the memory structure could double HBM4-class capacity in a DRAM-on-GPU configuration.

Both projects aim to solve the growing problem of AI chips being held back by memory. Modern accelerators can perform enormous amounts of computation, but large, powerful models depend on moving huge amounts of data between memory and compute. This is why HBM has become one of the defining technologies of modern AI hardware.

The technology addresses the memory wall by stacking multiple DRAM dies vertically on a base die and placing that stack very close to the processor. Nvidia's Blackwell Ultra B300, for instance, carries up to 288GB of HBM3E memory, without which much of the silicon would sit idle waiting for data. The dies are connected via through-silicon vias (TSVs) — tiny vertical channels etched through the silicon and filled with metal.

The stack then communicates with the GPU over an extremely wide interface, often routed through a silicon interposer or an advanced package. This is the core reason HBM can deliver terabytes per second of bandwidth: it uses a very wide, very short data path instead of sending memory traffic across a motherboard, as with conventional DIMMs (Dual In-line Memory Modules), physical sticks of RAM used in computers.

However, that same structure creates several problems. While taller stacks add more capacity, they also make it harder to remove heat. Heat generated in the lower dies and at the high-speed interface must pass through layers of silicon, bonding materials, underfill, and package structures before it reaches a heat spreader. Furthermore, TSVs consume die area that could otherwise be used for memory cells, and as bandwidth rises, more routing and I/O place additional pressure on both signal integrity and packaging costs.

HBM4, the latest generation of HBM, addresses a number of these challenges. Meanwhile, companies such as SK hynix, Samsung, and Micron are racing to improve speed, capacity, base-die performance, and thermal management. SK hynix has already shown iHBM, which embeds cooling elements into the HBM interface area, and Samsung has shown an HBM5 mockup with Heat Path Block cooling to more directly extract heat from the stack. However, they all retain the same upward stacking structure.

This convention is what V-Die and MOSAIC are challenging. By standing DRAM dies upright, the researchers expose far more silicon surface area to the cooling path. In theory, this turns the memory stack into something closer to a heat-sink fin array, where heat can move laterally and escape more directly instead of being trapped in the middle of a thick vertical pile. It also opens the door to new connection schemes along the bottom or side of each die, rather than forcing every die to communicate through TSVs running vertically through the stack.

For V-Die, the key shift is removing TSVs from the memory dies and replacing them with bottom-edge connections. Each DRAM die gets its own I/O along the bottom edge and connects directly to the substrate, with links reportedly spaced every 20 microns. The team says this layout gives four times as many connections as HBM4 and cuts memory read time by 37%, although some signals must travel farther across the package to reach the processor.

Cooling is the other half of the V-Die argument. The proposal places microfluidic cooling channels between adjacent upright DRAM dies, allowing coolant to dissipate heat closer to its source. According to the researchers, this could keep the stack around 45°C, far below the 80°C-plus range associated with dense HBM systems. In a simulated 16-die stack matched to H100-class hardware on a GPT-3-scale model, V-Die hit 540 tokens per second, compared to HBM4's 296, and cut first-token latency by 32%, or about 24 milliseconds.

MOSAIC, meanwhile, is focused on making the sideways stack manufacturable. Because the dies are assembled flat and then turned on edge, even a few microns of die-thickness variation across dozens of dies can add up to an alignment miss where the signal pads no longer land. The Japanese team’s answer is a contactless interface based on inductive coupling. One side of the memory die carries oblong coils, while a corresponding set of coils sits on the substrate or mating chip. Current in one coil induces a signal in the other, allowing data to cross the small gap without a direct metal-to-metal signal contact. This eliminates the need for precise overlapping, giving the package greater tolerance for assembly variation. Power, which requires fewer, larger connections than data, can still be supplied via physical contacts on the sides of the memory cube.

The VLSI MOSAIC prototype achieved up to 4 Gbps per channel and demonstrated TSV-free 3D integration for a memory-on-GPU layout. The team says the approach can enable twice the memory capacity of HBM4 without significantly increasing peak temperature. A related bump-MOSAIC hardware demonstration at ECTC used 100-micron-pitch microbumps, achieved stacking alignment within 6 microns as verified by X-ray CT, and showed a configuration with three times the thermal conductivity of conventional stacking while adding up to 30% more memory capacity.

While the results look promising, neither V-Die nor MOSAIC is close to replacing commercial HBM. Neither is close to shipping. V-Die is still a proposed architecture, with a prototype in the works to validate its thermal and electrical behavior; MOSAIC has proof-of-principle hardware, but the researchers have yet to show it scales to commercial DRAM capacity, yield, cost, and reliability.

Still, any viable solution to the multifaceted AI memory problem is a welcome development. SoftBank and Intel’s Z-Angle Memory (ZAM) and NEO Semiconductor’s 3D X-DRAM — both still in development — aim to solve the constraints of conventional memory. Meanwhile, the overall market is already feeling the squeeze on price and availability, even as memory makers divert capacity toward the more lucrative AI HBM and server products, driving consumer RAM prices even higher.

After announcing it last month, the first AMD EXPO Ultra Low Latency (ULL) memory kits are finally available; and with up to an 80% jump over already inflated RAM prices in tow. HardwareLuxx was able to snag a kit of G.Skill's new Trident Z5 NeoX RGB memory to see how ULL performs, and the results don't quite justify the extra cost. At most, the publication found just a 4% improvement compared to non-ULL kits.

That aligns with AMD's original claims about ULL. When the company announced the initiative last month, it also cited a 4% improvement over standard EXPO. However, AMD claims that ULL offers a 4% improvement on average, while HardwareLuxx only found that large of an improvement in a single game: F1 25. AMD reached out following publication and noted that its 4% average was across a wide variety of titles, and that there are inconsistences between each game, with some titles showing little to no benefit.

HardwareLuxx tested a 2 x 16GB kit at 6,000 MT/s with primary timings at 36-36-36-76. Compared to standard EXPO/XMP DIMMs, a lot of the optimization with ULL DIMMs comes from tuning the subtimings. The primary timings are largely the same as what you'll find on a standard EXPO kit, short of tWR (write recovery), which is lower on the EXPO ULL kit. Better binning of the memory ICs allows for more aggressive subtiming optimization, as HardwareLuxx notes, rather than relying on timings primarily concerned with stability.

In games, the ULL kit showed clear performance improvements, no matter how minor they were. In F1 25, the ULL kit outclassed a DDR5-6000 CL26-36-36-96 kit by 4.2%, and beat out JEDEC standards at 5600 MT/s by nearly 14%. Similarly, in Cyberpunk 2077, the ULL kit was around 3.7% faster than the standard EXPO kit, and 12.7% faster than JEDEC standards. The outlet also tested Arc Raiders, Baldur's Gate 3, and Counter-Strike 2; however, the ULL kit didn't offer a meaningful performance improvement in any of these titles.

The outlet also tested 7-Zip, though with only minor differences between ULL and non-ULL memory. The most interesting results are from the microbenchmarks available in AIDA64, which HardwareLuxx also ran. ULL showed largely similar copy and read throughput, but write throughput was 9.4% higher with ULL compared to stock EXPO.

Although there's a performance benefit, it's minor, and HardwareLuxx notes that "manual tuning still allows for the maximum possible optimization."

The particular kit that HardwareLuxx tested doesn't have the extreme ULL price increases we've seen elsewhere. It's currently available for sale for $530, which is only $20 more than a kit of G.Skill's Trident Z5 Neo RGB memory at DDR5-6000 CL36. It's actually gone down in price (it was originally listed at $550), while kits with more aggressive timings have increased in price.

The NeoX DDR5-6000 CL26 kit, for example, has jumped up $50 to $1,150 — yes, that's for a 2 x 16 GB kit still — while the CL28 kit has jumped up to $1,030 (a $30 price increase). Two weeks ago, we saw non-ULL kits selling at $560 and $700 for CL28 and CL26, respectively, creating a large delta in price between ULL and non-ULL kits. Now, those kits are selling for $700 and $900, respectively.

The introduction of ULL couldn't have come at a worse time, as the ongoing DRAM shortage continues to raise the cost of building a PC around the world. Adding a premium on top of those already inflated prices is tough to justify, even if that premium is modest — especially for mainstream CL36 and CL30 kits, the "ULL tax" is essentially null. The good news is that you can largely achieve what ULL offers on your own, at least given that you have the patience to sit through tuning your memory for single-digit gains.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

ChangXin Memory Technologies, or CXMT, has just received official validation from MSI for its high-speed DDR5 memory modules. The manufacturer has released new beta BIOSes across its AM5 lineup, unlocking stable frequencies up to 8,200 MT/s for 3GB CXMT chips on dual-DIMM motherboards. Previously, RAM using these modules was limited to around 6,800 MT/s despite the hardware itself being capable of much more.

The test BIOS comes from MSI China — there's no announcement on global channels for some reason, and it's only available for select motherboards at the moment. MSI tested region-bound retail kits from Lexar and KingBank on boards with both two slots and four slots, but we only have screenshots for the former, courtesy of Videocardz.

One test was conducted using 24GB sticks (2x24) on the MEG X870E Unify model and a Ryzen 7 9700X CPU. This was mostly a standard kit since it came with a 6,000 MT/s EXPO profile. The other config consisted of 16GB sticks (2x16) with an EXPO profile already running at 7,200 MT/s, so it was somewhat cherry-picked silicon, paired with a Ryzen 5 9600X on a MAG B850 MPower motherboard.

The results showed that on dual-DIMM motherboards, 24Gbit (3GB) modules from CXMT were able to clock up to 8,200 MT/s, passing MemTest with 101% coverage. Conversely, 16Gbit (2GB) chips were also stable at 8,000 MT/s on the same test bench with 101% coverage. Moving over to quad-DIMM, the patch notes for the BIOS say they've "also been raised to DDR5-7200," where the limit was stuck at 6,800 MT/s prior.

This is not the first time MSI has optimized Chinese RAM for some of its motherboards. Earlier this year, the company did the same thing for Intel's 800-series models in China. Anyway, these specific BIOSes are meant for the AM5 socket and they're based on existing stable releases — just patched with unlocked memory overclocking features. More motherboards should be supported soon, but for now you can check out the MSI China's community release channel if you want to try one yourself.

Memory prices will keep climbing through the third quarter of 2026, but the blistering increases of the past few quarters are set to cool as consumer buyers reach the ceiling of what they can afford, according to a detailed TrendForce report. The research firm's latest memory pricing survey projects conventional DRAM contract prices to rise 13% to 18% quarter-over-quarter (QoQ) in Q3 2026, with NAND Flash contract prices increasing 10% to 15%; substantial gains, but a marked slowdown from the roughly 60% jumps recorded in the second quarter.

According to the report, the cooldown is driven by consumer electronics manufacturers' unwillingness and inability to absorb higher memory costs after months of relentless price increases, rather than by improved supply. In other words, memory remains in short supply, but consumers are no longer willing to keep paying ever-higher prices.

AI continues to be the market's driving force. Demand for AI inference systems and hyperscale data centers remains strong enough to keep both DRAM and NAND supply constrained, while memory manufacturers continue shifting production capacity toward higher-margin server products. This leaves less capacity available for consumer memory, preventing prices from falling even as demand from PCs and smartphones weakens.

As a result, the memory market is increasingly split between enterprise and consumer customers. On the server side, TrendForce expects demand to remain healthy through 2027 as improving CPU availability supports continued deployments of AI servers built around x86 processors and registered DIMMs (RDIMMs). Although server DRAM is expected to remain undersupplied during the third quarter, price increases should moderate because a portion of purchases is covered by long-term supply agreements.

Consumer markets appear to paint a very different picture. Notebook manufacturers are expected to keep replenishing inventories, but higher memory costs are gradually feeding through into retail pricing, a trend TrendForce believes could weigh on PC shipments for the rest of the year. Smartphone vendors face similar pressure, with many expected to raise handset prices to offset persistently high LPDRAM (low-power DRAM) costs while simultaneously becoming more cautious with production plans as consumer demand softens.

The same pattern is beginning to emerge across storage products. PC manufacturers accumulated substantial client SSD inventories during the first half of 2026, reducing their willingness to accept another round of price increases. Suppliers have responded by taking a more flexible approach during contract negotiations, helping to moderate SSD pricing even as enterprise storage continues to benefit from AI infrastructure spending.

Not every segment is seeing the same level of demand. TrendForce notes that NVIDIA's RTX PRO 6000 Blackwell has yet to generate the expected wave of GDDR7 demand, while weaker notebook shipments have also softened demand for graphics memory. At the opposite end of the market, retail products such as USB flash drives and memory cards remain sluggish as higher upstream costs become increasingly difficult to pass on to consumers.

For PC builders, the report suggests that meaningful price relief is still some way off. Memory prices are continuing to rise because AI infrastructure remains the industry's top priority. However, the pace of those increases is slowing as consumer demand reaches its breaking point.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

The price of DDR5 memory is setting new highs these days as demand badly outstrips supply. In a bid to save money, Meta is recovering legacy DDR4 memory from used servers and is installing it into new machines using its in-house developed Vistara ASIC that enables it to connect old memory modules to its latest servers running AMD EPYC 'Turin' processors that only support DDR5 memory.

Interestingly, Meta is not the only company developing such a solution. Panmnesia, a startup from South Korea, has developed an off-the-shelf CXL controller and switch that enables servers to attach considerably larger memory pools without extending latency, which differentiates Panmnesia’s solution from competing CXL offerings.

Custom ASIC enables DDR4 memory to work with new servers

Vistara is Meta’s first-gen custom CXL memory expander ASIC designed to attach outdated DDR4 memory to modern servers. The chip implements a CXL 2.0 Type-3 memory expander over a PCIe 5.0 x16 interface and bridges standard DDR4 RDIMMs to host processors. Each ASIC supports two independent 72-bit DDR4 memory channels and can provide up to 256 GB of capacity using 64 GB DIMMs. At present, Meta deploys 128 GB per ASIC using 32 GB DDR4 modules recovered from decommissioned servers.

Meta deploys Vistara in its MemServer platform, where two ASICs connect to a single 158-core AMD Turin processor over PCIe 5.0 x8 links. Each server combines 768 GB of DDR5-6400 local memory with 256 GB of CXL-attached DDR4-2400, which expands memory capacity to 1 TB. The software stack transparently exposes CXL memory as a separate NUMA node and enables Linux to migrate cold pages to the slower DDR4 tier (with 76 GB/s of bandwidth) and retain frequently accessed data in local DDR5 (with 614 GB/s of bandwidth).

The ASIC is based on three RISC-V processor cores for secure boot, device initialization, firmware management, and health monitoring. Meta claims it has optimized its CXL controller and memory pipeline to reduce protocol overhead, minimize queuing delays, and lower idle round-trip latency to around 50ns. The chip also incorporates advanced reliability features, including Reed-Solomon two-symbol error correction and x4 chip-kill support.

Not only Meta's Vistara

Meta is not the only company that wants to attach legacy DDR4 memory to newer servers that rely on DDR5 memory and save some money. While Vistara is available exclusively to Meta, there is a new CXL expander solution from Panmnesia that will be available to other companies.

"There has been a perception that putting a switch between the CPU and devices makes it hard to meet the memory-access latency these systems expect, so directly attached multi-headed devices (MHDs) stayed the norm even though they were harder to scale," said Myoungsoo Jung, chief executive of Panmnesia. "Our work shows this is not an inherent limit of CXL or CXL switches — it is a trait of early-stage CXL, and one that fades as the standard and the products around it mature. With a fabric switch that carries our next-stage CXL controller, scalability, low latency, and stable performance can come together."

CXL is a protocol that sits on top of the PCIe physical interface. As a result of this, many early CXL implementations were built by modifying existing PCIe IP, which is why such implementations inherited architectural characteristics optimized for PCIe rather than for memory-semantic communications, which added substantial latency, according to Panmnesia. By contrast, its new CXL controller IP features a redesigned data path that replaces separate per-layer buffers with shared buffers to eliminate much of the synchronization overhead. In addition, it features additional latency optimizations throughout the protocol stack that offset the additional hop introduced by the switch.

The accompanying CXL fabric switch introduces Port-Based Routing (PBR), which removes the tree-topology limitations of conventional Hierarchy-Based Routing (HBR) used by PCIe and early CXL implementations. The fabric switch still supports both PBR and HBR to enable flexible system topologies, optimized traffic routing, and stable performance. In practice, it enables companies like Meta to install more DDR4 memory into their modern servers without major performance degradation because of high latency.

Panmnesia claims that while early CXL deployments could connect only a handful of compute nodes to shared memory pools, its fabric scales to up to 64 nodes, which means greater flexibility for hyperscalers that tend to run thousands of servers, but which now have to rationalize usage of expensive DRAM.

Panmnesia says its next-generation CXL technologies are progressing toward commercialization. The company has pre-release silicon for its PCIe 6.4/CXL 3.2 Fusion Switch and has completed development of its PCIe 7.0/CXL 4.0 Combo IP, which supports the latest features introduced by the CXL 4.0 specification.

Edit 07/02/2026 1:00 am ET: Corrected the DRAM voltages and pricing with new information provided by G.Skill.

G.Skill’s AMD EXPO ULL (Ultra Low Latency) memory kits, strong contenders among today's best RAM options, have arrived on the retail market. While AMD previously stated that EXPO ULL memory kits would be “effectively the same price” as vanilla EXPO memory kits, this has proven by far not to be the case. In reality, these new EXPO ULL kits carry a substantial premium that can scale up to 80% over their regular counterparts, according to the latest Newegg listings.

The Trident Z5 NeoX is G.Skill’s latest memory series featuring ULL optimizations. The new lineup is available in three striking color options, black, glossy black, and white, that cater to a variety of system aesthetics. G.Skill has not released the official product pages for the Trident Z5 NeoX series, so detailed information on the full range of planned capacities and speeds is unavailable. Newegg is currently selling the Trident Z5 NeoX memory kits in a 32GB (2x16GB) dual-channel configuration clocked at DDR5-6000.

To make it a meaningful comparison, we compared the Trident Z5 NeoX memory kits to their direct counterparts, the standard Trident Z5 Neo series. We deliberately excluded similarly specced lineups such as the Aegis or Ripjaws series, which are tailored for budget-conscious buyers, as well as omitting the Trident Z5 Royal Neo, which targets a more posh crowd.

According to G.Skill, the EXPO ULL memory kits share similar pricing to the non-ULL counterparts. However, there may be a price difference between ULL memory kits and regular memory kits in stores. The reason is that some retailers likely still have older inventory that was bought at a lower cost. They may try to balance the prices of new and old stock, resulting in the price gap. This may occur specifically when prices are on the rise.

According to Newegg, the Trident Z5 NeoX DDR5-6000 C26 memory kit presently carries a 57% premium over the standard Trident Z5 Neo DDR5-6000 C26 memory kit. The price gap widens further for the DDR5-6000 C28 variant, which commands a 79% premium. Meanwhile, the Trident Z5 NeoX C30 and C36 versions are 14% and 9% more expensive than their regular Trident Z5 Neo counterparts, respectively.

On a superficial level, it’s basically impossible to grasp the true extent of the level of optimization that goes into AMD EXPO ULL memory kits just by looking at product listings. It’s customary for memory manufacturers and retailers to only list the four primary memory timings: CAS Latency (CL), Row Address to Column Delay (tRCD), Row Precharge Time (tRP), and Row Active Time (tRAS). Unfortunately, these memory timings only tell part of the story, since most of the secondary timings for AMD EXPO ULL certification, including Refresh Interval (tREFI), Row-to-Row Delay Short (tRRDS), and Write Recovery Time (tWR), are not publicly visible.

Returning to the example of the Trident Z5 NeoX memory kits, what immediately stands out is the dramatically reduced tRAS value, which is up to 67% lower than that of standard Trident Z5 Neo memory kits. In short, tRAS dictates how many clock cycles must pass after a row opens before the memory controller can close it. The reason for high tRAS values in DDR5 resides in the architecture itself. Unlike DDR4, which operates with a single 64-bit channel, DDR5 employs two independent 32-bit subchannels. This change, alongside the doubling of burst length from BL8 to BL16, enables each memory command to transfer twice as much data through the channels in a single operation. As a result, the memory rows remain open longer, leading to the higher tRAS values typically seen in DDR5 modules. What makes the AMD EXPO ULL memory kits unique is that they drive tRAS values back down to levels reminiscent of high-performance DDR4 from the old days.

Another significant advantage of AMD EXPO ULL memory kits is their ability to maintain tight timings at the same voltages. Lower DRAM voltages translate to lower power consumption, lower operating temperatures, and more headroom for overclocking.

If you’re looking for the simplest explanation as to why AMD EXPO ULL memory kits carry a hefty premium over regular AMD EXPO memory kits, it boils down to the extensive optimization and meticulous binning process involved in their production. Memory vendors spend more time testing and sorting memory chips that can operate at the tightest timings and lowest voltages. It’s a very time-consuming and labor-intensive process. As a result, the overall manufacturing costs for EXPO ULL kits are higher than for standard kits. In many ways, you aren’t just paying a premium for the hardware itself, but also for the vendor’s time and the guarantee that the memory modules run at near-maximum potential right out of the box.

Hardware enthusiasts, server administrators, and all regular readers of this site will be well aware of the ongoing "RAMpocalypse," the memory and storage shortage affecting nearly every market and raising prices across the board in the tech sector. If you were hoping for relief, don't hold your breath; at the International Supercomputing Conference this past week, Lenovo reportedly said "it will never be like it was last year." Underlining the point, one of Lenovo's presentation slides was titled "The 5 Step RAMaggeddon Survival Guide."

That comes to us by way of our German friends over at ComputerBase, who note that "never" was said with a smirk, thus implying that it wasn't meant to be taken literally. Instead, the message from Lenovo is that memory prices were unusually low in early 2025, and it will be a long time before we see comparatively low prices on RAM, flash memory, and other components, as the #1 worldwide PC OEM expects AI demand to continue growing.

According to ComputerBase's report from ISC 2026, Lenovo's broader message is that the economics of the memory industry have fundamentally changed. The company reportedly argued that even as significant new manufacturing capacity comes online beginning around 2028, demand from AI infrastructure is expected to absorb much of that additional output, preventing DRAM and NAND prices from returning to the lows seen over the past two years.

The report points to SK hynix's recently announced plans to triple its memory production capacity by 2034 as supporting evidence. Lenovo's reasoning is straightforward: the notoriously profit-hungry memory manufacturers would be unlikely to invest so heavily in expanding production if they expected a return to the razor-thin margins and oversupply that characterized parts of the market in early 2025.

In case you needed extra evidence for its argument, Lenovo also suggested that memory capacity itself is becoming an increasingly important consideration when designing and purchasing servers. While vendors have traditionally advertised the maximum supported memory capacity of new platforms, actually populating those DIMM slots has become far more expensive. New dual-socket servers are on the way next year with 16 memory channels per processor, meaning that even a relatively modest configuration can require around 1 TB of installed memory to fully utilize the available bandwidth.

Lenovo is far from the only company predicting a prolonged memory crunch, although the industry's incentives are worth keeping in mind. Micron recently told investors it expects supply to remain constrained through at least 2027, with only gradual improvement beginning in 2028, while SK hynix has warned the shortage could persist until around 2030 as AI infrastructure continues absorbing wafer capacity. Those forecasts are backed by multi-year supply agreements worth roughly $100 billion that Micron has already signed with customers, underscoring how seriously hyperscalers are treating long-term memory availability.

Even companies that traditionally wield enormous purchasing power are feeling the squeeze. Apple reportedly has sought permission from the U.S. government to source DRAM from Chinese memory maker CXMT, a Pentagon-blacklisted company, illustrating just how valuable additional memory supply has become as prices continue to climb. At the same time, memory vendors are enjoying some of the strongest pricing power (and profit margins) they've seen in years, giving them little incentive to accelerate a return to the boom-and-bust pricing cycles that once defined the DRAM market.

Ironically, one consequence of the ongoing memory shortage is that HBM is becoming more economically attractive relative to conventional system memory. DRAM manufacturers have redirected significant production capacity toward higher-margin HBM for AI accelerators, reducing the supply of commodity DDR5 and LPDDR5 while demand for both remains elevated. As a result, the premium for HBM-backed computing has narrowed, not because HBM has become inexpensive, but because traditional system memory has become dramatically more expensive. Hyperscalers were going to buy the GPUs anyway, so maximizing their utilization to reduce DDR5 requirements suddenly becomes an attractive proposition.

That shift helps explain Lenovo's suggestion that GPU-accelerated computing may now make more financial sense for some workloads. If an application can keep much of its working set in GPU-attached HBM, it may require significantly less DDR5 installed in the host system. With system DRAM now representing a much larger share of overall server cost than it did just a year ago, reducing memory capacity requirements can materially lower the price of deploying large-scale infrastructure.

Obviously, we don't know whether Lenovo's long-term outlook will prove accurate, but memory pricing has historically been cyclical, with periods of oversupply often followed by sharp corrections. With hyperscalers continuing to pour billions into AI infrastructure and memory vendors increasingly prioritizing high-margin enterprise products, the company believes the unusually inexpensive DRAM and NAND prices of 2024 and early 2025 may prove to have been an anomaly.

The RAMpocalypse is hitting enthusiasts hard. We recently reported on the crisis seeping down to affect supplies of the decades-old DDR2 gen RAM. So it comes as no huge surprise that a well-known tech tinkerer has been inspired to look at the viability of Windows 11 on an even more ancient DDR1 platform. Step forward Omores, who demonstrates Microsoft’s newest OS running on a Core 2 Quad Q6600, using a DDR1 motherboard, supported by an ATI Radeon HD 4650 AGP graphics card. “The best part,” says our hacky hero. “It’s completely stable.”

Windows 11 on a DDR1 motherboard, with AGP support enabled from r/windows

DDR1 first became available to PC builders and DIYers at the turn of the century, replacing the aging SDR SDRAM. The DDR1 rollout began with data rates like DDR-200 and DDR-266, being the preferred choice over older platforms featuring PC100 or PC133 SDRAM. We don’t know the rated speed of the DDR1 sticks Omores used, as it isn’t shown, but DDR-400 was the best official non-overclocked standard (a couple of years later). It would make sense to use the best memory on a cherry-picked older system like this.

Other key components of this age-defying Windows 11 PC build include an ASRock ConRoe 865PE motherboard. This is regarded as something of a legendary board as it bridged generations and allowed folks to use the latest Core 2 Duo and Core 2 Quad chips from Intel while keeping their DDR1 RAM and AGP graphics cards. It isn’t only today that PC DIYers have cared deeply about component longevity.

The last significant component in this DDR1 system that we were told about was the ATI Radeon HD 4650 AGP graphics card. This seems to have required the most wrangling to make it work with Windows 11 / modern software. However, Omores reveals that “With some 'hacking' ... AGP 8X is fully functional and H.264 hardware decoding is active.” The key was finding, then crowbarring, ATI’s Windows 7 64-bit drivers from 2012 onto the system.

Once some details of the setup were confirmed in the video using tools like CPU-Z and GPU-Z, Omores showed the ‘fresh’ Windows 11 DDR1 system running modern browsers, with embedded video and hardware decoding. A handful of games and 3D benchmarks were also shown running without glitches. Last but not least, the system did indeed run Crysis.

In a later comment on the Reddit post, Omores elaborates on how to install the ATi driver on Windows 11 and shares a more detailed video link. “I like that Windows 11 is rock stable on these older systems with no UEFI whatsoever and only ACPI 1.1,” adds the adventurer in older PC tech. “A lesser-known fact is that Windows 11 actually officially supports BIOS systems via Windows 11 IoT, so it's kind of expected to run smoothly.”

Apple has made the unprecedented decision to hike the prices of all its current computers and tablets. iPhone prices remain as they were, for now. Bloomberg indicates that the rather steep price rises have been precipitated by increased costs of memory and storage. One of the most impactful hikes we see is the entry-level MacBook Pro going from $1,699 to $1,999. However, even the recently released but resource-starved MacBook Neo has had another $100 piled onto its price, so now it starts at $699 before tax.

In addition to Gurman’s highlighted price increases, we spotted that the cheapest Mac Studio M4 Max (mini PC desktop) has had its price increased to $2,499 from $1,999. There’s a lot to take in, so check out our at-a-glance before and after table for quick reference.

Bloomberg’s resident Apple expert, Mark Gurman, quoted an apologetic company rep. “We know this is not welcome news, and we are working tirelessly to find solutions,” a spokesperson from Apple told the reporter. Other interesting assertions from that conversation were that Apple had never seen component prices rise so high, so quickly. Moreover, its representative claimed that the firm did all it could to shield customers from any knock-on device price rises, stating the company had "shielded our customers from these increases so far, but we have now reached a point where we need to begin raising prices on a number of products including today’s increases for iPad and Mac."

While newsrooms might be agog at these price rises being implemented today, the writing has been on the wall of the RAMpocalypse for several months. Back in April, Tim Cook publicly forecast that the component shortages and price rises didn’t appear to be going anywhere soon. That statement came in the wake of the withdrawal of the entry-level $599 configuration of the Mac Mini, and Apple softening the blow of higher prices of its latest MacBook Air and MacBook Pro models by upgrading memory and other tech specs.

Until now, it seemed like Apple’s massive buying power and vertical integration had managed to help it hold off computer and tablet price increases. Today, the brakes came off, pretty dramatically.

In a world where memory is no longer a commodity but a strategically valuable asset, customers are eager to sign long-term supply agreements (LTAs) with their suppliers to ensure a steady supply of 3D NAND and/or DRAM. Micron this week announced that it had signed 16 strategic customer agreements (SCAs), 14 of which are worth around $100 billion. Furthermore, the company expects to receive cash deposits and other commitments worth $22 billion, but has warned there is no foreseeable end in sight to the RAM crisis driving up PC component prices.

“14 of the 16 SCAs that we have signed have a cumulative revenue at minimum price per our contracts of approximately $100 billion over the remaining agreement term,” a statement by Micron reads. “Under the SCAs we have signed so far, we project to receive cash deposits and related financial commitments of $22 billion.”

Based on Micron’s claims, the company has about $100 billion of guaranteed baseline revenue already locked in under 14 of those 16 strategic customer agreements, assuming customers only buy the minimum committed volumes and only pay the minimum contract price. In reality, Micron can earn more if customers buy higher volumes or pay higher prices. Furthermore, Micron expects customers who signed these long-term SCAs to put up real money up front — or make equivalent binding financial commitments — as part of reserving future memory supply.

Micron claims it has signed strategic customer agreements with four 'very large customers' and three 'medium-sized customers,' which means that the contracts were inked with clients that previously did not commit to LTAs. The contracts are signed with a five-year term (except the automotive LTAs, which have a term of three years), from calendar 2026 to calendar 2030.

Micron claims that memory supply will be insufficient in 2027 and may improve gradually only in 2028. To that end, it is not surprising that its clients are willing to sign LTAs for 3D NAND and DRAM to ensure that they have enough memory for their products.

"With respect to supply, our customers are recognizing that supply shortages in memory and storage will take considerable time to improve," said Sanjay Mehrotra, chief executive of Micron, in prepared remarks. "Even as we expect industry supply to improve gradually in 2028, we currently do not have line of sight as to when memory supply will be able to catch up with increasing demand."

Normally, Micron and other memory producers inked LTAs with select clients only (read: with Apple, Nvidia). 16 LTAs is a lot for this kind of arrangement, and this looks like a business model shift for the company. It is noteworthy that the 16 signed contracts represent roughly 20% of Micron's DRAM volume and 33% of the company's NAND volume over the period through 2030. That said, Micron may sign more LTAs with more companies.

Valve has confirmed that the first batch of Steam Machines will only come with a single stick of 16GB RAM, limiting the device to single-channel memory. The company confirmed this in a correction to Gamers Nexus (GN), after its engineers initially said that Steam Machines could either come with a single 16GB stick or two 8GB sticks. “We misspoke here,” Valve wrote in its email to the media channel. “All units will actually have one 16GB stick of RAM.”

Tests have shown that using single-channel memory can reduce performance by about 9% to 13% compared to dual-channel memory, meaning gamers will feel the difference, especially in 1% lows. This is especially hard on the Steam Machine, which uses already aging hardware — a semi-custom AMD Zen 4 CPU and RDNA3 graphics with only 8GB of GDDR6 VRAM. Note that AMD launched Zen 5 in 2024, while the RDNA4 GPUs dropped in early 2025. We also already have details for Zen 6 CPUs and have heard rumors that RDNA5 GPUs will arrive next year.

However, the company probably made this decision to keep the costs for the Steam Machine as low as possible. The device’s $1,049 base price is already steeper than what many are willing to pay for — an estimated $300+ price increase from the $700 to $750 target price that Valve presumably targeted. While its engineers did not confirm these numbers, they also said that the Steam Machine would have gotten a “probably similar” price hike to the one the Steam Deck experienced recently. Nevertheless, there is hope that later batches will have dual-channel memory, with Valve telling GN that there is a chance of this happening in the future.

This is another blow to the much-awaited living room PC console that is supposed to finally give PC gamers a chance to enjoy their Steam library with a console-like experience. Valve originally announced the Steam Machine and the Steam Controller in November last year, which was also around the same time that memory chips have started to be in short supply due to the massive demand from AI hyperscalers. The device was originally slated to launch in the first quarter of 2026, but the ongoing memory crisis forced Valve to hold off until it finally released the console this summer.

Although having only a single stick of RAM is a disadvantage to any system, more optimistic gamers can consider this a boon as they could easily upgrade the console to 32GB if they have an extra matching 16GB DDR5-5600 SODIMM stick lying around at home (or are willing to spend extra to buy one). Upgrading the console’s RAM is a rather involved affair, though, requiring you to remove a lot of components and sub-boards just to reach the RAM slots. But if you’re the adventurous kind and could score a good deal on laptop RAM, this might be a viable solution to getting more performance out of your Steam Machine.

TSMC has reportedly told customers to prepare for price increases across its advanced chipmaking portfolio, extending the hikes beyond the newer 3nm process to include 7nm and even legacy products. According to a June 23rd Culpium report, the increases would affect the bulk of TSMC’s wafer revenue and could raise costs for major chip designers, including Apple, Nvidia, AMD, Qualcomm, Broadcom, and MediaTek.

The exact size of the increases remains unclear, as figures would reportedly vary by customer, node, and product category, but generally appear to fall in the 5% to 10% range. TSMC price increases have reportedly already started rolling out in some cases, while other customers have been told to build the higher cost structure into future purchase orders.

The company declined to discuss specific pricing with Culpium. “TSMC does not comment on pricing. Our pricing strategy is strategic, not opportunistic,” the company said in a statement to the publication. “We will continue to work closely with customers and sell our value to them.” Although the company had earlier said it would refrain from raising prices.

Earlier reports from Taiwanese media had mainly pointed to increases at TSMC’s 3nm node, one of its most advanced processes currently used for premium smartphones, PC, and AI chips, with price pressure also expected at the newest 2nm-class production. However, Culpium reports that TSMC has informed clients that “all advanced nodes” will become more expensive, meaning the hikes would extend beyond 3nm and 2nm to include older but still advanced processes such as 5nm and 7nm.

3nm alone accounted for 25% of TSMC’s wafer revenue in the first quarter of 2026, while the company’s full advanced-node portfolio — defined by TSMC as 7nm and more advanced technologies — accounted for 74% of wafer revenue. Therefore, the hikes would span nearly three-quarters of the company’s wafer business.

The inclusion of 7nm is especially notable because the node is no longer TSMC’s flagship technology. However, it's not exactly surprising as 7nm remains heavily used across processors, accelerators, networking silicon, and other high-performance chips. Many products remain on older, more advanced nodes because they offer better cost, yield, and maturity than the newest processes, especially when a design does not require the density or efficiency gains of 3nm or 2nm.

The client notices follow weeks of public comments from TSMC executives suggesting that higher prices were at least under consideration. At the company’s annual shareholders’ meeting in Hsinchu on June 4, CEO C.C. Wei said customers remained positive on the AI demand outlook, while also acknowledging cost pressures and the widening gap between chip demand and available manufacturing capacity. CFO Wendell Huang also said earlier that TSMC did not rule out price increases as inflation, overseas expansion, and advanced manufacturing costs continue to rise.

The timing of the price increases reflects TSMC’s strong negotiating position. The company remains the dominant manufacturer of leading-edge logic chips, and its most advanced capacity is in high demand among AI accelerator vendors, smartphone chip designers, and custom ASIC developers. With customers competing for access to the same manufacturing lines, TSMC has more room to pass on rising costs than it would in a weaker cycle.

The move also comes as TSMC benefits from a surge in AI-related demand. In its first-quarter results, the company reported $35.9 billion in revenue and a 66.2% gross margin, both supported by strong demand for high-performance computing and advanced-node production. TSMC has also raised its 2026 revenue growth target to more than 30%, with capital spending expected to remain elevated as the company expands capacity in Taiwan, the U.S., Japan, and Germany. The company’s Arizona manufacturing capacity has been sold out through 2027 since early 2025.

The reported increases are still far smaller than the recent price spikes seen in the memory market, where AI-driven demand for HBM and other high-end memory products has allowed suppliers to push through much steeper increases. Conversely, TSMC does not need memory-style pricing to meaningfully improve its margins. Because advanced nodes account for most of its wafer revenue, even a mid-single-digit increase across that base could add billions of dollars in annual revenue if demand remains strong.

For chip designers, the immediate impact is a higher manufacturing bill. For consumers, the effect is less direct but still important. A 5% to 10% wafer price increase does not automatically translate into a 5% to 10% increase in the price of a GPU, CPU, smartphone, or laptop, since the wafer is only one part of the final product cost. However, when combined with higher memory prices, packaging constraints, AI demand, and rising manufacturing costs, it creates another reason for device makers and component vendors to raise prices or protect margins by cutting costs elsewhere.

DDR2 contract prices rose 55% to 60% in the second quarter of the year and are projected to climb another 35% to 40% in the third, according to research published this week by TrendForce, pushing the AI-driven memory shortage onto a standard that first shipped in 2003 and that the three largest DRAM makers stopped prioritizing years ago. The increases come from buyers redesigning products around older memory to secure supply, and from a split among the handful of remaining DDR2 suppliers, with Winbond reducing output as ESMT expands it.

The shortage hasn’t hit DDR2 directly, but Samsung, SK hynix, and Micron have steered wafer capacity toward HBM and server DRAM to feed AI infrastructure spending, thinning the supply of mature-node parts, including DDR4. As DDR4 tightened, OEMs and ODMs began specifying DDR3 in its place, and some DDR3 designs were reworked to use DDR2, with each tier of buyers chasing whatever generation it could still source. The result of this is shortages moving down through successive generations, something we saw unfolding back in March, when earlier data showed DDR3 and DDR2 prices rising 20% to 40% in a single month.

This continues the market inversion we’ve watched unfold throughout the year, as DDR4 climbed past DDR5 on price despite being slower and older, and in which module makers and motherboard vendors restarted DDR4 production after the big three had moved to wind it down.

Winbond and ESMT are the two main remaining sources of DDR2 components, and they’re responding to the squeeze in different ways. Winbond is gradually cutting DDR2 production to shift capacity toward higher-margin DDR3, DDR4, and LPDDR4, while ESMT is doing the reverse, concentrating its wafer allocation at foundry partner PSMC on DDR2 to capture the demand Winbond is tossing aside. Taiwanese suppliers, including Nanya, are already struggling to match the volume of orders migrating down from DDR4, and because new capacity depends on slow process migration, Winbond's withdrawal removes supply faster than ESMT can replace it.

Of course, today’s PCs don’t use DDR2, so we’re likely to see the impact of these price increases landing in areas like embedded systems, networking equipment, industrial controllers, automotive electronics, and other long-lived devices that were designed around it and are too costly to requalify on newer memory generations like DDR4 and five.

The spread of rising contract prices to DDR2 suggests that we’re staring down the barrel of a very long-term DRAM shortage. Contract prices across the wider market are still rising with no sign of levelling off, and meaningful new capacity isn’t expected until late 2027 at the earliest as a best-case scenario.

While we're accustomed to having Samsung, Micron, or SK hynix chips in the best RAM on the market, it may not be long before we start seeing Chinese chips in mainstream memory kits. According to ITHome, many Chinese memory vendors have already defected to domestic producers such as CXMT (ChangXin Memory Technologies).

Chinese manufacturers such as CXMT, which produces chips for memory, and YMTC (Yangtze Memory Technologies Corp.), which manufactures NAND for storage, often enjoy heavy government backing and other subsidies. While there isn't an obligation per se, it's understood that domestic chipmakers contribute to China's technological self-sufficiency; therefore, profits somewhat take a back seat.

While foreign chipmakers, such as Samsung, Micron, and SK hynix, are maximizing profits of data centers and the AI boom, Chinese chipmakers prioritize supplying Chinese companies. To a certain extent, the supply and pricing of memory chips, or NAND, in China are relatively stable because it's shielded from the steep premium charged by the Big Three memory giants.

Nelson Duann, Silicon Motion's Senior Vice President, in a recent interview with Tom's Hardware, stated that "China is a different market. China has domestic NAND and DRAM makers, and their strategy is not the same as that of foreign memory suppliers. Because they receive government support, they also have a responsibility to help maintain the health of the local market."

Duann went on to say that "foreign suppliers generally follow the highest-return opportunities and can allocate most of their supply to data centers. Chinese suppliers cannot do that in the same way because the government can provide guidance and encourage them to support certain local industries."

Chinese memory brands Gloway and KingBank recently announced new DDR5 memory modules that highlight the usage of domestic 24Gb (3GB) memory chips. Using a standard eight-die configuration, these companies could produce 24GB memory modules and package them into dual- or quad-DIMM memory kits for 48GB or 96GB of capacity, respectively.

Chinese memory chips, particularly those from CXMT, have begun to spread outside China. Corsair has already implemented CXMT DDR5 in some memory kits from the brand's prestigious Vengeance lineup. Meanwhile, titans such as HP and Dell have begun qualifying CXMT memory kits for their products. Unfortunately, we haven't had the opportunity to review any memory kits with CXMT chips, so their performance and overclocking headroom remain to be seen.

Despite having just 10 years under its belt, CXMT has gradually become an influential player in the chipmaking game. Thanks to U.S. export controls that have effectively cut China off from acquiring advanced extreme ultraviolet (EUV) lithography tools, CXMT has made all its progress with trailing-edge deep ultraviolet (DUV) chipmaking tools. The company's 16nm (G4) node is its current flagship manufacturing process, which CMXT uses to produce DDR5 and LPDDR5X chips, or the same ones found in recent Corsair, Gloway, and KingBank memory kits. Whether the use of CXMT DRAM becomes more widespread as a result of the AI supply crunch remains to be seen.

Nvidia and SK hynix have inked a multi-year collaboration agreement under which the companies will co-develop next-generation memory technologies for Nvidia's upcoming platforms, and SK hynix will supply them to Nvidia. The deal is designed to ensure that Nvidia will get the memory it needs from a prominent supplier and will guarantee that SK hynix will be able to sell its output in a predictable manner.

The key part of the agreement is indeed the co-development of advanced memory products designed for Nvidia's future platforms. Currently, Nvidia uses HBM, LPDDR5X, DDR5, and 3D NAND memory in various systems, so going forward, SK hynix will develop its new memory with Nvidia in mind. The joint press release says nothing about customization of memory for Nvidia, and while we cannot exclude such a possibility, it looks like the companies will continue to co-develop industry-standard solutions, but will ensure that they are compatible with Nvidia's processors.

In addition, the agreement is intended to address the increasingly long lead times and massive capital expenditures required for the production of advanced types of memory. The two companies will coordinate roadmaps over multiple years. Nvidia will gain greater visibility into future memory availability, while SK hynix secures a guaranteed role in Nvidia's next-generation platforms (i.e., guaranteed demand).

The initial part of the cooperation covers memory destined for NVIDIA Vera Rubin AI systems (HBM4, LPDDR5X, 3D NAND), standalone Vera processors (LPDDR5X), RTX Spark-powered personal computers (LPDDR5X, 3D NAND), and Jetson Thor robotic computing systems (LPDDR5X, 3D NAND).

The deal also extends to semiconductor research and design. SK hynix is deploying Nvidia's CUDA-X libraries to speed up complex chip development workloads, such as technology computer-aided design (TCAD) and computational lithography (CuLitho). In addition, the memory maker is adopting Nvidia PhysicsNeMo to accelerate proprietary simulation software as well as AI-driven physics models used during semiconductor development. In addition, the companies see an opportunity to expand these capabilities into general electronic design automation (EDA) and simulation ecosystems and potentially create tighter relationships within the industry.

Last but not least, SK hynix is creating digital twins of its semiconductor fabs using Nvidia Omniverse and OpenUSD technologies. These virtual facilities enable engineers to model production lines, test changes, and optimize operations before making adjustments in real fabs. The company also plans to use Nvidia's cuOpt and Metropolis platforms to improve the movement of autonomous robots and other factory equipment. In the future, SK hynix aims to connect these digital twins with existing manufacturing software and AI systems and enable them to analyze fab data, automate routine tasks, and help make production decisions.

Lexar's Regional Manager for Australia & New Zealand, Chris Xia, said that he personally thinks RAM prices are expected to double by the end of the year. While there have been a few instances of RAM module prices stabilizing and even some retailers selling them for a discount or bundled with other PC parts, he said that this is just sellers making an effort to make their inventory move and make way for new stocks, which are expected to be priced higher.

The current AI build-out is siphoning all the memory chips available from the traditional big three suppliers — Samsung, SK hynix, and Micron — with nearly all production capacity getting allocated towards high-bandwidth memory. Consumers are getting left behind, and as supplies dry up, their prices continue to go up.

Sapphire PR manager Edward Crisler said last December 2025 that DRAM prices will begin to stabilize in the next six to eight months, albeit at higher prices. However, the situation seems to have changed, and industry insiders now expect prices to continue going up towards the end of the year. Xia said that industry costs take up to eight to nine months to affect consumer prices, and the current market pricing trend has only been going up.

Some consumers get hope when they see RAM kits getting discounts or retailers lowering the list prices of these items, but Chris said that these are often the result of sellers trying to get rid of old inventory. They do this so that they can get some liquidity back and to make way for new stocks coming in from suppliers, usually at a higher price. Another thing that adds to the confusion is that some distributors manage to get their hands on unsold inventory from other regions that are still priced lower compared to what’s arriving now. Because of this, they’re able to sell at a lower price — but only until supplies last. Once the old stock runs out, they will eventually be forced to increase retail prices as market forces catch up with the low supply and high demand. Xia recommends that if you need to buy RAM, you should buy it now. Don’t wait for lower prices as they won’t arrive for years to come.

The memory chip crisis is going beyond desktop computers and laptops, which are expected to see shipments contract by more than 10%. Motherboard sales have already collapsed by more than 25% as the increasing RAM and SSD prices are making enthusiasts think twice before building a new system. Smartphones are expected to either get more expensive or see lower and slower memory configurations, and even action camera manufacturer GoPro is in trouble due to memory chip shortages and lower sales.

AMD's EXPO Ultra Low Latency program, announced at Computex 2026, aims to give users a one-click route to lower memory latencies than its existing EXPO profiles, but the company's initial announcement was light on details. To learn more about EXPO ULL, I stopped by G.Skill's Computex booth, where the company demonstrated four new kits that offer EXPO ULL support.

Memory latency directly affects how long the CPU has to wait in order to get data back from RAM, and so it has a major impact on CPU performance. But even as new DDR standards and ever-faster DIMMs have boosted memory bandwidth, DDR latency has improved at a much slower pace over time.

For some very high-level background, when selecting memory, PC builders will generally consider a given memory kit's speed and its CAS latency (CL). If you compare two CL30 memory kits, for example, the one with the higher clock rate will have a lower effective latency in nanoseconds (because CL30 expresses a number of clock cycles).

Knowing this, your first instinct for reducing latency might be to seek the highest-clocked memory you can find with the lowest CAS latency (like DDR5-8400 or even faster modules).

But on modern AMD platforms, it's not that simple. Reaching memory speeds higher than 6000 MT/s generally requires the use of a 1:2 multiplier mode between the clock of the integrated memory controller (the UCLK), which generally tops out around 3000 MHz, and the memory clock (MCLK). This 1:2 multiplier adds latency, and so it can counterintuitively reduce performance even as memory speeds climb above 6000 MT/s. (Remember that DDR memory moves bits at twice the clock rate, hence MT/s).

With this 1:2 multiplier active, by the time additional memory clock speed even begins to bring latency back down to where it would generally be in the 1:1 mode, you're looking at wildly expensive and exotic memory kits, and so most enthusiasts running Ryzen 7000 and Ryzen 9000 CPUs consider it desirable to choose memory that lets them run the UCLK and MCLK in 1:1 lockstep for the best balance of low latency and (relatively) low cost.

All that is why using memory faster than 6000 MT/s on AMD platforms is generally counterproductive for gaming performance. That's why modules in the range of DDR5-6000 CL30 are widely regarded as the overclocking "sweet spot" for Ryzen 7000 and Ryzen 9000 CPUs.

But that doesn't mean there isn't further room for improvement, as the introduction of EXPO ULL suggests.

G.Skill told me that until now, DRAM module makers were only permitted to change the four primary timings within EXPO (and XMP) profiles, leaving performance on the table. EXPO ULL affords memory makers more freedom to adjust the sub-timings within each of those four primary timings for even lower latencies, and to include those results in the memory's SPD.

Tweaking memory sub-timings on Ryzen platforms using community-made tools to determine the best potential settings used to be a fairly common practice for those seeking the best performance from their AMD systems, but Ryzen X3D processors and their massive slices of 3D V-Cache reduced those CPUs' sensitivity to those finer adjustments. It's become much more common to just get a DDR5-6000 CL30 kit, enable EXPO, and call it good.

But if you are focused on achieving the absolute lowest memory latency, EXPO ULL removes the need to perform the (tedious and tricky) process of determining those improved sub-timings by allowing memory makers to shoulder that work and include it as part of the one-click boost that EXPO provides.

For all that, EXPO ULL doesn't change the fundamental performance characteristics of X3D versus non-X3D CPUs, so while you can certainly pair an X3D chip with an EXPO ULL kit, G.Skill tells me that you're not going to see as large of a difference in performance from that pairing as you would with a non-X3D chip. That's why AMD is touting the performance gains of EXPO ULL with a Ryzen 7 9700X and not the Ryzen 7 9850X3D you might expect.

G.Skill also told me that EXPO ULL-ready memory requires stricter binning of individual memory chips during production, so it isn't just a software change that can be applied to existing modules. The company says the extra work involved in this stricter binning process means that modules supporting the feature are likely to be more expensive than kits that haven't undergone the same characterization.

Overall, then, EXPO ULL is likely to be a premium (and somewhat niche) addition to the EXPO program instead of a broad replacement for non-ULL EXPO profiles. Demanding gamers who need the lowest memory latency for the best performance in CPU-bound gaming scenarios will likely want an EXPO ULL kit regardless of the type of Ryzen CPU they're using. But we'll have to see just how much extra cash these kits demand in today's already eye-watering memory market and what benefit they have, if any, for AMD's massively popular X3D chips.

A coalition of nine US trade associations has urged the Trump administration to take immediate action on what it describes as an emerging memory chip shortage driven by the explosive growth of AI data centers. In a June 3 letter sent to US Commerce Secretary Howard Lutnick and Treasury Secretary Scott Bessent shared with Tom's Hardware, the organizations — representing telecommunications providers, automakers, medical device manufacturers, and major retailers — warned that AI infrastructure deployments are consuming an outsized share of global memory production, creating supply constraints and price increases that could ripple across large segments of the US economy.

The coalition warned that the AI data center expansion, which has consumed an unprecedented share of global memory capacity, has led to a memory chip shortage that could lead to higher prices for consumer electronics, increased costs for broadband and telecommunications infrastructure, disruptions to automobile and medical device production, and delays affecting federal contractors attempting to fulfill government procurement obligations. The letter argues that these risks are emerging despite billions of dollars of US investment intended to strengthen domestic semiconductor supply chains.

The signatories acknowledged AI's importance but argue it shouldn't come at the expense of the rest of the economy. "While recent developments in AI offer the promise of generational technological advances and are important for US tech leadership, we must also ensure other key industries are not negatively impacted by this disruption in the marketplace," the coalition said.

The organizations are asking the administration to work directly with memory suppliers and major chip buyers to address the imbalance. Their recommendations include accelerating expansion of memory manufacturing capacity in the United States and allied nations, using trade agreements to strengthen supply-chain resilience, ensuring adequate memory supply for non-AI industries, leveraging CHIPS Act programs where possible, and reducing regulatory barriers that may slow capacity growth.

"We urge the Administration to work with memory chipmakers and chip buyers to assess steps that can be taken to address this imbalance in the memory market and protect against harm to consumers, workers, and businesses of all sizes," the letter states.

The warning arrives as memory manufacturers increasingly prioritize high-bandwidth memory (HBM), the specialized memory used in AI accelerators from companies such as Nvidia and AMD. Demand for HBM has surged over the past two years as hyperscalers race to deploy larger AI clusters, prompting memory suppliers to devote an increasing share of their production capacity to AI-oriented products.

Samsung and SK Hynix — which together with Micron control over 95% of global DRAM production — have been diverting wafer capacity toward high-margin HBM for AI accelerators, starving the commodity DRAM and NAND markets in the process. Both companies warned in April that significant shortages will continue through at least 2027. IDC, meanwhile, has already revised its 2026 PC market forecast downward by up to 9% as a direct consequence of memory scarcity and rising prices.

Industry analysts have repeatedly warned for months that AI demand is reshaping the economics of the memory market. While memory shortages have historically been cyclical, the coalition argues that AI infrastructure spending is creating a structural shift large enough to affect industries far removed from data centers. The letter marks the first coordinated, multi-industry push for federal intervention. Whether the administration will respond — and how — remains to be seen.

The PC industry is bracing for a slip back to DDR4 memory among enthusiasts. Tom’s Hardware has learned at Computex 2026 that both motherboard brands and many module houses — the companies that produce the DIMMs you can buy — are shifting their strategy toward a resurgence in DDR4 platforms as unprecedented memory shortages and price increases continue to raise the entry point into building a PC. Those pain points are particularly acute with DDR5 memory.

We confirmed with over half a dozen sources: motherboard manufacturers and module houses are seeing an increase in demand for DDR4 platforms and shifting production accordingly. This could create challenges, however, as high-performance DDR4 dies, such as the famous Samsung B-dies, are no longer in production. As such, most of the revamped DDR4 kits will top out at a rather pedestrian DDR4-3600.

On the motherboard side of things, at least two vendors confirmed to Tom’s Hardware that they are ramping production of DDR4-supporting motherboards for the second half of the year and into 2027, which makes sense, given that motherboard sales have seen a “collapse” this year, with sales declining by as much as 37% with some vendors. Others have confirmed that they plan to either refresh or re-release DDR4-supporting options later in the year. Many of these products had been in end-of-life (EOL) status, so production lines had long ago shifted to other products. Now new manufacturing capacity will be dedicated to restoring those product families.

This comes as demand for DDR4 platforms has increased. One motherboard brand cited a double-digit increase in sales over the last quarter, which Tom’s Hardware was unable to corroborate, while others simply said the demand has increased significantly.

AMD and Intel have geared up for a shift back to DDR4, as well. AMD launched the Ryzen 7 5800X3D 10th Anniversary Edition at Computex, which the company says it will continue to sell as long as it makes sense; in other words, it’s not a limited edition run. AMD has also shifted the hybrid bonding process of the 5800X3D, setting it up for a more long-term production run. It joins AMD’s Zen 3 XT chips, which it released in 2024 and continues to sell.

Intel continues to sell its Raptor Lake and Raptor Lake Refresh CPUs, as well, and the company told Tom’s Hardware it “will continue to make sure that there are products which can take care of older memory technologies.” One motherboard vendor said it was specifically ramping production of LGA 1700 motherboards with DDR4 support, as options have slowly dried up in the market.

Although there is already DDR4 in the market, it’s also easier to produce, which would help elevate some of the bottlenecks in the current memory supply chain. One of the key shortages right now is advanced packaging, which DDR5 requires with an integrated PMIC. DDR4, by comparison, is much simpler to package and sell, which should help keep prices from climbing into the DDR5 range.

The major chokepoint for DDR4 is wafer allocation, which is a bottleneck that one memory manufacturer (not a module house) pointed to as a potential issue with a shift back to DDR4 platforms. Wafer allocation is a broader bottleneck within the PC industry, however, with Intel even shifting allocation toward the data center as an unprecedented demand for data center CPUs takes hold.

Unfortunately, there appears to be no end in sight. If there’s one thing that nearly all of our sources agreed on, it is that DRAM and NAND shortages will continue throughout all of 2027.

TeamGroup showed Tom's Hardware a new external SSD with a remote “self-destruct” function at Computex 2026. The T-Create Expert P35SG External SSD offers a “wireless one-click data destruction” function, letting you wipe the contents of the storage device remotely with a single text message.

The drive is connected wirelessly via 4G LTE to ensure that the user can still reach it even when not connected to Wi-Fi or to another device. Once it receives the wipe command, it triggers a “deep-level logical wipe” of the drive and then executes a high-voltage “physical hardware breakdown” to ensure that its contents are unrecoverable. This new drive arrived on the show floor nearly a year after TeamGroup revealed the P250Q-M80 M.2 SSD that had a similar physical self-destruct function.

Aside from this wireless high-security external drive, the company also unveiled the T-Create Expert P35S, which offers the same “self-destruct” function, but through a physical button right on the drive. There’s also the P33 External SSD, which includes an e-Paper display that can show important information like available storage capacity, drive health, drive name, and other information. This lets you see what a particular USB drive contains without needing to plug it into a device or place an external label on it.

There’s also the T-Create Expert AI 4R CUDIMM — this quad-rank CUDIMM packs in two rows of DRAM chips on both sides, giving a single RAM stick 128GB capacity. The sample DDR5 RAM was installed on an MSI MEG Z890 Unify-X that offers two RAM slots, giving it a total capacity of 256GB. We’ve seen other vendors like Origin Code bring 4R CUDIMMs to market, too, and this high-capacity RAM, which could potentially go as high as 256GB per stick, is quite useful for AI developers and enthusiasts who need the massive amounts of memory for AI agents.

Gamers gets goodies from T-Force too

Aside from the professional and creator-focused T-Create product line, TeamGroup also introduced new RAM kits, SSDs, and associated accessories from T-Force. The most interesting new device is the T-Force Liquid II SSD cooler, which brings liquid cooling to SSDs. This cooling solution is designed to sit on an exposed SSD and uses aluminum alloy heatsink fins, a micro cooling fan, and a liquid coolant (available in multiple colors) to help keep your high-performance storage drive cool. The coolant itself is designed to last five years and could be topped up as necessary.

There’s also the T-Force DARK RGB desktop memory kits, which are designed for low-profile builds with a maximum height of just 42mm. Despite its lower height, this RAM kit still features 6400 MT/s speed and a full RGB light strip. It’s also available in various capacities up to 64GB, making it an ideal solution for enthusiasts looking for an SFF build.

And, in celebration of 10 years of T-Force, TeamGroup also released several carbon-fiber-themed products. These include the T-Force Delta RGB DDR5, T-Force Xtreem DDR5, T-Force Z54E M.2 PCIe 5.0 SSD, M400 RGB External SSD, and the T-Force Vulcan and Delta LPCAMM2 DDR5 memory.

We expect these products to drop in the coming weeks and months, although we weren't able to confirm exact availability dates. Nonetheless, we can't wait to get our hands on some of these new solutions and see how they match up against the best RAM and SSDs we have available at the moment.

Representatives told Tom's Hardware at Computex 2026 that counterfeit memory modules with G.Skill and V-Color badges have hit various marketplaces in China, and the problem is widespread enough that V-Color has observed lower sales to certain clients. Fake memory modules are nothing new, but in this case, forged DIMMs reportedly use printed circuit boards (PCBs) that are identical to those used by G.Skill and V-Color, which makes early detection of counterfeit products difficult.

“We have customers telling us that some Chinese manufacturers are making copies of our products, as well as products from other brands, and selling them at lower prices than we do,” a spokesperson for V-Color told Tom’s Hardware. “We do not really know how they are doing it. The PCB looks the same, even the heat spreader looks identical.”

Given the current situation with memory prices, counterfeit memory modules have become a growing problem in Asian online marketplaces, particularly in gray-market and second-hand channels. Recent reports described fake DDR5 modules containing dummy ‘chips’ made of plastic or fiberglass with fake markings, as well as mislabeled modules marked as products from well-known brands. However, the new case is different because forged memory modules use PCBs that are identical to those used by G.Skill and V-Color and use the same heat spreaders and perhaps complex RGB lighting, making distinguishing between real and counterfeit products particularly difficult.

While developing a PCB for an enthusiast-class memory module takes time and money, producing that PCB is fairly easy, as makers of DIMMs use neither complex PCBs nor too complex equipment. Also, developing enthusiast-grade memory modules (ensuring that they run at the right specifications with popular CPUs) also takes time and money. In addition, sourcing chips from DRAM makers or distributors to make fake memory modules is hard, if even possible at all today. Finally, quality control at the chip level and at the module level is relatively costly, and these two are the main value adders when it comes to enthusiast-grade memory. That said, forging high-end memory modules is easy and might be a profitable business, especially if perpetrators have access to second-hand memory chips. Speaking of chips, the V-Color representative could not say which ICs the fake modules used.

“We do not know because we have not had any of those modules in our hands,” the spokesman said. “We only use SK hynix memory, so we cannot say what chips they are using. We have not received any RMAs related to them. Other brands may have received returns and been able to inspect the products, perhaps because the memory chips were different.”

While a representative for G.Skill confirmed that there are counterfeit G.Skill memory modules sold on Chinese marketplaces, he said that the issue has existed forever, so users should buy their high-end DIMMs from official partners and resellers in a bid to avoid the problem.

As the demands of AI continue to consume manufacturing capacity at every level of the PC hardware supply chain, 32GB of DDR5 RAM — broadly understood to be the sweet spot for gaming PCs and enthusiast builds — can no longer be found for less than $375. Well, $374.97 to be precise.

RAM price tracking through 2026 will show you that kits that routinely cost less than $100 just a year ago are now fetching upwards of $240 (16GB). As the AI frenzy has taken hold, retailers far and wide have been pumping up their RAM prices to exorbitant levels. However, there's so much fluctuation and noise that average pricing is now something of a ludicrous fugazi. The going rate for 32GB of DDR5 RAM — the cheapest you can expect to pay — has hovered around $320 for some time, climbing past $350 in recent weeks. Price tracking courtesy of PCPartPicker now reveals the cheapest 32GB DDR5 RAM you can buy is $375. Specifically, four XPOWER kits from Silicon Power will set you back $374.97 thanks to a promo code. You can see the listings yourself below.

• Silicon Power Zenith Gaming DDR5 6000MT/s (PC5-48000) CL36 32GB(2x16GB)
• Silicon Power Zenith RGB DDR5 6000MT/s (PC5-48000) CL36 32GB(2x16GB)
• Silicon Power Pulse Gaming DDR5 6000MT/s (PC5-48000) CL36 32GB(2x16GB)
• Silicon Power Zenith RGB DDR5 6000MT/s (PC5-48000) CL36 32GB(2x16GB)

As you can imagine, this is enormous pricing pressure for enthusiasts trying to build gaming PCs or upgrade their rigs in 2026. A component that once cost less than $100 and was something of an afterthought now costs almost four times as much, and that's before you've even fired a neuron in consideration of aesthetics, timings, or brand. More popular kits from the likes of Corsair and Crucial, or RGB offerings to match the rest of your build, will easily set you back more than $400.

Of course, 32GB is really the minimum sweet spot you should be aiming for when building a PC in 2026. If you did want more capacity, 64GB will set you back an astonishing $679.99. 16GB of RAM as a compromise can be found for $200 at B&H Photo, but with SK hynix warning that manufacturing constraints will persist through 2030, there's no sign of prices letting up so that you can upgrade capacity any time soon.

The humble RAM combo deals we've been highlighting in recent months are a small source of solace for builders, letting you score RAM for less than the $375 going rate if you pair it with a decent motherboard, a processor, or even an entire set of PC components. A theme of ongoing Computex 2026 announcements remains a lack of pricing clarity on lots of PC hardware, including Nvidia's RTX Spark laptops and PCs, as well as new-build systems and, of course, RAM components themselves. Vendors are likely wary of scaring off potential buyers with higher-than-expected prices ahead of release. Perhaps more likely, the prices haven't been set because they're still going up. Storage isn't much better, with SSD price tracking revealing that drives which once cost as little as $38 are now fetching $200.

AMD is making a noticeable effort to keep PC gaming prices down, this week announcing the return of its Ryzen 7 5800X3D, and the advent of a new Ryzen 7 7700X3D. Intel, which warned this week that "something has to give" when it comes to memory prices, also teased dragging out some of its legacy products to give users more options on older memory technologies, namely Raptor Lake and DDR4.

GoPro, the creator of the modern action camera, warned in a regulatory filing on June 1 that it faces “substantial doubt about the company’s ability to continue.” According to Digital Camera World, the news report comes as the camera manufacturer is pummeled on both sides by declining sales and increasing costs, particularly memory chips driven by a global AI shortage.

These action cameras do not have internal memory, meaning buyers must purchase their own microSD cards. So, even though these have skyrocketed in price, the only direct impact they would have on the company would be reduced sales because buyers are balking at the thought of buying a separate storage card. On the other hand, even though camera specifications do not list them, these cameras' processors require RAM.

GoPro, as a niche action camera maker, isn’t in a good position as smartphones have become better at photography and videography. Furthermore, it has faced stiff competition from the likes of DJI and Insta360, which also offer products such as drones and gimbals. While the FCC has banned the former from the U.S. market, the latter is still widely available.

The action camera company suffered a net loss of $432.3 million in 2024, while it managed to shrink this to $93.5 million last year. Unfortunately, GoPro saw reduced sales in April and May this year. When you pair that with the memory chip crisis, which has driven up RAM prices and made supply harder to find, it seems that GoPro is in real trouble.

This filing does not mean the company is in deep trouble just yet, but it publicly signals that it needs to address its situation — otherwise, it could lead to a complete disaster. “Without obtaining additional sources of financing or consummating a strategic transaction, the Company’s ability to continue as a going concern would be materially and adversely impacted,” GoPro said in its regulatory filing. “The Company may be required to significantly reduce, restructure, cease operations, or seek protection under the Federal bankruptcy laws, although no specific plans to file for bankruptcy protection have been initiated or considered.”

Since GoPro is a publicly traded company, it’s required by law to make notifications like this. Still, it does not mean the company cannot turn itself around before it runs out of cash. We’ve seen a few firms turn themselves around before they had to declare bankruptcy. However, because GoPro is focused on such a niche product, vagaries in the direction of its only market will have an outsized impact on its sales and revenue.

AMD announced EXPO Ultra Low Latency at Computex 2026, but provided very few details about what it is or how it works. The company claims it provides a 13% average uplift compared to JEDEC standards, and a 4% uplift compared to standard EXPO, and that’s it’s coming from leading memory partners. Now, AMD’s David McAfee, VP and general manager of Ryzen and Radeon, has given Tom’s Hardware a bit more color on what exactly EXPO ULL is and how it will roll out.

“Expo has evolved, and we've been working with all of the module vendors. We've seen an opportunity with adding more sub timings to the SPD profile, and just getting a little bit lower latency,” McAfee told Tom’s Hardware.

Beyond what EXPO ULL is doing, AMD says that it will work with existing chipsets and motherboards, but McAfee clarified that he wasn’t sure if it would require a BIOS update (that seems likely). Regardless, McAfee said: “My advice to all of your readers and viewers is: update your bios.”

EXPO ULL kits will come with different branding on them, including a new badge, so “it’ll be noticeable that these kits are different.” McAfee also says that, although AMD doesn’t control memory or module prices, “[AMD’s] understanding from the partners is [that] they expect to bring these in at effectively the same price points that the current kits are at.”

Those price points, at the moment, are inflated due to ongoing memory shortages. But McAfee isn’t being coy here about pricing. The executive says ULL is “simply about extending the sub-timings and really getting every little bit of OC performance out of those DIMMs,” so there’s nothing specifically about ULL that would cause the DIMMs to be radically more expensive.

Across a test suite of 30 games with the Ryzen 7 9700X, AMD says ULL delivered a 4% uplift compared to standard EXPO, with both running at DDR5-6000, and a 13% uplift compared to JEDEC-standard DDR5-5600. 1% lows, as expected, see more of an improvement, with a 15% uplift compared to JEDEC and the same 4% compared to standard EXPO.

AMD says that EXPO ULL is “coming soon,” but it hasn’t said anything beyond that for a release window. Regardless, it already has partners lined up to support the feature, including G.Skill, Kingston, Lexar, XPG, and TeamGroup.

This week at Computex 2026, we saw Nvidia reveal its RTX Spark, and last month, AMD detailed its Ryzen AI Max 400 "Gorgon Halo" lineup, a refresh of the Strix Halo APUs that lifts supported unified memory to 192GB and allows up to 160GB of that pool to be addressed as VRAM. AMD describes the flagship Ryzen AI Max+ PRO 495 as the first x86 client processor able to run a 300-billion-parameter language model locally, pitching the platform for use cases that need to keep multiple AI agents resident in memory at once.

The market for Gorgon Halo will likely be directly shared with other chips, such as Nvidia's RTX Spark, which debuted at Computex 2026. RTX Spark is also positioned as an on-device agentic computing device. With local AI computing demanding lots of on-device RAM, it poses a difficult issue for device vendors.

DRAM contract prices are forecast to climb another 58% to 63% this quarter, on top of the record 90% to 95% jump TrendForce recorded in Q1, which also saw Nvidia raise the price of its DGX Spark desktop from $3,999 to $4,699, citing memory supply. So, what happens to the dream of accessible local AI compute?

DRAM supply squeeze

The local AI PC has become a category defined by how much memory it carries, and it’s scaling that memory up at a time when memory has never cost more. AMD's three Gorgon Halo SKUs reuse the same Zen 5 cores, RDNA 3.5 graphics, and XDNA 2 NPU as the existing Ryzen AI Max 300 parts, with the Max+ PRO 495 gaining a 100 MHz boost-clock bump to 5.2 GHz, a 40-compute-unit Radeon 8065S, and a 55 TOPS NPU.

Memory capacity has been increased 50% from the 128GB ceiling on Strix Halo, with a leaked PassMark entry putting the 192GB figure as eight 24GB SK hynix LPDDR5X packages on an HP test board, though AMD hasn’t yet confirmed this. Partner systems from Asus, HP, and Lenovo are due in the third quarter of 2026.

It’s all well and good that Nvidia and AMD are releasing machines like the RTX Spark and the Gorgon Halo line-up. However, Samsung, SK hynix, and Micron have all shifted the bulk of their wafer capacity toward high-bandwidth memory for AI accelerators because HBM carries far higher margins than commodity DRAM, and the conventional memory supply has tightened as a direct result of this. HP told investors in February that memory now accounts for roughly 35% of the cost of building a PC, up from 15% to 18% a quarter earlier.

SK Group chairman Chey Tae-won, speaking at Computex 2026 on the show’s official opening day, repeated his position that the shortage will run through 2030, despite the company's intention to double wafer capacity within the next five years. New fabs from all three makers are under construction, but none will reach volume production before late 2027 at the earliest, and most forecasts now predict a structurally higher price floor that persists even after the acute shortage eases.

The 192GB in a Gorgon Halo box, the 128GB in an RTX Spark or DGX Spark, and the LPDDR5X soldered into every AI laptop announced at Computex all come off wafers the memory makers would otherwise sell as HBM. That’s why Nvidia raised the DGX Spark by $700 in February without changing a single spec, and why component makers have begun passing memory costs through directly. One vendor has even taken an extremely on-the-nose approach of adding a flat memory surcharge to every purchase, and in some cases, smaller buyers are now quoted prices that change by the hour.

Bandwidth caps inference speed

A single pool of 192GB would enable an APU to hold a model that would otherwise require a multi-GPU server. While it doesn’t make the model run quickly, dense language model inference reads close to the full set of active weights from memory for every token generated, so generation speed is governed by memory bandwidth divided by the per-token weight footprint, not by idle memory.

Gorgon Halo keeps the same 256-bit LPDDR5X-8000 interface as Strix Halo, which tops out around 256 GB/s in theory and which independent testers have measured closer to 212 GB/s on the GPU. By comparison, the Apple M3 Ultra that AMD and Nvidia are chasing on capacity is rated at 819 GB/s, and an RTX 5090 moves data at 1,792 GB/s.

This gap explains why a dense 70-billion-parameter model fully resident on a Strix Halo iGPU lands in the low single digits of tokens per second, regardless of how much headroom the memory pool has. Our own Corsair AI Workstation 300 review found that Nvidia's slightly higher-bandwidth GB10 pulled ahead of Strix Halo as context length grew, for exactly this reason.

Capacity matters most for mixture-of-experts models, which activate only a fraction of their parameters per token and run far faster than their total size suggests, and for long-context agentic workloads, where it’s KVcache rather than model weights that consume memory. It’s these use cases that AMD’s agentic pitch points at, with leaked details on the next-gen Medusa Halo parts showing a move to LPDDR6 and as much as 80% more bandwidth.

Holding the line on price

Agentic AI is also something of a pricing tool for vendors, beyond describing a workload. A 192GB workstation sold on the promise of running 300-billion-parameter models locally can hold a four-figure price more comfortably than a mini PC sold on cores and clocks, and it justifies loading the most expensive component in the build to its maximum. AMD's Ryzen AI Halo developer box, a 128GB Strix Halo system, opens pre-orders in June at $3,999 through Micro Center, matching the launch price of Acer's GB10-based Veriton GN100 and the original DGX Spark before its increase.

Apple, the one vendor with the scale to hold priority memory allocation, has moved the other way. It pulled the 512GB Mac Studio configuration from sale, raised the price of its 256GB upgrade, and in May removed several more high-memory Mac mini and Mac Studio options as supply tightened.

This shows us beyond doubt that expanding capacity while holding the line on premium pricing is a choice the AMD and Nvidia camps are making, not one that the market is forcing. Whether buyers accept it rests on whether local agentic inference delivers enough value over cloud services to justify the outlay, on machines shipping with memory capacities that outpace the bandwidth that ultimately determines what that memory can do.

SK hynix will double its memory wafer capacity within five years, SK Group chairman Chey Tae-won told reporters at Computex in Taipei on June 2nd, while repeating his forecast that the AI-driven shortage gripping the memory market will run until 2030. As reported by Bloomberg, Chey declined to put an exact dollar figure on the expansion, saying instead that the company's 2026 spending would climb well above the 30.2 trillion won (roughly $20 billion) it spent in 2025, and confirmed SK hynix has filed to list American depositary receipts in New York this year.

On its own timeline, the pledge will do little to shorten the squeeze. Chey put the lead time for a greenfield fab at more than five years, placing fresh output near the tail end of the shortage window that he’s predicting. This new stance is also a significant departure from his March comments at Nvidia’s GTC conference, where he said a new fab wasn’t planned and that capacity couldn’t be added on demand.

Chey also said the cost of the buildout is difficult to pin down because prices for land, equipment, and electricity keep moving, which is likely why no figure accompanied the announcement. With the company's existing lines already saturated, customers have offered to buy SK hynix's EUV scanners and prefund fab lines as available capacity has fallen to near zero. "Until 2030, there's still some shortage," Chey told reporters

Ultimately, it’s HBM that’s driving the massive gap between wafer supply and demand. HBM consumes far more wafers per bit than standard DRAM and carries the industry's highest margins, so capacity keeps tilting toward them. SK hynix holds about 57% of the HBM market and 32% of global DRAM, and Chey has said he wants the company to become a major HBM supplier for Nvidia's Vera Rubin platform and is seeking more manufacturing partnerships in Taiwan beyond TSMC.

But buyers aren’t waiting on new fabs for relief. TrendForce projected DRAM contract prices to rise 63% in the second quarter after climbing roughly 95% in the first, and DDR4 spot pricing ran up around 2,200% over 12 months before a recent decline. Even with capacity doubling, outlooks across the next five years are unchanged, and the market is likely to stay tight for the rest of the decade as things currently stand with AI demand.

Thousands of SK hynix employees fled their factory stations earlier today as a fire broke out in a room where fluorine gas was used. Yonhap News reports that seven of the workers have been hospitalized, five are being treated for eye irritation, and two are under observation (machine translation). At the time of writing, a cleanup operation appears to be continuing at SK hynix’s Cheongju 4th campus, with all 3,600 employees evacuated. A company official told Yonhap, “There are no issues with equipment operation, so there will be no production disruption.”

Reports indicate that the fire began at around 10.23 am Korean time today. An unintentional fire is probably not a great thing anywhere in an advanced semiconductor fab, even in the burgers and cigars wing. However, in “the gas room on the 6th floor connecting the M15 and M15X factories at SK Hynix's Cheongju 4th campus,” it could have been a particularly nasty incident. This room includes equipment/canisters/pipelines holding highly toxic fluorine gas.

According to the Korean news source, the fire in the gas room was extinguished immediately by sprinklers, but fluorine escaped into the room at a concentration estimated to be 5 ppm. This is where the seven hospitalized workers had been situated.

Fluorine gas is used in various industrial processes, but it is a highly reactive gas that can cause spontaneous combustion or explosions if it comes into contact with common materials. It is also quite deadly to humans. Wikipedia states that “significant irritation of the eyes and respiratory system as well as liver and kidney damage occur above 25 ppm… The eyes and nose are seriously damaged at 100 ppm… and inhalation of 1,000 ppm fluorine will cause death in minutes.”

Official insists there will be “no production disruption”

With the immense demand and pressure on memory-making titans like SK hynix, some may be concerned that a facility like Cheongju closing even for a few hours could impact supplies, schedules, pricing, and more. However, an official insisted, “There are no issues with equipment operation, so there will be no production disruption.” It was also suggested that the fire/leak occurred in the gas pipeline, but that fact had yet to be determined.

At the time of writing, there may still be environmental purification and repair work to do. If and when that’s completed, operatives will begin safety inspections, including air quality measurements. After the all-clear, “we plan to return the employees,” the official told Yonhap. We’ve linked to the latest report on this incident available at the source.

Origin Code, one of the newest players in the memory market, has unveiled the brand's quad-rank (4R) CUDIMM memory kits to compete directly with the best RAM. Unveiled at Computex 2026, with DDR5 memory modules up to 128GB each, achieving up to 256GB (2x128GB) on a dual-DIMM motherboard has become a reality for the mass market.

Quad-rank memory has existed for a while, though it has largely been available in the enterprise and server domains. It has played a significant role in enabling high-capacity memory modules. However, it wasn't until very recently that the technology reached the mainstream market. Consumer memory modules normally feature a single- or dual-rank design.

In other words, memory modules either have a single set of memory chips (single-rank) or two sets (dual-rank). Quad-rank memory, on the other hand, comes with four sets of memory chips. As a result, memory manufacturers can fit more memory chips on a single memory module, increasing its density. DDR5 already enabled a single 64GB memory module, and now quad-rank DDR5 has upped it to 128GB, a twofold increase. It wouldn't surprise us if the capacity eventually reaches 256GB.

Origin Code showcased a standard 4R CUDIMM memory kit on a Gigabyte Z890 Aorus Elite Duo X with a Core Ultra 7 270K Plus processor. The 256GB (2x128GB) DDR5-8000 memory kit had relaxed 64-63-63-128 memory timings, which is entirely expected given that the modules run at 1.1V DRAM voltage. Notably, Origin Code has a flagship version that's geared toward enthusiasts and professionals who demand the absolute best in performance. The premium DDR5-8000 memory has much tighter memory timings, 42-57-57-108, but requires 1.4V.

The emergence of consumer quad-rank DDR5 memory kits isn't a coincidence but the result of the introduction of CUDIMMs, memory modules equipped with a client clock driver (CKD). Just as the CKD enables memory modules to reach very high frequencies, the chip also enhances the stability of quad-rank memory, which uses four banks of memory chips. Running a large amount of memory puts excessive stress on a processor, which is why quad-rank memory didn't exist before for everyday users until the arrival of CUDIMMs.

Origin Code won’t be the only memory vendor to offer quad-rank CUDIMM memory kits. For instance, Adata had already partnered with MSI to demonstrate quad-rank CUDIMM functionality several months ago, showcasing modules running at DDR5-5600 speeds. It’s reasonable to expect that additional brands will soon jump on the quad-rank CUDIMM bandwagon.

So far, demonstrations from Origin Code with Gigabyte and Adata with MSI all share one common factor: Intel's Z890 platform. It is reasonable to speculate that quad-rank CUDIMMs will likely not work on AMD's current platform since it hasn't fully embraced CUDIMMs. The chipmaker has confirmed that the AM5 socket supports CUDIMMs, but never said when the feature will arrive. However, the current speculation is that full CUDIMM support could arrive with Zen 6.

However, the biggest challenge quad-rank CUDIMM memory kits and consumers face is the persistent global memory shortage. Memory prices have already skyrocketed, and there appears to be no end in sight. That alone is enough to kill any momentum that quad-rank CUDIMMs can generate.

AMD is bringing a new automatic memory overclocking feature out, dubbed EXPO Ultra Low Latency (ULL). The new tool promises a 13% uplift in average performance across over 30 games compared to JEDEC standard speeds for DDR5, as well as a 4% uplift compared to standard EXPO, at least according to AMD’s internal benchmarks. The company hasn’t said when ULL will be available, but it has several memory partners lined up to support the feature.

We don’t know much about how EXPO ULL works, and more specifically, where AMD is finding improvements compared to standard EXPO. Despite that, AMD shared some broad benchmarks looking at EXPO ULL performance on a Ryzen 7 9700X CPU in over 30 games. AMD didn’t share resolution (presumably 1080p) or settings details for the titles, outside of the fact that they were tuned for “best performance.” You can see the full configuration in the gallery below.

Compared to JEDEC-standard DDR5-5600 CL46, AMD shows EXPO running at DDR5-6000 running 9% faster, and DDR5-6000 CL30 with EXPO ULL running 13% faster. Looking at 1% lows, AMD claims a performance improvement for EXPO and EXPO ULL of 11% and 15%, respectively. AMD didn’t clarify the CAS Latency of the standard EXPO memory, but it notes that it tested at CL28, CL30, and CL36 for both EXPO and EXPO ULL.

AMD simply says that EXPO ULL is “coming soon” from major memory partners, including G.Skill, Kingston, Klevv, Lexar, Origin Code, TeamGroup, V-Color, and XPG.

There are still several lingering questions about ULL, which we hope to learn more about on the ground at Computex 2026. Presumably, ULL isn’t a feature that’s being backported to older EXPO DIMMs, but rather a new standard moving forward. AMD hasn’t confirmed that’s the case, however.

We also don’t know what ULL is actually doing to find 4% extra performance compared to standard EXPO. Given the wide swath of games and CAS Latency settings AMD tested at, there’s a good chance ULL won’t show a benefit in all games. We should see better uplifts in smoothness, however, as evidenced by AMD’s 1% low results.

Tom’s Hardware is on the ground in Taipei for Computex, where we’ll be meeting with AMD to learn more about EXPO ULL, along with the newly-announced Ryzen 7 7700X3D and reintroduced Ryzen 7 5800X3D.

If you thought DDR5 was already too expensive right now, Cooler Master and G.Skill have a surprise in store for you. The two manufacturers are partnering up to make "MasterDIMM" — a new line of DDR5 memory kits that come with active cooling and a promise of temperatures that are up to 15 degrees cooler than conventional RAM. These sticks feature a thick heatsink with a fan built-in to emulate a blower-style cooler you see in some GPUs. There are no pricing or availability details yet, but it's not hard to imagine these kits, made for "demanding next-gen systems," will be even pricier than regular DDR5.

MasterDIMM will be properly shown off at Computex 2026 in just a few days, so expect more information then. For now, we know that these are high-end UDIMMs (desktop) that will push the envelope for DDR5 RAM in terms of style. The design of these sticks is very classy, sporting a black and gold aesthetic with part of the copper heatsink visible on the front, along with the fan on the other end. Naturally, they're a little larger than regular DIMM's, so motherboard compatibility remains to be seen.

There are two RGB strips running along the top, also flanked by gold accents, and the whole thing looks oddly similar to a fancy M.2 SSD. The RAM itself is made by G.Skill, while the heatsink is designed by Cooler Master. MasterDIMM will offer speeds up to 6,000 MT/s at CL26 latency with AMD EXPO, or up to 8.400 MT/s on Intel platforms via XMP 3.0. Capacities will scale up to 128GB at the top-end through 64GBx2 configs.

The companies claim the fan inside is whisper-quiet, delivering optimal cooling at just 35 decibels. That's the same noise level as a library. The heatsink and fan combo can drop temperatures by up to 15 degrees Celsius, which would be a remarkable improvement if proven true in testing. Keep in mind that DDR5 RAM, in general, is already rated for operation at up to 95°C, but it stays between 70-80°C in most cases.

Now, this is not the first time someone has put a massive cooler, or even two fans, on some RAM, but it's the most mainstream version of such a combination yet. Both G.Skill and Cooler Master are huge names in the PC hardware industry, so it'll be interesting to see how well this product does. Of course, that depends on pricing, and DDR5 prices are still out of control despite some semblance of the AI boom slowing down as of late.

More than a decade ago, Corsair tried to actively cool memory with its Vengeance Airflow modules, and vendors have tried to fit their DIMMs with creative heatsinks forever. Last year, we even tested a Silverstone AIO that could attach optional fans to itself to cool your memory and SSD.

In late 2024, China-based ChangXing Memory Technologies (CXMT) began producing DDR5 modules aimed at the consumer market. Since then, the company has even laid out a roadmap that currently puts its max DDR5 capabilities at 8,000 MT/s across 16 Gb and 24 Gb densities. Fast forward to today, and we're finally seeing Chinese DRAM in a mainstream product, more specifically, a Corsair Vengeance DDR5 16GB stick purchased in China by @wxnod, running at 6,000 MT/s with CL36 speeds.

We can see the "CMK5X16G3E60C36A2-CN" part number, where "CN" denotes it's a China-exclusive kit. It's still certified for both Intel XMP and AMD EXPO (since it runs beyond JEDEC speeds), and we also see the rest of the specs printed on the label, such as the timings and operating voltage. There are also "UKCA" and "CE" signs that indicate this kit meets European and British standards for sale in those regions.

The post above shows CPU-Z screenshots clearly revealing that the DRAM powering this kit is from CXMT and not one of the big three memory makers: Micron, Samsung, or SK Hynix. All of those companies are busy selling out their entire production lines to data centers instead, so it makes sense that Corsair is shifting around its suppliers. CXMT might seem like an unusual choice, but the company is well-positioned for this transition.

See, unlike the major DRAM manufacturers, CXMT doesn't even possess the latest cutting-edge tools to produce memory for hyperscalers. The company isn't tied to any data center contracts, so it has, relatively speaking, empty production lines just waiting for customers. And that clientele CXMT seems to be targeting is regular consumers left in the dust by the rest of the RAM industry.

Until now, CXMT has only really sold to local businesses and lesser-known brands, but being featured in a Corsair kit marks a major shift in the landscape. Even if this kit is exclusive to Chinese markets, it's still made by one of the biggest names in consumer memory — a name that people trust. Besides, most customers won't actually check what factory their DRAM chips are coming from as long as the specs seem up to par.

Speaking of which, we're looking at a DDR5-6000 CL36 kit, which is not the fastest, but it's plenty for gaming and daily tasks. There's generally less than 5% difference between a CL30 and CL36 kit at 6,000 MT/s, so if you're saving a lot of money going for the slower latency, it might be worth it in some cases, such as, you know, a RAM shortage. That brings us to the main question: Is this RAM actually cheaper?

There was no explicit mention of a price, so for all we know, Corsair is sourcing cheaper memory from CXMT but still selling it at the same inflated rates. If supply from Samsung, SK Hynix, and Micron is tight, it makes sense that DRAM bought from those companies would be expensive, but CXMT-made DDR5 should be significantly more affordable for it to matter and make an actual dent in the market.

Moreover, there would be concerns about how stable these modules are and whether they're fit for overclocking. Since a brand like Corsair is backing them up, a customer would expect it to perform just as well as any other Corsair kit. Another post from the same OP shows a similar KingBank-branded DDR5-6000 kit overclocked to 8,000 MT/s with 44-56-56-128 timings at around 1.5V, so there's clearly some potential here.

PC memory manufacturer Team Group has agreed to settle a class action lawsuit to the tune of $1.1 million over allegations it advertised deceptive speeds for its DDR3, DDR4, and DDR5 memory products purchased in the U.S. between May 3, 2020, and April 8, 2026. Similar to a recent case involving G.Skill, the lawsuit claims that consumers were led to believe that the advertised speeds on Team Group’s memory kits could be achieved out of the box without requiring BIOS tweaks or overclocking profiles.

It was alleged by the plaintiffs that the company marketed its RAM kits using rated speeds that could only be achieved after enabling XMP or EXPO memory profiles via the motherboard BIOS/UEFI menu. Team Group has denied all allegations of wrongdoing and says that its “products were appropriately labeled and performed as represented.”

An individual can claim as part of the settlement class if they purchased Team Group DDR3, DDR4, or DDR5 memory products while living in the United States between May 3, 2020, and April 8, 2026. The settlement only applies to individual consumers, while purchases made directly by a business, such as a company, LLC, corporation, or partnership, do not qualify for compensation. However, if you personally bought the memory as an individual consumer, you may still qualify even if you later used the product for work or business purposes.

As there is no fixed amount out of the total settlement fund of $1.1 million, the money will be divided among every individual who submits a valid claim. Payments will be made based on how many eligible Team Group DRAM products each person claims. The settlement also clarifies that one may claim compensation for up to five memory products per household without providing proof of purchase, while claims beyond that require supporting documentation.

Eligible customers can head to the Claim Hub website and follow the instructions carefully to file an official claim. You can also submit an objection or exclude oneself from the lawsuit completely. The deadline for the claim is currently set for July 7, 2026.

Earlier this year, G.Skill settled a similar $2.4 million lawsuit involving its DDR4 and DDR5 memory products. Plaintiffs argued that advertised speeds above JEDEC defaults required additional BIOS adjustments and overclocking settings that were not clearly disclosed on packaging or product pages. Most memory kits for modern PC platforms ship with conservative default speeds based on JEDEC standards, while higher advertised frequencies, such as DDR5-6000 or DDR5-7200, require users to manually enable XMP or EXPO profiles. The lawsuit argued that average consumers may not realize these additional steps are necessary to achieve the marketed performance levels.

G.Skill was also required to change its packaging and be clearer about overclocking and BIOS adjustments as part of its agreement. The Team Group settlement doesn't seem to include any such provisions and is rather purely offering a payout to affected buyers.

75 years ago this week, on May 11th, 1951, MIT electrical engineer Jay Forrester filed the patent application for coincident-current magnetic core memory, a technology that became the dominant form of random-access storage in digital computers for two decades.

Granted as U.S. Patent 2736880 in February 1956, Forrester's invention evolved from MIT's Project Whirlwind, where unreliable vacuum-tube memory was failing to meet the demands of real-time Cold War air defense.

Whirlwind began in the mid-1940s as a U.S. Navy flight simulator project but pivoted toward real-time digital computing. The machine needed to track aircraft in flight, and the electrostatic storage tubes Forrester initially used broke down constantly.

Forrester's solution used tiny rings of ferrite material, each about the diameter of a pencil lead, strung on a grid of copper wires. Sending current through two intersecting wires simultaneously magnetized a specific ring in one direction for a "1" or the other for a "0." The coincident-current technique allowed a small number of wires to address millions of bits in three-dimensional arrays. His graduate student, William Papian, built the first prototype in October 1950, and the first full core memory bank went into Whirlwind on August 8th, 1953.

This demonstrated that the underlying tech worked, and Whirlwind subsequently became the prototype for the SAGE air defense network, which operated 23 computer-controlled radar installations across the United States and one in Canada, and remained operational into the 1980s.

While Forrester applied for the patent in 1951, it took five years for it to be granted, and a series of legal battles soon followed. RCA engineer Jan Rajchman had filed a similar application eight months earlier, and Harvard researcher An Wang had separately patented a different core memory technique that IBM purchased in 1955 for $500,000. Wang used the proceeds to expand Wang Laboratories.

IBM then spent years challenging Forrester's broader patent. MIT responded with forensic thoroughness, according to its archival records, tracing purchase orders, examining telephone bills and travel vouchers, and analyzing lab notebooks to establish Forrester's priority. RCA eventually withdrew its claims, and in 1964, IBM settled for $13 million, the largest patent payout in history at the time. Forrester personally received $1.5 million.

Forrester left digital computing in 1956, the same year his patent was granted, joining MIT's Sloan School of Management, where he founded the field of system dynamics. He died on November 16th, 2016, at 98.

Celebrating the 20th anniversary of the Republic of Gamers (ROG) brand, Asus has unveiled the company's first memory kit, which will compete with the best RAM on the market. Announced at the ROG Day 2026 event, the ROG 幻刃 (meaning "Phantom Blade" in English) 48GB DDR5 RGB 20th Anniversary Edition memory kit will retail for $880, turning it into a luxury item that's even more expensive than a GeForce RTX 5070 Ti graphics card, which starts at $829 when in stock.

Late last year, there were rampant rumors within the technology community that Asus might venture into the competitive memory market. At the time, the company publicly denied these rumors, and for good reason, because there was a misunderstanding about the speculation. Many thought Asus would magically spin up a fabrication facility and begin manufacturing and selling memory. It was quite the opposite. The rumor was about the possibility of the company offering Asus-branded memory modules, likely under the ROG gaming brand, to the retail market.

Asus's move is reminiscent of what Gigabyte does with its Aorus line. The latter sells many Aorus-branded DDR5 and DDR4 memory kits on the retail market. The tactic would allow Asus to expand its ROG ecosystem and leverage its already-renowned brand to retain existing customers and attract new ones in segments that the company previously didn’t compete it.

Asus’s first ROG memory kit comes in an impressive 48GB capacity, packaged as two matching 24GB memory modules. The specifications of the memory kit are pretty solid. It operates at DDR5-6000 with tight CL26-36-36-76 timings at 1.45V. Like many enthusiast memory kits, the ROG memory kit supports both AMD EXPO and Intel XMP profiles. Additionally, Asus has introduced a unique secondary profile that is exclusive to ROG motherboards to set this kit apart from standard offerings.

Users can activate “ROG Mode” directly in the BIOS of a compatible ROG motherboard to push the memory kit to DDR5-8000 with 36-48-48-110 timings at a DRAM voltage of 1.40V. It's just Asus's way of giving its customers an easy one-click method to overclock the memory kit. Logically, this is possible because the memory kit leverages SK hynix's high-quality M-die integrated circuits, which are great for overclocking.

Over the years, Asus has strategically partnered with several major memory manufacturers to offer Asus-branded memory products under both the ROG (Republic of Gamers) and TUF (The Ultimate Force) lineups. Notably, Asus developed the recently announced ROG memory kit with Biwin. Building on a collaborative approach, Asus has significantly expanded its ROG-certified memory program to include 14 carefully selected partners authorized to produce and market ROG-themed memory kits. The growing network of partners includes some of the most trusted brands in the memory industry, such as Corsair, G.Skill, Kingston, and Adata.

The ROG DDR5-6000 C26 48GB memory kit will retail for $880. For perspective, the most affordable GeForce RTX 5070 Ti graphics card commands a retail price of $829, when it is available, and the Trident Z5 Neo RGB DDR5-6000, which offers similar capacity and specifications, is currently listed for $799.99 on Amazon. Asus’s ROG kit is up to 6% more expensive than a contemporary high-end graphics card and approximately 10% pricier than the competition.

The substantial price premium is something we've grown accustomed in the ongoing global memory shortage. Furthermore, Asus products are famously associated with what enthusiasts refer to as the “Asus Tax." The ROG DDR5-6000 C26 48GB memory kit, which comes with a limited lifetime warranty, will launch in late June. Given its exclusivity and the supply constraints, it probably won't have a problem getting off the hardware shelves.

It's a bad time to build a PC right now, given all the component shortages and political tensions that seemingly never leave sight of uncertainty. Bad times call for desperate measures, and that's precisely the window of opportunity that scammers are waiting to bank on. As such, reports of fake DDR5 memory circulating in Asian markets have begun to pop up, with some scammers replacing entire modules with counterfeit, hollow plastic chips. You can see the clever counterfeits by expanding the tweet below.

The post above from Japanese user TAKI shows laptop DDR5 memory (SODIMMs) with some of these fake chips. The sticker on the RAM says it's a Samsung stick, but the modules are clearly from SK Hynix. They also look a bit weird with the edges looking abnormally rounded off, exposing a white material around the perimeter. If you look closely, one of the ICs on the PCB is also knocked out of place, suggesting these components have been dropped on the board rather prematurely.

Looking closer at one of the DDR5 modules, it's clearly been shaved off; that explains the white perimeter. But there's nothing inside because these chips are just made of plastic or fiberglass with no circuitry inside. The second giveaway then becomes clear — since these are literally just bits of plastic, the SK Hynix part number markings are also fake, printed on top to make the RAM look convincing.

These counterfeit memory kits are common on secondhand marketplaces, such as Mercari and Yahoo Auctions, and some are listed as broken. The description on one of these listings outlines a whole story about where these sticks come from, and that the buyer shouldn't purchase them expecting a functional product.

People looking to make a quick buck would pounce on such ads, or even worse, scammers would buy these lots to actually resell as working sticks to unsuspecting customers. And these are SODIMMs with no heatspreaders, so you can actually see the part numbers and likely make out the fact they're not authentic. For desktop memory that does come with heatsinks, you're basically out of luck until you actually test it.

The sellers peddling these fake DDR5 modules also accept no returns, which is common for "as is" purchases. Another possibility is that these sticks are coming from Amazon bait-and-switch scams where people buy an authentic product, swap it for a fake (or nothing at all), and return it, from where it ends up in a returns warehouse. It then gets picked up by a larger seller who might sort and sift through the lot to identify valuable items like RAM and put them up on the aftermarket.

Ultimately, the point remains that you should be extremely vigilant when buying used products, especially in times like these. If a deal is too good to be true, it most likely is. Purchase from reputable stores and vendors that accept returns or refunds, or at least those who'll exchange faulty items for you. While memory is the most price-hiked PC hardware category right now, similar scams run through GPUs and even CPUs.

Make sure to tally any product numbers with authentic ones you find online and thoroughly test the components to ensure they work. The latter practice should be enough to spoof out any bad actors, but try to secure a warranty as well, just in case.

Retro Games Limited (RGL) has announced that the release of TheA1200 computer has been delayed by almost six months. The Commodore Amiga-emulating full-size A1200-like design has been up for pre-order since Nov 2025, and retro-hungry fans were anticipating deliveries of the first units on June 16, 2026. In a social media post on Wednesday, RGL announced that the machine won’t be available until December 4, 2026. It blamed a combination of “global chip shortages and rising plastic production costs” for the setback. However, the firm insists that TheA1200 specs and pricing will not be adjusted.

In some ways, we are surprised that the release plans for TheA1200 have been impacted by the global chip crunch. An original Amiga 1200 had such puny specs compared to systems nowadays – it used a 14 MHz processor, 2MB (not GB) of RAM, and zero fixed storage, just a floppy disk drive. We would assume RGL is going to create TheA1200 using the magic of emulation and a cheap Allwinner/Rockchip Arm SoC backed by 512MB to 1MB of RAM. However, the tendrils of the AI boom are now beginning to spread and strangle tech production beyond the high-end RAM, NAND, and processor niches.

RGL also notes that TheA1200 OS “isn’t yet where it needs to be.” This aspect of the product is currently functional, it is explained, but for the best possible Amiga experience, the dev team needs more time “to get it right.”

Obviously, delays like this are frustrating to folks who have already endured a protracted pre-order period. An extra (almost) six months of patience is quite a lot to ask. With this in mind, RGL has prepared an FAQ regarding the delays. We’ve embedded the full blurb above, but key takeaways are that pre-orders will stand unless you are fed up enough to cancel, the price isn’t going to change, and the machine specs will not be adjusted. Furthermore, TheA1200 is “fully on track for release on 4^th December 2026,” insists RGL.

We visited the U.S. distributor’s TheA1200 product page on Amazon.com and saw that the machine is still up for pre-order at $189.99 at the time of writing. However, the release date hasn’t yet been updated; it still says “June 16, 2026” is when TheA1200 will become available.

TheA1200’s price looks quite competitive for a bit of retro fun in 2026, with the entry price of even basic computers and SBCs ratcheting up lately. The pre-order value looks even better compared to RGL’s TheA500 Mini, which is listed at $218.95. This well-reviewed Mini Amiga can also play A1200 games, but it doesn’t have a functional keyboard, and thus lacks the real Amiga feel and presence.

If you're building projects based on Nvidia Jetson modules, don't panic; it's fairly likely that you're working with the newer Orin and Thor modules. If, however, your project is based around the older Xavier or TX2 boards, then we have some bad news: Nvidia has apparently brought forward its EOL timelines for those families of Jetson products due to the RAMpocalypse making LPDDR4 harder to get. That's according to Connect Tech, a Canadian supplier and system integrator for AI systems that says Nvidia has moved these devices to Non-Cancelable, Non-Returnable (NCNR) status due to the change. (Shout out to CNX Software for spotting this.)

The specific devices affected at Connect Tech are the Jetson TX2 NX, the Jetson TX2i (all SKUs), the Jetson AGX Xavier 32GB Industrial variant, and the Jetson Xavier NX in 8GB and 16GB versions, but the supplier actually says that Nvidia has marked all TX2 and Xavier models as NCNR on its side. It also says that final purchase orders for those modules must be in by July 1st, existing purchase orders convert to NCNR on July 15th, and the last time it will ship any orders featuring those products is July 15th next year.

Strictly speaking, those timelines are from Connect Tech, not Nvidia itself, but the company does say that they are "based on Nvidia timelines." In any case, it's not really that surprising; all of these are older models, with the TX2 having been introduced in 2017 and the Xavier parts originally introduced in 2018, though some of the specific variants included arose as late as 2021.

Given that, it's probably time to start thinking about moving to newer hardware if you're working with these parts. Nvidia's Orin NX is close to a drop-in replacement for the older Xavier NX platform as long as you are not relying on more specialized I/O configurations, and the overall form factor and power envelope remain in the same class. Moving from AGX Xavier to AGX Orin is even more straightforward since both use the same 699-pin connector family, although power delivery and thermals still need to be validated.

These are hardly the first casualties of the RAMmageddon, but they do complicate the idea that only DDR5 is under pressure. DDR4 pricing has skyrocketed due to lacking supply since memory manufacturers moved on to DDR5. What is happening here is not a simple shortage in the traditional sense but a reallocation of manufacturing capacity. Memory vendors are prioritizing higher-margin parts for AI accelerators, particularly HBM and newer DDR5, and that shift pulls capacity away from legacy nodes that produce LPDDR4.

That leaves older embedded platforms in an awkward position. They depend on memory that is no longer the focus of the industry, yet they still require long lifecycle guarantees that newer consumer products do not. When supply tightens, those platforms are often the first to be pushed into constrained ordering terms, and NCNR status is usually the earliest visible signal.

Seen in that light, this is less about an abrupt discontinuation and more about a market reality finally catching up with aging hardware. The TX2 and Xavier families were already living on borrowed time, and the current memory crunch simply accelerates a transition that was going to happen anyway. For developers and integrators, the takeaway is that if a design still depends on LPDDR4-based Jetson modules, the window to secure supply is closing, and migration to Orin is no longer just a performance upgrade but a matter of long-term viability.

Reports of YouTube freezing browsers and consuming enormous amounts of RAM began spreading across Reddit and browser forums late last week, with developers now pointing to a bug in the platform's interface code that may be trapping browsers in an endless layout recalculation loop. What's emerging is that there is a runaway interface bug buried inside the platform's video controls.

Users across multiple browsers, including Firefox, Brave, and Microsoft Edge, have described videos stuttering, tabs becoming unresponsive, and systems slowing to a crawl while watching YouTube. Some users reported the individual YouTube tabs consuming more than 7GB of RAM.

Many of the initial reports blamed YouTube's ongoing war against ad blockers or recent browser updates, as the issues seemed to have first been noticed after a Firefox update. However, similar reports from Brave and Edge users have increased the spotlight on YouTube.

Following investigations, reportsMozilla's emerging from Mozilla’s open-source bug-tracking system, Bugzilla, suggest YouTube's frontend interface logic is the main culprit. Developers investigating the issue appear to have narrowed the problem down to the flexible menu container located directly beneath the video player — the section containing controls such as Like, Dislike, Share, and other interaction buttons.

Button peek-a-boo loop

According to comments related to the investigation, the interface repeatedly checks whether all buttons fit within the available horizontal space. If the controls overflow, the system hides one of the buttons to free space. However, hiding the button changes the container's width, immediately creating a new problem.

Once the button disappears, the available width appears enough for the interface to believe there is room again, causing the hidden button to reappear. The buttons then overflow once more, forcing the interface to hide the button again. The cycle repeats continuously at extremely high speeds.

While the visual behavior itself may appear minor, the consequences inside the browser can be far more significant. Modern browsers constantly recalculate page layouts whenever interface elements change size or position. If a webpage repeatedly triggers those recalculations thousands of times per second, the browser can become trapped in what developers often call layout thrashing or a reflow loop.

That forces the browser to continuously recompute layout geometry, redraw interface elements, and update rendering states, rapidly consuming CPU resources and memory. A user shared screenshots on Reddit showing CPU cores pinned near maximum utilization while YouTube tabs became nearly unresponsive. Others reported browser-wide slowdowns severe enough to temporarily freeze entire systems.

Mozilla developers are reportedly still investigating the issue, though no broadly confirmed fix appears to exist yet. The fact that both Firefox-based and Chromium-based browsers appear to experience similar problems further supports the suspicion that the issue may originate primarily with YouTube. For now, the exact root cause remains unofficial; neither Google nor YouTube has publicly confirmed the source of the problem.

AMD's long-awaited EXPO 1.2 has finally arrived on AM5 motherboards. The new and improved memory overclocking technology will allow vendors to release fast memory kits for AMD that rival the best RAM. Renowned third-party AMD utility developer 1usmus and hardware leaker chi11eddog have detailed the improvements in EXPO 1.2. However, according to the former, the most substantial benefit will likely be unlocked only with AMD's next-generation Zen 6 processors. The new version also adds support for three Chinese RAM vendors.

One of AMD EXPO 1.2's enhancements appears to be support for module geometry. While 1usmus didn’t provide extensive details, module geometry refers to the arrangement and structure of memory chips on a memory module. The feature may be related to HUDIMMs, a recent innovation that suppresses one of the 32-bit sub-channels in DDR5 memory modules, aiming to offer a cost-effective solution to the ongoing memory shortage.

AMD EXPO 1.2 introduces support for MRDIMMs (Multiplexed Rank Dual In-line Memory Modules), designed to deliver substantially higher bandwidth and greater memory capacity. These memory modules are for server and data center platforms, though, so they won't be available on consumer AM5 platforms.

Sadly, EXPO 1.2 still only partially supports CUDIMMs (Clocked Unbuffered Dual In-line Memory Modules) and CSODIMMs (Clocked Small Outline Dual In-line Memory Modules). These modules leverage a CKD (Client Clock Driver), a small IC that maintains signal integrity and stabilizes memory operation at higher frequencies. It's a key component to help DDR5 continue to scale the frequency ladder.

However, EXPO 1.2 retains bypass mode for CUDIMMs, treating them as standard memory modules without fully leveraging the CKD's benefits. There is mention of CKD bypass modes, but we don't yet have any detailed information on them. According to 1usmus, the current AGESA 1.3.0.1 firmware does not yet fully support CUDIMMs. According to 1usmus, AMD is likely laying the groundwork for full CUDIMM support in preparation for the upcoming Ryzen 10000 processors (codenamed Olympic Ridge) that will leverage AMD's new Zen 6 execution cores.

$4.99 thrift store GPU from r/pcmasterrace

AMD has been making significant behind-the-scenes improvements on EXPO 1.2. One of the standout features introduced is the new Ultra Low Latency (ULL) mode. It reportedly reduces memory latency. Hardware leaker chi11eddog claims that enabling ULL mode can decrease memory latency by an impressive five to seven nanoseconds on a typical DDR5-6000 memory kit.

Other improvements that EXPO 1.2 brings to the table are new fields for further fine-tuning memory that overclocking enthusiasts will appreciate. The new memory timings include tREFI, tRRDS, and tWR, along with options for VDDP voltage.

In response to the ongoing global memory crisis, AMD has proactively expanded memory compatibility by adding support for three Chinese memory manufacturers: RAMXEED Limited Conexant, Rui Xuan (formerly known as Rei Zuan), and Fujitsu Synaptics. These brands are popular in China, but it's unlikely you'll see their memory kits in the Western markets. However, consumers who purchase Chinese memory kits from overseas via platforms such as AliExpress can expect full compatibility thanks to AMD EXPO 1.2.

Asus has already started deploying beta firmware with early support for AMD EXPO 1.2 across its 800-series motherboard lineup. Many of the company's X870E and X870 motherboards can access the new firmware; however, the B850 motherboards still have to wait a little while longer. Other motherboard manufacturers will likely follow suit very soon.

AMD EXPO 1.2 is a great sign of commitment to continue improving the AM5 platform. However, we won't get to experience its full potential until Zen 6 hits the market, which should be sometime between late 2026 and early 2027.

Dr. Semiconductor is back in his shed, and this time he’s checking whether Joe Public can DIY themselves out of the DRAM crisis. In the video embedded below, you can see the good doctor go through the semiconductor process steps required to make an array of memory cells in a backyard shed cleanroom. This is the “first time ever RAM has been made at home,” boasts our hero.

RAMageddon isn’t the only issue affecting PC DIYers and the industry in general. Dr. Semiconductor mentions the AI-industry-fueled RAM price disruption being driven by the big three players (but there are others) not being able to keep up with demand. We are seeing similar effects on storage, GPUs, and some reckon CPU supplies will also begin to be impacted.

With the existing industry incapable of addressing consumer RAM needs at attractive prices in 2026, the TechTuber asks, “I turned a shed in my back yard into a class 100 semiconductor cleanroom… but the question is, can I make my own RAM?”

After the intro, Dr. Semiconductor gives a brief description of how computer memory works, and how it is largely made up of huge arrays featuring oodles of capacitors and transistors.

Moving on to the practicalities of the job at hand, the good doctor begins by snipping a couple of silicon chips from a large sheet. This is the beginning of the preparation and cleaning stage of the chipmaking process.

Next up, we move to the initial patterning stage. A layer of oxide is built on the surface of the silicon in a high-temperature furnace. It is estimated that this layer is 330nm thick. On top of this layer, an adhesive layer and photoresist film are applied. UV exposure projects a design mask onto this newly created surface, which allows a developer solution to wash away the areas that have been hit by the light rays.

The source and drain of the transistors in the design are formed in the following steps. This involves more layer etching, doping exposed silicon to make it highly conductive, then annealing the chips to push the doping agent deeper.

Several more carefully targeted deposition and erosion steps later, we are ready for the metallization of the silicon chip. A tiny stencil is used to accurately spray the sample with aluminum, the excess stripped away, and the fully layered and formed chip is at last ready for some tests!

Checking the results

The freshly fabricated DRAM cells are so small that wires can’t be used to hook them up to test machinery by the DIYers. Micromanipulator probes are precisely positioned instead. The good news is that Dr. Semiconductor was pleased with his finished DRAM chips, as cells were measured to offer a hobbyist sweet spot of 12pF capacitance.

At the end of the video, the doc teases that he’s going to build on this significant, though admittedly small-scale, achievement. He’s looking to prepare a much larger array of finished memory cells and says that they will be prepared to “hook up to a PC.” Stay tuned for the PC-scale practical implementation, folks.

We reported on Dr. Semiconductor's creation of this garden shed-based cleanroom back in March.

A couple of days ago, Intel, TeamGroup and ASRock came together to unveil the "HUDIMM" spec for DDR5 RAM. HUDIMM use a single 32-bit subchannel instead of populating a 64-bit wide bus with two 32-bit channels. This effectively cuts bandwidth and capacity in half but allows for cheaper DDR5 that uses less ICs per stick. Today, new testing done by HKEPC, with the help of Asus, confirms exactly that — HUDIMM will incur an almost 50% bandwidth penalty, reducing performance significantly.

First things first, HKEPC did not get their hands on an actual retail HUDIMM kit manufactured by TeamGroup; instead, they used standard DDR5 RAM but taped half of the contact points. This allowed for one of the 32-bit subchannels to become unrecognizable, hence simulating HUDIMM. A member of Asus' R&D team has already tried this before the announcement, and we mentioned it in our previous coverage.

This new testing is more substantiated and was done on an Asus ROG Maximum Z890 Extreme motherboard, using an Intel Core Ultra 9 285K. The outlet "matched the BIOS that supports HUDIMM modules" because, unlike a retail 1x 32-bit stick, the modified 2x 32-bit RAM's SPD will still tell the memory controller it's supposed to have a 64-bit wide bus. The PC will fail to initialize (POST) otherwise and be stuck with training errors.

We start with a single rank 16 GB 7,200 MT/s stick that showed up as 8 GB. In AIDA64, it achieved read speeds of 32,447 MB/s, write speeds of 25,195 MB/s, and copy speeds of 26,894 MB/s, with an 87.7 ns latency. In contrast, the same stick when untaped hit 58,913 MB/s read, 48,800 MB/s write, and 52,648 MB/s copy speeds. That's essentially double the throughput across the board, but latency was the same at 85.7 ns.

As expected, disabling one of the 32-bit subchannels slashes the numbers in half pretty consistently. You get to build cheaper sticks that require only 4 ICs instead of the usual 8 for a 16 GB DIMM, but it clearly comes at a cost. The standard 16 GB stick is almost at 60 GB/s of effective bandwidth while the simulated 8 GB HUDIMM stick only reaches 32 GB/s. That's the kind of discrepancy you'll notice.

Switching gears to a dual channel setup, HKEPC put 2x 16 GB 7,200 MT/s sticks on the motherboard, which showed 32 GB in the standard config, but only 16 GB when taped. The same story follows; half of the bandwidth is gone when simulating HUDIMM. We drop from 106 GB/s read speeds to just 58 GB/s, the write speeds go from 93 GB/s to 48 GB/s, and the copy speeds fall from 97 GB/s to 51 GB/s. The latency remained identical.

The HUDIMM numbers here basically match the performance of a regular 16 GB stick running in single channel, which is to be expected. It's simple math, really. Across the board, we're just halving the bandwidth and capacity just to be able to make cheaper DDR5. The performance hit is significant, but since HUDIMM is aimed at budget gamers and business users, perhaps the tradeoff will be worthwhile for some.

One claim from the announcement that HKEPC didn't check was asymmetric dual channel support — combining HUDIMM with regular DDR5 with 2x 32-bit subchannels is supposed to drastically improve performance. ASRock said that using an 8 GB HUDIMM stick with a standard 16 GB stick nets more bandwidth than a single 24 GB UDIMM (despite having the same capacity). The 24 GB stick on its own is apparently more expensive to manufacture, too, so this is a sort of "best-of-both-worlds" pitch.

40 years ago today IBM was in the news for becoming the first computer company to make use of 1-megabit memory chips. Thus, the megabit memory era began with an American company and its Vermont fab leading the way, pushing back stubbornly against the seemingly unstoppable Japanese takeover of the memory market.

IBM’s 3090 (Sierra series) mainframe computers were the first to adopt this new high-density memory. However, the New York Times reported the occasion as “a rare, if fleeting, moment of glory,” as it thought the Japanese semiconductor industry would inexorably rise beyond its already impressive 75% market share.

The NYT’s take contrasted with IBM’s triumphant tone. “This is a signal of our semiconductor technology leadership,” said IBM SVP, Jack D. Kuehler, at the time. He went on to emphasize how these DRAM chips were built in the USA. Some of the newspaper’s cynicism came from the fact that it already knew the likes of Fujitsu, Hitachi, Mitsubishi, NEC, and Toshiba were busy sampling their own 1-megabit DRAM chips. Once they were satisfied and moved them to mass production, it was expected the Far East tiger economy would roar back to pole position.

If we turn the clock back to 1986, most computing devices in use might have packed memory chips of the 64 kilobit variety. The state-of-the-art Japanese memory tech at the time was churning out 256 kilobit memory chips. In that context IBM’s 1-megabit chips, fabricated on a 1.2 micron process, were very impressive, bringing a leap in both density and efficiency.

The arrival and establishment of 1-megabit memory chips would enable memory makers to produce 30-pin SIMMs with 1MB RAM capacity, using eight to nine chips in a single-side configuration. Such SIMMs will be very familiar to users of home and personal computers from the mid-1980s to the mid-1990s. Additionally, you would be able to use the same SIMMs in printers, on sound cards, and even graphics cards like the Tseng ET3000 / ET4000, Trident TVGA 8800 / 8900, and Cirrus Logic GD542x series.

Thanks to the AI boom, component prices have skyrocketed in the past few months, leading constituents to come up with creative ways to fight the RAMpocalypse. ASRock has previously introduced a motherboard with both DDR4 and DDR5 slots to help alleviate the crisis, but now it's teaming up with Intel and TeamGroup to launch "HUDIMM" — a new type of DDR5 RAM that can potentially help you save money.

DDR5 memory (UDIMM) typically uses two 32-bit subchannels per stick, requiring enough chips to populate a full 64-bit wide bus. This constitutes a single rank. HUDIMM, or Half Unbuffered DIMM, uses just a single 32-bit subchannel instead, effectively halving the bandwidth and density of the RAM. This allows for cheaper sticks that use fewer modules and are basically "half-rank" in nature.

ASRock has partnered up with TeamGroup to produce some of these first HUDIMM sticks, which are already working on Intel 600, 700 and 800-series motherboards. ASRock is also making HSODIMM, which is basically the same concept but for SO-DIMM (laptop/mobile) instead of U-DIMM (desktop). The company is targeting entry-level users across both segments that don't need the highest performance, or capacity.

According to ASRock, "two sub-channel (2*32-bit)" architecture is beneficial for high-capacity single DIMM module, however, it is not so practical for current PC market." That being said, HUDIMM has asymmetrical dual-channel support at the BIOS level. This should allow you to mix and match different DDR5 RAM to circumvent the single subchannel limitation and achieve higher bandwidth, while still maintaining compatibility.

For instance, an 8 GB HUDIMM stick paired with a 16 GB UDIMM stick will run in proper dual-channel mode with at least 3x 32-bit subchannels active — one from the HUDIMM and two from the standard UDIMM. This Frankenstein 24 GB setup apparently provides better bandwidth than a single 2x 32-bit 24 GB stick, which would be more expensive to manufacture anyway. Though ASRock's press material shows a 90 ns latency, which would be considered high by any modern standards.

Following ASRock's announcement, Asus also chimed in with its own HUDMM showcase on a ROG Maximum Z890 Apex motherboard. A member of the R&D team took two regular 24 GB DDR5 RAM sticks and just taped half of the contact points, effectively disabling half of the ICs. Instead of showing 48 GB in the BIOS, these taped sticks showed only 24 GB.

The company didn't say whether it was partnering up with TeamGroup as well to add official HUDIMM support, but the fact that an engineer acknowledged it could signal something is in the works. If Asus hops on board the standard, an industry-wide push for this would be imminent, and we could genuinely see more affordable DDR5 soon. There is no word on availability or pricing from any side, however.