Save for the occasional deal, GPU prices are so high these days that they might even get you wondering if you couldn't just roll your own. As it happens, renowned hardware hacker Matthias Balwierz (more commonly known as Bitluni) elected to do precisely that, enlisting the help of a total sum of 8,192 RISC-V microcontrollers (MCUs) for this enterprise.

He originally planned to create a display of some sort, but after careful consideration regarding costs and difficulty, he elected to solder an RGB LED directly to each microcontroller chip, effectively turning his GPU into a GPU-and-monitor combo, if we're getting technical. Going for a 1920x1080 resolution would require over two million chips, so Balwierz aimed for a final-project resolution of 320x200 with 64,000 chips — familiar figures to anyone who played games in the DOS days.

Balwierz opted to make boards with 16x32 "pixels" each, in a circular arrangement reminiscent of the Cray-1 supercomputer, though with far more blinkenlights. His option to directly solder each light onto each MCU was borne out of budgetary restrictions, as the addressable-RGB variant would also prove too expensive.

For this initial stage of the project, Balwierz stuck with "only" 8,192 chips, though he made plans for the whole shebang. Perhaps the most impressive figure is the power draw, at a total of 2,161 W, or around 655 amps at 3.3 V. Each MCU only draws 10 mA, a figure that looks innocent enough until you do the actual math. To feed power into the beast, he enlisted the help of a Corsair WS3000 ATX power supply unit along with custom-designed converters to go from 12 V to 3.3 V at high current.

As for the chips themselves, they're QingKe CH570 RISC-V units, each with a 32-bit RISC-V CPU with a limited instruction set, running at up to 100 MHz. The diminutive chip contains an impressive amount of hardware, including a USB controller, a 2.4 GHz transceiver, and Bluetooth 5.0 LE support. Each of these set Balweirz back $0.13, once again a measly looking figure that will add up to well over $8,000 in chips alone for the final 320x200 array. Each set of 32 MCUs is controlled by a beefier CH32V unit.

As habitual, Balwierz custom-designed every single PCB, power delivery circuit, interface board, and testing board himself. This is apparently the first time he's designed a six-layer PCB, and he actually ran up against design limits of the JCLPCB service. He originally planned for the whole project to use immersion cooling, but decided against that for the time being due to environmental and cost concerns, though he did spec out the appropriate acrylic container for it.

Balwierz goes over each chapter of the process in detail in his video, and one of the most clever bits is how he made a 3D-printed three-prong fork-like tool to program each MCU. He then took said tool and attached it to the 3D printer's carriage, and used a Python script issuing direct G-code to the printer to precisely aim it at each MCU in the board.

It'll take a while before this is a functional CPU that can threat Nvidia, but we're looking forward to seeing Doom displayed on it. Also, it's kind of funny how one guy in a lab designed a better power delivery mechanism than the firm's 12V-2x6 connector... using just parts from AliExpress.

Unlike many startups producing nothing but vaporware, Jim Keller's TensTorrent has actually delivered impressive-looking RISC-V AI accelerators, but there could be some trouble brewing. Starting with firmware version 19.5.0, the firm has now chopped the tensor core count on Blackhole p150 cards from 140 to 120, affecting both new cards and existing units already in customers' hands.

The news was apparently communicated to customers via email, with the same wording present on the firmware update's GitHub page. Tenstorrent isn't elaborating on why the change was made, leaving existing and potential buyers scratching their heads. The quote follows:

The statement seems to raise more questions than answers. Twenty out of 140 cores is about a 14% chop. When comparing the old and new Blackhole p150 product pages on Tenstorrent's site, the raw compute capacity is 774 vs 664 TFLOPS, a change that appears substantial, especially in the context of multi-card setups like the QuietBox. And yet Tenstorrent claims that in practice, for one card, this should amount to a 1-2% performance delta when using TT-Metalium, a low-level developer kit that operates close to the hardware.

One user in the company's Discord server raised the question of whether the SDK even fully utilizes the underlying hardware to begin with, while another remarked that changing the core grid layout and timing can negatively affect existing, tested code. It's not that existing users have much of a choice, either: update the firmware and lose cores, or lose out on new features of a nascent, in-development product. Predictably, jokes about the 14% core chop were plentiful.

One can but hypothesize as to why the change was needed. Perhaps Tenstorrent wasn't getting good yields for their Blackhole chips, but that would be an odd twist given that they're reportedly manufactured on a 6-nm process, pretty mature technology by today's standards. Tenstorrent is already in conversations with multiple 2-nm chip manufacturers for its next generation of products, but in the meantime, has yet to deliver its upcoming two-chip, 64 GB Blackhole p300.

Tenstorrent's existing lineup of Blackhole products comprises AI accelerator cards for workstations and developers wanting to run AI models locally. They're actually reasonably priced, as the p150 model can deliver 664 TFLOPs and comes with 32 GB of VRAM for just $1,399, or about one-third the price of a single RTX 5090, while theoretically delivering several times the performance. The cards can be wired together to pool VRAM, too, and the chips combine CPU and tensor cores on the same die, bypassing a number of limitations of conventional designs.

It's reasonable to expect some turbulence, as it's exceedingly difficult to create an entire new AI accelerator plus its software, on an unusual architecture, with an unusual chip layout. TensTorrent's current aim at small-scale AI accelerators for small businesses, laboratories, and individuals may well carve out a niche of the market and offer dividends in the long run, so long as turbulence is kept to a minimum.

Chinese retail giant Alibaba is planning an initial public offering (IPO) for its chip manufacturing business, T-Head, as reported by Bloomberg. The move will initially give employees partial control of the business, although the timing of the IPO has yet to be revealed. When it happens, though, it will generate capital for Alibaba that it will be able to use to further invest in T-Head’s production and design hardware. With Alibaba having previously pledged more than $53 billion on AI infrastructure and development over the next few years, it will need serious capital to meet its aims.

It’s not clear at this time how much of a valuation T-Head would reach, but it is one of a handful of companies in China looking to develop AI inferencing hardware to help rival international companies like Nvidia. Although Chinese firms aren’t likely to be able to develop the chips necessary to handle AI training, inferencing hardware is certainly possible. Alongside Cambricon and Moore Threads, T-Head has the potential to become one of the major AI hardware suppliers in China.

With its own major cloud services and AI ambitions, Alibaba is looking to position itself as one of the key players in the space that China has pledged to invest 10s of billions of dollars over the coming years.

China’s Amazon

The parallels between Alibaba and major Western technology and retail companies are stark. Like Amazon, Alibaba is one of the world’s largest retail firms for both direct-to-consumer sales and business-to-business transactions. For over 16 years, it has run a highly successful cloud computing business, too, offering e-commerce management, data processing, and data mining services.

Like Amazon’s more recent endeavours to develop its own chips and hardware, Alibaba has been at it for several years too. It announced its first AI accelerators in 2019 and subsequently provided rentable access via cloud platforms.

In a post-ChatGPT world, both companies have also developed their own AI services, which they offer through their cloud platforms. Amazon has also invested in other AI firms like Anthropic and potentially OpenAI. Alibaba is going after the consumer space in a slightly different way, though, pushing its Qwen AI in its main mobile app in November last year, with plans to turn it into a personal assistant that anyone can access. It most recently tied in its online shopping and travel services with Qwen, expanding its capabilities.

It plans to turn that into a one-stop app for AI services and features, and with its T-Head IPO, it’s looking to build out the hardware development arm of its business to take the lead in domestic AI accelerator manufacturing, too.

Powering the third wheel

T-Head Semiconductor was founded by Alibaba in 2018 and traditionally develops RISC-V-based CPUs and integrated circuits for enterprise SSDs. However, it has also developed AI hardware and accelerated that in 2025 with a new range of AI accelerators, which some Chinese media sources claimed were able to compete with Nvidia’s H20.

Although those claims have yet to be tested, T-Head is making a name for itself in the chip design space and is competing in a huge market served by very few players. It falls far behind industry leaders like Huawei and Cambricon in terms of its capabilities and market reach, but with Alibaba’s financial backing, its manoeuvred into a position as a third option for Chinese companies looking to adopt AI technology without falling foul of government mandates to use primarily domestic chips.

Bloomberg highlights how T-Head has been aggressively recruiting visual AI and chip-making experts of late, and it’s just signed a deal with China’s number two wireless carrier to use its Pingtouge AI accelerators. Those chips will be used alongside those from other Chinese AI chip developers, MetX Integrated Circuits and Biren Technology, showcasing that there is serious competition within this burgeoning industry. And why not, with so much potential money on the table?

Hoping for history to repeat

After Alibaba completes its restructuring to provide employees with partial ownership and then moves to an IPO for T-Head, it will be hoping for a successful repeat of what happened with fellow tech companies working on IPOs in recent months.

Chinese GPU manufacturer, Moore Threads, often called “China’s Nvidia,” completed its long-awaited IPO in December 2025, after a mere five years in operation, and secured a valuation as high as $40 billion, raising more than $1.1 billion in capital from share sales.

This is occurring while the Chinese market is seemingly consolidating around major chip players. Fellow Chinese retail giant, Baidu, is also hoping to complete a successful IPO in Hong Kong for its chip design company, Kunlunxin. It’s hired banks ahead of what it hopes will be upwards of $2 billion in investment for the company. Although no official announcement has been made yet, the IPO was confidently filed earlier this month.

If Alibaba can replicate this kind of success with an IPO for T-Head, it will secure strong funding to expand the company’s capabilities and allow it to compete more favorably with Chinese industry giants like Huawei and Cambricon, even if it may remain a smaller player for some time to come.

GlobalFoundries this week announced that it had reached a definitive agreement to acquire Processor IP Solutions business from Synopsys, its second acquisition of a CPU IP business in less than a year, and its fifth major acquisition in one-and-a-half years. Synopsys's portfolio of ARC and RISC-V processor IPs will complement GloFo's technologies obtained with the MIPS acquisition. This will enable the company to broaden its offerings across automotive, embedded, industrial, wearables, and other emerging applications, which benefit from standard CPU IP and customized accelerators.

GlobalFoundries gets more CPU IP

As a result of the deal, GlobalFoundries will take over processor IP assets that include ARC-V (RISC-V), classic ARC CPU cores, DSP, and NPU IP that use the ARC framework. It will also benefit from the associated software ecosystem, such as the ARC MetaWare development toolkits. The acquisition also includes Synopsys's ASIP Designer and ASIP Programmer toolchains, which automate the development and deployment of application-specific instruction-set processors (ASIPs) that integrate base CPU cores with bespoke instructions, pipelines, or accelerators immediately supported by a compiler.

The terms and conditions of the deal, expected to be closed in the second half of the year, have not yet been disclosed. Both companies have committed to a coordinated transition plan to ensure existing Processor IP customers continue to receive uninterrupted support, so Synopsys's customers will not be forced to migrate to other technologies due to the acquisition.

Upon closing the transaction, all the assets that are part of the Synopsys Processor IP Solutions (we will call it 'ARC' for the sake of simplicity) as well as 'expert teams' will become a part of MIPS, which operates like a separate company within GlobalFoundries (e.g., it can work with other foundries and license IP to companies that do not use GF's manufacturing services).

As a result, MIPS will control a vast range of IPs, such as MIPS RISC-V cores, as well as IP from Synopsys, which includes ARC-based CPU, DSP, and NPU cores, as well as ARC-V offerings featuring the RISC-V instruction set architecture (ISA).

RISC-V & ARC

With RISC-V, GlobalFoundries can offer an extensible ISA, open-source software, and compatibility with a growing ecosystem. The value of ARC lies in its configurability, which enables developers to build ASIPs, processors with a custom ISA and features. Building system-on-chips (SoCs) with RISC-V general-purpose cores and bespoke ARC accelerators could provide an edge for GlobalFoundries' customers, as the technology benefits from burgeoning market penetration.

For those unfamiliar with ARC, these processors use the 16/32/64-bit ARCompact compressed ISA originally developed in the 1990s for graphics processing purposes. Instead of a fixed microarchitecture, ARC allows designers to add custom instructions, bespoke accelerators, and modify datapaths while the software toolchain (compilers, debuggers, profilers) automatically adjusts to match the hardware. This makes ARC fundamentally different from general-purpose CPUs, as the final ASIP is shaped around a specific workload rather than optimized to run a wide range of applications. As a result, ARC excels in applications where specialization matters more than peak performance. As a result, specially-tailored Application-specific instruction set processors (ASIPs) can offer higher performance-per-watt efficiency and predictable performance than SoCs based on off-the-shelf CPU cores and IPs.

Building its own IP ecosystem

The goal set by GlobalFoundries is to 'deliver a comprehensive processor IP suite' that spans from RISC-V general-purpose cores to special-purpose DSPs, NPUs, and other accelerators. Ultimately, this will increase its customer lock-in through lower adoption barriers, a faster-time-to-market, accelerated development of custom silicon, as well as IP licensing and embedded software.

Once GlobalFoundries integrates the Processor IP Solutions into MIPS, it will inevitably align ARC and MIPS designs with its own process technologies, packaging options, and verification/qualification flows, which is something that must be done to accelerate development of custom solutions as well as speed up time-to-market.

This alignment will reduce incompatibilities between architectural intent and physical implementation, as both will come from a singular company. As a result, GlobalFoundries' customers will be able to pick up a wide range of silicon-proven IP blocks, integrate them into their own differentiating IP (or even develop one based on the ARC ISA from scratch) into their upcoming chip, and greatly fast-track their path from Register-Transfer level design (RTL), to mass production while taking advantage of power, performance, and area-optimized IPs with predictable yields.

For embedded designs with a very long lifecycle, that predictability, along with cost-cutting and time-to-market, matters more than chasing leading-edge density or the highest performance. In fact, many fabless companies among those building custom silicon for emerging applications lack internal resources to assemble a full compute stack from scratch. Traditionally, these customers would license CPU IP from one vendor, DSP or AI blocks from another, and only then begin mapping the design onto a foundry's process technology. With TSMC's OIP and Arm's portfolio of IPs, the path to silicon is rather straightforward, as the ecosystems are vast.

With the takeover of MIPS and ARC, GlobalFoundries can offer its clients a bundle of silicon-proven IPs from one shop, which means even faster time to market, greater flexibility with RISC-V and ARC, and perhaps a lower price. While GlobalFoundries avoids explicitly marketing this as vertical integration, the technical implication the company revealed earlier this year in an interview with Tom's Hardware made clear: processor IP, software tools, and fabrication are now coordinated inside a single organization.

Changing the role of pure-play foundry

GlobalFoundries is deliberately reshaping its role in the semiconductor value chain by combining its manufacturing capability with in-house processor IP — built around RISC-V and the newly acquired Synopsys ARC portfolio, as well as silicon photonics and optical connectivity enabled by Advanced Micro Foundry (AMF) and InfiniLink acquisitions — to offer customers a tightly integrated path from architecture to silicon. The strategy targets a wide range of emerging applications across a variety of verticals, including automotive, embedded, industrial, and physical AI markets.

For GlobalFoundries's customers, the ARC + RISC-V combination provides a standards-based ISA for general-purpose compute, paired with the ability to introduce workload-specific instructions and accelerators without negotiating changes with the owner of a proprietary architecture, such as Arm.

This might open GlobalFoundries some additional business opportunities with newly established fabless chip designers with limited budgets, clients with requirements for sovereign chip designs without massive upfront investments, and customers operating under export controls and looking for a partner with policy-resilient IP and manufacturing. Keeping in mind location of GloFo's fabs in Asia, Europe, and the U.S., the strengthened IP portfolio makes even more sense.

What's next for GlobalFoundries?

With two CPU IP-related acquisitions in less than a year, we can now only wonder what is next for GlobalFoundries: will it focus on integration of MIPS and ARC into its organization, or it will pursue more M&A activities?

If the company is looking forward to more acquisitions, the most logical thing to do would be to pursue adjacent technologies, enabling M&A that deepens its platform without turning it into an Integrated Device Manufacturer or putting it in conflict with customers or partners. Among the most probable scenarios for the company would be to obtain controller, connectivity, and security IP to further simplify the development of chips for its clients. Another move could be acquiring an IP focused on advanced packaging.

A less likely move is to purchase an accelerator or domain-specific IP to address specific applications. So far, GlobalFoundries has focused on general IP, which can be deployed broadly.

Another option for the company could be taking over software or middleware assets for automotive, embedded, or industrial applications. Software certification is a long process, so offering customers a solution that includes both silicon-proven hardware and functionally safe software and middleware could produce another layer of opportunities for GlobalFoundries.

A calculated expansion

The acquisitions of MIPS and ARC represent a calculated expansion of GlobalFoundries's value proposition that extends beyond silicon manufacturing production and now spans to the level of physical IP and software.

To a large degree, GlobalFoundries is about to become a platform partner for its clients as it not only makes and packages chips, but also defines IP that is inside. This strengthens GloFo's competitive position against other foundries as well as against TSMC, whose OIP ecosystem serves the same purposes as GlobalFoundries's in-house IP.

For customers, the ARC + MIPS integration will offer faster time-to-market, deeper customization, increased efficiency, and safeguards against geopolitically motivated limitations.

The RISC-V ecosystem might still be a nascent one, but it's definitely starting to take shape. You can now order the Milk-V Titan full-featured Mini-ITX motherboard kit with an integrated Ultra-RISC UR-DP1000 CPU (RISC-V), all with standard hardware, and ready to roll.

Although this isn't strictly the first such offering, it's one of the few on the market that combines complete feature, out-of-the-box usability, and a reasonable price. The motherboard is a pretty plain Mini-ITX model, but in a good way. It supports up to 64 GB of DDR4 RAM in a dual-channel setup at up to 3200 MT/s, and has one M.2 slot, USB-A and USB-C ports, Gigabit Ethernet, and BMC (out-of-band management) ports.

The only notable omission is integrated graphics, as you'll have to make use of the available PCIe x16 slot to plug in your own graphics card. As RISC-V is for practical purposes an entirely new platform, graphics driver support is still somewhat spotty. Older Radeons (7000 series and previous) are known to work well, but this very statement is likely to change quite quickly.

There are no audio ports on the board, but that's unlikely to be a deal-breaker as you can always use USB audio devices. Besides, these boards are aimed at development work anyway. In fact, there are even 3-pin UART and USB-C connector for CPU debugging purposes. The idle power consumption is apparently pretty high at 14 W, but that's not likely to matter for development purposes.

As for the Ultra-RISC UR-DP1000 CPU itself, it's an eight-core setup with four two-cluster cores, each loaded with 4 MB of L3 cache, for a total of 16 MB. It is fully compliant with the RVA22 profile (RVA specs are CPU instruction sets), and there's support for the RVA23 except for the V (vector) extension. It's important to note this CPU supports hardware virtualization, so you can use hypervisors with it. And, of course, at only 2 GHz on a nascent platform, keep your performance expectations tempered.

You can run Ubuntu on the The Milk-V Titan right out of the box. The kit available is for preorder now at Arace Tech. The standard price is $329 or 288€, but there's a $50 discount for preorders, so make that $279 in practice, a pretty reasonable amount. And since it uses DDR4 RAM, you might be able to get the memory for less than the entire board.

Qualcomm has acquired Ventana Micro Systems, a RISC-V CPU specialist whose engineers have spent several years pushing the open instruction set toward high-performance server and edge designs. The deal brings Ventana’s core CPU talent in-house just as Qualcomm is broadening its compute ambitions well beyond smartphones, balancing Arm-based designs with a growing interest in RISC-V as AI continues to disrupt, well, everything.

Qualcomm is in the middle of expanding Oryon, its custom CPU architecture that debuted in Snapdragon X Elite and underpins its push into data center accelerators, Windows PCs, and automotive compute platforms. Adding Ventana gives Qualcomm direct access to a mature RISC-V design team, rather than relying solely on internal experimentation or third-party IP, and it does so as customers across all markets are asking questions about long-term architectural flexibility.

RISC-V as a hedge

Qualcomm executives have said publicly that the company is capable of building high-performance CPUs on RISC-V if it chooses to do so. The Ventana acquisition turns that assertion into reality, as the company’s work has focused on scalable, out-of-order RISC-V cores with features expected in enterprise-class CPUs, including coherent interconnects and virtualization support. Folding that expertise into Qualcomm reduces the friction of turning RISC-V from a research effort into a deployment-ready option.

None of this is to say that Qualcomm is abandoning Arm, though. The duo’s relationship remains central to its smartphone and PC businesses, and Arm-based cores will continue to dominate shipping volumes in the near term, but roadmap alignment and geopolitical risk have become more visible considerations for large chipmakers. RISC-V offers a way to diversify architectural exposure without committing to a clean break, something that, for Qualcomm, offers value even if RISC-V volumes ramp gradually.

Ultimately, RISC-V has moved past its early microcontroller roots and is now entrenched in storage controllers, networking gear, industrial controllers, and an increasing share of automotive silicon. Competition within the ecosystem is intensifying as major vendors seek influence over extensions, toolchains, and software support. Owning a credible in-house CPU team gives Qualcomm leverage in those conversations and reduces dependence on external roadmaps.

Industrial and automotive momentum

Outside consumer devices, RISC-V is becoming mainstream in areas that value long product lifecycles and architectural stability, like industrial control systems and embedded platforms. Qualcomm has been expanding its presence in these markets through its IoT and industrial compute groups, and deeper RISC-V capabilities will help it compete against vendors that already ship large volumes of RISC-V silicon.

The automotive sector is following a similar trajectory, with software-defined vehicles driving consolidation of compute functions into centralized platforms. Automakers in particular are increasingly sensitive to licensing costs and supply chain risk — as we saw during the chip shortage of 2020 to 2023, and more recently with the Nexperia-China drama — which is leading them to prepare RISC-V-based compute platforms for systems like infotainment and ADAS.

Speaking of China, customers in the region who are facing uncertainty around access to certain Arm-based products have become more receptive to RISC-V as a neutral alternative. That demand shift has contributed to a rapid increase in RISC-V investment and product development across the region. While Qualcomm does not need to tailor products exclusively for China to benefit from that momentum, having strong RISC-V capabilities lowers barriers to participation in markets where openness and local control are being increasingly prioritized.

Where Oryon and AI intersect

One of the more interesting implications of the deal is the intersection of RISC-V flexibility and AI workloads. As AI inference spreads across edge and embedded devices, the line between CPU, GPU, and NPU responsibilities is blurring. In certain classes of workloads, especially control-heavy or sparsely parallel tasks, a well-designed CPU can approach accelerator-class efficiency when paired with the right extensions and memory architecture.

RISC-V’s modularity makes it very attractive in this context, with custom extensions allowing vendors to tailor cores for specific inference patterns without waiting for standardization cycles. Qualcomm’s Oryon CPUs are already positioned as high-performance general-purpose cores optimized for AI-adjacent workloads. Integrating Ventana’s RISC-V expertise creates room for parallel exploration, where RISC-V designs could complement Oryon in products that prioritize consolidation of compute over raw peak throughput.

This does not imply that Qualcomm plans to replace NPUs with RISC-V CPUs, or to collapse its architecture stack into a single design. Instead, it reflects a broader industry trend toward heterogeneous compute, where CPUs, GPUs, and accelerators are selected based on workload characteristics. Having both Oryon and RISC-V options will give Qualcomm more freedom to potentially tune that mix across product categories.

A maturing ecosystem

Skepticism around RISC-V has often centered on ecosystem maturity, particularly software and tooling, but that argument is becoming harder to sustain. RISC-V is now present across cloud and edge computing, and while mass-market consumer devices remain dominated by Arm and x86, many emerging application domains already include RISC-V deployments. Toolchains and OS support have improved substantially, driven by commercial demand, but they still remain behind what’s available for Arm and x86.

Qualcomm’s decision to acquire Ventana, however, fits nicely within RISC-V’s general upward trajectory, apparently timed to coincide with expanding addressable markets and a clearer picture of customer demand. Ventana’s team brings immediate engineering expertise, while Qualcomm provides scale, manufacturing access, and integration experience across multiple industries.

In that sense, the acquisition can be seen as Qualcomm preparing for the inevitable and ongoing reshaping of compute requirements by AI. Customers will seek greater control over their silicon roadmaps in response, making architectural flexibility a competitive offering. By deepening its RISC-V capabilities while continuing to invest in Oryon and Arm-based designs, it appears that Qualcomm hopes to pivot around that transition with fewer bottlenecks.

Edit 2, 12/17/2025 3:45am PT: Sipeed has contacted Tom's Hardware to dispute the researchers' claims. Sipeed says the microphone was listed on a Wiki page for the LicheeRV Nano at launch. The LicheeRV Nano is a development board used for the product. However, the microphone was not listed or mentioned directly on the NanoKVM Wiki page at launch. Instead, Sipeed linked to a document that detailed the LicheeRV Nano and its microphone. Sipeed has added a direct reference to the microphone on the NanoKVM Wiki page.

In response to the issues, Sipeed has now added a note about the microphone to its retail listing for the 'Developer Edition' models that include it. Sipeed has also notified its authorized distributors to update their listings. "Sipeed also notes that while the text description was missing on original retail pages, the high-resolution product images provided always clearly displayed the microphone component. There was never any intentional concealment of its existence," the company says.

Sipeed also states that the project used a phased open-source approach and is now fully open source since February 2025. The firm says it has addressed the community's security concerns. Tom's Hardware cannot independently verify that all security issues have been addressed, but we are aware that multiple issues have been confirmed as corrected by other media outlets.

Edit 12/8/2025 5:25 pm PT: Adjusted article to reflect that the report was published in February.

In February, a Slovenian security researcher published an analysis of Sipeed’s NanoKVM that raised far-reaching concerns about the €30-€60 ($35-70) remote management device. Alarmingly, the researcher’s teardown showed the device shipped with a catalogue of security failures and an undocumented microphone that could be activated over SSH. After reporting the issues, many of those problems have been addressed over the intervening months.

The compact RISC-V board, which arrived on the market last year as a budget alternative to PiKVM, offers HDMI capture, USB HID emulation, remote power control, and browser-based access to a connected PC. It is beginning to show up in IT environments precisely because it requires no software on the target machine and can operate from BIOS to OS install.

The researcher says the device’s software stack exposes weak points from the moment it boots. Early units arrived with a pre-set password and open SSH access, a problem the researcher reported to Sipeed and which the company later corrected. The web interface still lacks basic protections, including CSRF defence and any mechanism to invalidate active sessions.

More troubling, the encryption key used to protect login passwords in the browser is hardcoded and identical across all devices. According to the researcher, this had to be explained to the developers “multiple times” before they acknowledged the issue.

The NanoKVM’s network behavior raised further questions, as it routed DNS queries through Chinese servers by default and made routine connections to Sipeed infrastructure to fetch updates and a closed-source binary component. The key verifying that component was stored in plain text on the device, and there was no integrity check for downloaded firmware.

The underlying Linux build was also a heavily pared-down image without common management tools, yet it included tcpdump and aircrack, utilities normally associated with packet inspection and wireless testing rather than production hardware intended to sit on privileged networks.

All this, paired with the discovery of a tiny surface-mount microphone, should make any user suspicious of the device’s true intentions. The researcher said the microphone is not documented in product materials, yet the operating system includes ALSA tools such as amixer and arecord that can activate it immediately. With default SSH credentials still present on many deployed units, the researcher demonstrated that audio could be recorded and exfiltrated with minimal effort, and streaming that audio in real time would require only modest additional scripting.

Thankfully, because NanoKVM is nominally open source, community members have begun porting alternative Linux distributions, first on Debian and later Ubuntu. Reflashing requires opening the case and writing a new image to the internal microSD card, but early builds already support Sipeed’s modified KVM code. Physically removing the microphone is possible, though the component’s size and placement make it a fiddly job without magnification. Sipeed has since addressed many of the security concerns around the device. However, the general consensus is that users should flash these devices to custom Linux distributions to mitigate potential issues, and many reviewers currently recommend Sipeed products for use in homelab environments.

A hardware hacker has installed a Minecraft server on a cheap smart lightbulb. Vimpo shows how this feat was completed and demonstrates the server working in a brief video, embedded below. Key to this achievement was the bulb’s BL602 RISC-V-powered microcontroller.

Hardware hacksawing

Vimpo begins their quest by taking a knife to the unfortunate AliExpress-bought LED bulb. Oldies like me still find it jarring to see a lightbulb popped open without terrible consequences – but LEDs don’t need to reside in a delicate vacuum.

Next up, our intrepid hacker desolders the microcontroller from the center of the bulb, where it sits surrounded by an array of LEDs. Remember, this lightbulb's microcontroller is powered by a BL602, which features a single RISC-V core, running at up to 192 MHz, and partnered with 276KB RAM, 128KB ROM, and sporting a modicum of I/O.

We then see the detached microcontroller with wires soldered individually to its headers. Vimpo confirms the connections are fine by quickly hooking up the wires to turn the lightbulb on and off.

A simple USB-to-serial adapter board is soldered to these connections for a steady, usable interface. We now have a ‘system’ ready, with monitor and input peripherals, upon which to run a Minecraft server.

Software shenanigans

Of course, hardware is only half of Vimpo’s solution. To get a Minecraft server operating on the limited resources of a smart bulb, the hacker has put together a system running an implementation dubbed Ucraft. You can find Ucraft code resources on GitHub, plus a guide to building the server system on a Linux machine.

Ucraft is gloriously compact, with a “binary size is approximately 46K bytes without authentication and 90K bytes with the authentication library,” says Vimpo. “Memory usage varies based on the number of active players. In the worst-case scenario with 10 players, heap usage will be around 70K bytes with authentication and 20K bytes without authentication.” However, the hacker is first to admit that Ucraft “lacks most, if not all, features of the vanilla server.”

In some ways, Minecraft is becoming the new Doom, used as a springboard for outlandish projects. Minecraft is now a leading light in inspiring hardware and software hackers to push the boundaries of the computing world. For example, in recent months, we’ve seen a 5-million-parameter ChatGPT AI model in Minecraft, as well as Minecraft running entirely in 8MB of VRAM on an old GPU, and another Minecraft server implemented using 63-year-old COBOL code.

ARM has some competition in the reduced-complexity chip space, and it's gaining ground quickly. RISC-V International plans to announce that silicon on the open-standard has reached 25% market penetration later this month, according to an announcement posted to LinkedIn. Market analysts SHD Group are primed to announce their findings on RISC-V market share at the RISC-V Summit North America.

Linus Torvalds, the creator and lead developer of Linux, has publicly dismissed a RISC-V code contribution from a Google engineer as “garbage.” The code was sent as a pull request for inclusion in the Linux 6.17 kernel on Friday, but has been roundly rejected by Torvalds for both its poor quality and for being late. Those are two cardinal sins in pull requests, and misdemeanors that have clearly ignited the Linux creator’s infamously short fuse.

In response to the RISC-V Patches for the 6.17 Merge Window, Part 1, from Google’s Android team member Palmer Dabbelt, Torvalds didn’t pull any punches. “No. This is garbage and it came in too late. I asked for early pull requests because I'm traveling, and if you can't follow that rule, at least make the pull requests *good*,” insisted Torvalds. “This adds various garbage that isn't RISC-V specific to generic header files. And by "garbage" I really mean it. This is stuff that nobody should ever send me, never mind late in a merge window,” he brusquely elaborated.

The comment from Torvalds wasn't just bile. He went on to give some examples of where the RISC-V pull request went astray. But even in this mostly reasoned response, Torvalds couldn’t resist adding a few more barbs.

'You're on notice'

At the 2025 RISC-V Summit in China, Nvidia announced that its CUDA software platform will be made compatible with the RISC-V instruction set architecture (ISA) on the CPU side of things. The news was confirmed during a presentation during a RISC-V event. This is a major step in enabling the RISC-V ISA-based CPUs in performance demanding applications.

The announcement makes it clear that RISC-V can now serve as the main processor for CUDA-based systems, a role traditionally filled by x86 or Arm cores. While nobody even barely expects RISC-V in hyperscale datacenters any time soon, RISC-V can be used on CUDA-enabled edge devices, such as Nvidia's Jetson modules. However, it looks like Nvidia does indeed expect RISC-V to be in the datacenter.

Linux developers have managed to get Steam running on RISC-V-powered platforms. Moreover, some big-name games like The Witcher 3 and Crysis are now playable (h/t GamingOnLinux). Please note, this achievement isn’t due to something as momentous as the Steam Client being ported to the RISC-V architecture. Rather, the Steam client and some games can run on RISC-V due to the increasing quality of the felix86 emulation project.

The Felix86 blog mentions that the emulator has just started delivering playable AAA Windows games, so this is a major breakthrough for the project. Additionally, the devs praise the ‘user-friendliness’ of Felix86, making it quick and easy to get running with your games. Other notable improvements have come to AppImage support and file system emulation.

GamingOnLinux got some tastier, fresher morsels in an email sent by the developers. “We even got the Linux Steam client working, which means games that have Steam DRM can be played on RISC-V with felix86,” wrote a jubilant developer.

If you want to read more and keep up to date with this project’s latest developments, keep an eye on the Felix86 GitHub page, too.

RISC-V, the underdog already powering billions of devices

RISC-V is something of an underdog in the processor architecture race in 2025, but there are glimmers of light, with increasing amounts of sparks. In November 2023, we covered forecasts that there would be more than 16 billion RISC-V-powered devices in the wild by 2030. More recently, we have seen reports that Nvidia will get on the RISC-V train, and China is pushing the adoption of the open-source ISA.

The biggest success for RISC-V, so far, has been its adoption by embedded systems and IoT gadgets, so these chips are already in billions of devices, with little fanfare. Now this platform is edging more into the view of enthusiasts and tinkerers with projects like the DC-ROMA, Milk-V Megrez board, and even Framework, looking for some RISC-V action.

RISC-V is snappier than the dragon

Developer NSG650 has succeeded in his attempt to get “Linux running in Excel.” The GitHub-hosted and aptly named LinuxInExcel project was uploaded to the cloud-based developer platform earlier this week, and updated with input support just yesterday.

Getting Linux to run within the confines of Excel is the latest in a long line of Excel coding gymnastics, which might only be rivaled by those boasting of running various incongruous software gems inside PDFs. And yes, we have already seen Linux running inside a PDF.

If you’ve read about these kinds of software feats previously, you'll know there is perhaps more than an ounce of trickery in running complex software like Linux within the confines of a spreadsheet application.

Developer NSG650 openly admits that his achievement leans heavily on a RISC-V emulator built by fellow GitHubber cnlohr. It also makes use of a Microsoft VBA macro to call the emulator in the DLL, which “gets the output and writes it into the cells in the spreadsheet.”

Using this emulation layer and software vector to run Linux takes a toll on performance – and stability doesn’t seem to be the best, either. NSG650 confirms LinuxInExcel is “very buggy,” but seems to be happy enough with achieving the software milestone, as it stands. It was “done mostly for fun,” says the Bangaluru-based developer in the GitHub readme.

Despite exhibiting little intention to refine his LinuxInExcel project, it has already seen an important improvement. Specifically, NSG650 thanks YouTuber Enderman (who hit our headlines in 2023 by tricking ChatGPT into generating Windows 95 keys) added interactivity by implementing input support.

Last month, a team of Google security researchers released a tool that can modify microcode of AMD's processors based on the Zen microarchitecture, the Zentool. While this is a security vulnerability, for some, this is an opportunity; Members of the Chinese Jiachen Project are running a contest with an aim to develop a microcode for AMD's modern Zen-based CPU to make them execute RISC-V programs natively. The ultimate goal could be building an ultimate RISC-V CPU using already available silicon. 

x86 is a complex instruction set computer (CISC) instruction set architecture (ISA) developed some 48 years ago. However, internally, modern x86 cores rely on proprietary engines running a reduced instruction set computer (RISC) ISA to handle complicated instructions. The internal RISC ISAs are not documented, but they should generally be similar to well-known RISC ISAs, such as Arm or RISC-V. CPU microcode is a low-level layer that translates complex x86 CISC instructions into simple RISC-like internal instructions the CPU hardware executes. CPU microcode is only supposed be modifiable by CPU vendor, but sometimes this is not the case and apparently some parts of AMD's Zen 1/2/3/4 microcode can be changed using the Zentool. 

The Jianchen Project members want to find someone, who can modify AMD's Zen CPU microcode on a modern processor — say, an EPYC 9004-series — to execute RISC-V binaries. The patch is expected to either enable direct execution of RISC-V programs or significantly boost their runtime speed compared to emulation using the same hardware. The work must be tested using RISC-V versions of benchmarks like Coremark or Dhrystone. A complete submission includes binaries or source code, configuration files, dependencies, and test instructions. If only binaries are submitted before the deadline on June 6, identical source code must be added via pull request later. The winner will get ¥20,000 (approximately $2,735). 

AMD's EPYC 9004-series and similar processors offer performance and core counts not achievable on currently available RISC-V-based processors, so executing proprietary RISC-V programs on EPYCs is a plausible idea. However, microcode is designed to fix internal bugs rather than replace the front-end ISA completely and it is even unclear whether the microcode can be completely re-written, people over at Ycombinator noted. 

Back in the mid-2010s, AMD planned to offer both x86-64 and Armv8-A Zen CPUs (something recently recalled by Mike Clarke, AMD's chief architect), so it is highly likely that there was a microcode for the Zen 1 microarchitecture that supported an Aarch64 front-end ISA. That said, Zen 1 CPUs could feature multiple microcode layer 'slots,' one supporting x86-64 and another Aarch64. We doubt this is the case though as modern CPUs have very thorough hardware performance optimizations that include hardwire optimizations between the microcode and the rest of the core. AMD has hardly ever developed a microcode that supports Aarch64 or RISC-V for Zen 2/3/4 processors and therefore the microcode layer of these CPUs is strictly x86-64 and there is hardly enough microcode space for re-writing them from scratch. 

"This is not achievable," one commenter named Monocasa wrote. "There is not enough rewritable microcode to do this even as a super slow hack. And even if all of the microcode were rewritable, microcode is kind of a fallback pathway on modern x86 cores with the fast path being hardwired decode for x86 instructions. And even if that were not the case the microcode decode and jump is itself hardwired for x86 instruction formats. And even if that were not the case the micro-ops are very non-RISC." 

One commenter criticized the contest format, suggesting it is a way to get complex work done for less than $3,000 pay. 

In general, while the concept of re-writable microcode is an interesting one and stimulates discussion about alternative CPU designs, multi-ISA support, and low-level optimization, it does not look like the contest will achieve the stated goal. Perhaps, re-writing (or rather re-compiling) a RISC-V program or two for x86 CPUs makes more sense?

DeepComputing has developed a reputation as a pioneer of small form factor RISC-V PCs, being the first company to bring a RISC-V laptop to the market in 2022. The company is now accepting pre-orders for its newest product, a mini AI PC that can replace the mainboard of the Framework Laptop 13.

The new device comes with two names: either the "DC-ROMA RISC-V AI PC" or the "DC-ROMA RISC-V Mainboard II for Framework Laptop 13" according to its listing page. The mainboard is one of many members of DeepComputing's DC-ROMA line, a family of SFF/laptop PCs all built on the RISC-V architecture set. It is also DeepComputing's second replacement mainboard for the Framework Laptop 13, with both the RISC-V AI PC and its predecessor functioning either inside the Framework or on its own as a stand-alone unit.

The specs of the DC-ROMA RISC-V AI PC are slightly mysterious. The device will be based on the "world's first RISC-V chiplet dual-die connected AI SoC." The mystery SoC will hold a 64-bit 8-core RISC-V CPU running at up to 2 GHz, along with an NPU, GPU, and VPU to cover all of the AI bases. VPUs are an emerging type of microprocessor devoted to vision-based machine learning tasks, distinct from GPUs as they have no rasterization or video encoding abilities.

The device will reportedly provide up to 50 TOPS of AI performance, with 40 TOPS coming just from the onboard NPU. The 3D-capable GPU onboard supports up to 8K@50Hz encoding, with the VPU tagging along for those vision-dependent AI training tasks. The mini PC supports up to 64GB of LPDDR5 RAM and NVMe SSDs, and we'd expect to see a microSD slot for the OS, as is common on DC-ROMA devices.

The only SoC that advertizes the same specs (and makes the same bold "world's first" claims) is Eswin Computing's EIC7702X, which is two Eswin EIC7700Xs stuck together. The dual-CPUs, two 4-core SiFive Performance P550s, are rated for up to 1.8 GHz each, paired with GPUs based on Imagination IP. The EIC7700X, one-half of the EIC7702X we expect to find in the DC-ROMA PC, can be seen on SiFive's HiFive Premier P550 developer board, which we reviewed earlier this year and gave 3.5 out of 5 stars.

RISC-V is an open-source instruction set architecture, similar to x86 or Arm. RISC-V development has been very active in recent years, especially in China, where its open-source nature provides a path forward for Chinese engineers stymied by an ongoing trade war with the United States. The DC-ROMA RISC-V AI PC, while not likely to blow anyone away with its speeds, does provide an extremely novel promise. Small form factor AI performance on the RISC-V platform is a very narrow intersection of three already niche worlds, but it may be a desirable buy for those happy few.

The RISC-V Mainboard II for Framework Laptop 13 (aka the DC-ROMA RISC-V AI PC) is available now for pre-order from DeepComputing. The device will start at $300 on its release in Q3 2025, with a $9.90 deposit required today. If it follows the pattern of the first DC-ROMA Framework mainboard, it will likely be sold as a standalone board, inside a mini-PC enclosure, or pre-assembled inside a Framework Laptop 13. We're cautiously optimistic about the future of this release, and as always stand ready to applaud any and all headway made towards a brighter future for RISC-V computing.

A version of the Linux operating system can now be run inside a PDF opened by a Chromium-based browser. The brains behind the coding gymnastics involved in this 6MB LinuxPDF project belong to high school student Ading2210. If the name is familiar, it might be because the same person created DoomPDF, which we reported on in January.

Ading2210 explains that Linux runs in the PDF within a modified version of the TinyEMU RISC-V emulator. The developer notes that LinuxPDF "works in a very similar way to my previous DoomPDF project." Like DoomPDF, this Linux-in-a-doc project also has a bit of a performance problem, as it is claimed to be "over 100x slower" than it should be.

The TinyEMU RISC-V emulator runs in the PDF thanks to a technique where its code is compiled "using an old version of Emscripten that targets asm.js instead of WebAssembly." This is embedded and loads in the PDF, subsequently auto-running a minimal Linux kernel targeting that architecture. In this implementation, once you agree to 'Start Emulator' in your browser, you will see the LinuxPDF UI load, and a welcome message in the Linux viewport, as you wait for the OS to boot.

Those who dabbled with the DoomPDF release will see some familiarity with LinuxPDF's low-contrast gray display. LinuxPDF also outputs to the screen via the same line-by-line ASCII output that drove the gaming PDF.

Below the Linux viewport in the PDF is a soft keyboard created by an array of PDF buttons. However, it is likely quicker for everyone with a decent physical keyboard to input commands into the 'type here for keyboard inputs' field to the lower right of the keyboard UI area.

On the topic of speed and efficiency, Ading2210 humbly admits that performance might be the largest problem with LinuxPDF. "The Linux kernel takes about 30-60 seconds to boot up within the PDF, which [is] over 100x slower than normal," notes the developer. With Chrome's current PDF engine having its Just-in-Time (JIT) compiler disabled, Ading2210 sees no way of speeding up the code, for now.

If you wish to try out the LinuxPDF, it requires a Chromium-based browser to work correctly (we checked, but it didn't work in Firefox on PC). Others might be satisfied to simply watch Ading2210's video of LinuxPDF starting, booting, and responding to a handful of commands. As with Ading2210's previous projects, the source code is all available to read and tinker with on GitHub.

SpacemiT, a China-based CPU developer, has introduced the VitalStone V100, a server processor with up to 64 RISC-V cores, reports Heise Online. While the CPU is aimed at modern workloads, the single-thread performance of the processor is comparable to outdated Intel Xeon and AMD Opteron processors.

SpacemiT's VitalStone V100 processor is largely based on the OpenC910 project design, which is already used by Alibaba's T-Head Xuantie C910 processor. The X100 4-issue 12-stage out-of-order cores in the VitalStone V100 were developed in-house by SpacemiT. They are compliant with the RVA23 core specification and support 256-bit vector processing, standardized hypervisors and IOMMU (input-output memory management units), protection against certain side-channel attacks like Spectre or Meltdown, and RISC-V Boot and Runtime Services (BRS), which define how processors boot and interface with firmware and operating systems. The processor is made on a 12nm-class process technology and its maximum frequency is 2.50 GHz.

Performance-wise, each X100 core achieves a SPEC CINT2006 integer score of 9, translating to a total of 22.5 points at 2.5 GHz, according to Heise. This places it on par with older processors like the Intel Xeon E5520 (2.27 GHz, 24.1 points) and AMD Opteron 6212 (2.6 GHz, 22.9 points) but with a significantly higher core count, making it suitable for parallelized tasks, the source noted. The chip also delivers AI computational capabilities, offering 2.5 TOPS with INT8 data processing at its peak frequency, which is not something to write home about.

Launching a processor that offers performance on par with CPUs that are more than 10 years old would not make a lot of sense in the U.S. or Europe. But as China strives to reduce dependence on Western technologies in general and processors in particular, SpacemiT will certainly find customers for its 64-core VitalStone V100. Unfortunately, we have no idea about its pricing, nor pricing of servers based on the VitalStone V100 processors. Given that the CPU is based on the open-source RISC-V ISA and is made on a rather mature 12nm-class process technology, it is unlikely that it is an expensive CPU.

In addition to the VitalStone V100, SpacemiT also markets the Keystone K1, a RISC-V processor designed for laptops and single-board computers.

Qualcomm is assembling a team of developers to design server processors for the data center. Evidence of this comes via a vacancy posted on the company's own website (noticed by Longhorn). The company is looking for a server system-on-chip (SoC) security architect, and the details of the listing outline that the company is "developing reference platforms based on Qualcomm's Snapdragon SoC, delivering a comprehensive solution that includes hardware, software, reference designs, user guides, SDKs, and more."

The job listing confirms the existence of a 'Qualcomm Data Center' team that is designing a 'high-performance, energy-efficient server solution for data center applications.' While we are, of course, speculating, Qualcomm may plan to use the high-performance energy-efficient cores designed by its Nuvia team for data center applications. This same team developed the company's Snapdragon X processors for laptops, but it originally designed server processors before it was brought into the Qualcomm stable. 

In fact, Qualcomm used to develop and sell Arm-based data center CPUs back in the day without much success, which is presumably why it stopped. However, Amazon’s Graviton processors have proven that Arm-based solutions can thrive in the data center, and the market is wide open for more innovative entrants. Apparently, Amazon's success made Qualcomm rethink and return to the drawing board with data center CPUs. 

"We are seeking experienced SoC Security Architects to join our team," the job listing reads. "If you possess a deep understanding of hardware security architecture and are passionate about architecting and designing complex SoCs at advanced process nodes, we would be pleased to hear from you. This critical role involves architecting the next-generation security system and hardware infrastructure by collaborating with other platform architects to optimize overall Power, Performance, Area (PPA) efficiency and security assurance while ensuring compliance with industry standards."

Interestingly, when acquiring Nuvia, Qualcomm specifically noted that it planned to use Nuvia's Phoenix cores in its processors for client PC and not data centers, despite the fact that Nuvia originally designed its cores with the data center in mind. Nowadays, the cores dubbed 'Oryon' power Qualcomm's Snapdragon X processors for client PCs.

But now that Qualcomm has apparently changed its mind about data center products and is assembling a team of SoC developers (the core team is already there), it is reasonable to expect the company to develop a data center solution within the next couple of years. While we do not know for sure, the first devices to use Qualcomm's CPUs would likely be the company's platforms for 5G and then eventually 6G base stations, a space where the company controls the hardware and software stack. As for Qualcomm's development of chips for data centers currently dominated by x86, only time will tell if that is the company's ultimate intention. 

Imagination Technology is primarily known for its GPU IP used by a wide range of companies across the industry, but in 2021 the company expanded its business with RISC-V Catapult CPU IP to address various market segments with a complete CPU+GPU solution. However, it looks like the business did not meet the company's expectations, so it has decided to divest in RISC-V to focus on GPU and AI IP, reports eeNews Europe.

"Imagination exited its standalone line of CPUs to increase our investment in graphics, AI, and compute at the edge which we believe is transformational for our business," a statement by Imagination published by eeNews Europe reads.

Despite this shift, Imagination maintains a commitment to the RISC-V ecosystem. It is ready to work with developers of RISC-V CPUs and CPU IP to try to become 'a GPU provider of choice' for the entire ecosystem, rather than addressing designs that its range of CPU IP could cover.

Indeed, the company's lineup of RISC-V CPU IP was not exactly wide and included IPs for microcontrollers, real-time embedded processors, entry-level automotive CPUs, and more recently a 64-bit core that could compete against Arm's Cortex-A510/A520. While the portfolio could potentially allow Imagination to license its cores to dozens or hundreds of companies (especially in China), it could not address the high end of the market, which is small today, but could grow in years to come.

Imagination's decision to shift its focus solely to GPUs is a bit ironic considering its history with MIPS, a company that developed processors based on its own instruction set architecture, got acquired by Imagination in 2013, then sold in 2017, went bankrupt, and then re-emerged in 2020 as a developer of RISC-V CPU IP.

One of the most recent reports about Imagination Technologies indicated that its current owner Canyon Bridge Capital Partners tasked an asset management firm to find a buyer for the GPU developer.

This happened weeks after the UK-China Transparency organization accused Imagination Technologies and its owner which is controlled by the Chinese government of facilitating the transfer of Imagination's key IP to China-based GPU designers Biren Technology, InnoSilicon, and Moore Threads. These technologies reportedly enabled Chinese companies to develop advanced GPUs that could be used to advance AI, military, and supercomputing applications.

We may have a winner for the $20,000 Raspberry Pi and Hextree RP2350 Hacking Challenge, but we won't officially find out who the winner is until January 14. Engineer Aedan Cullen went public with his Hacking the RP2350 presentation at the recent 38th Chaos Communication Congress (38C3), and there is a GitHub repo now published to accompany the video here. Cullen studied the RP2350 in detail before going for a voltage injection glitch attack on pin 53 of the RP2350 chip, which managed to turn on the 'permanently disabled' RISC-V cores and their debug access port, enabling him to read the secret.

Raspberry Pi introduced the RP2350 via the Raspberry Pi Pico 2 as a successor to the RP2040 – with added security features to appeal to commercial and industrial customers. To publicize the new microcontroller it teamed up with Hextree to devise the RP2350 Hacking Challenge, announced at DEF CON in August. This challenge concluded on 31 Dec 2024, but we must wait until January 14 for the official winner announcement. Cullen made his presentation at 38C3 on Dec 27 and also shared a GitHub repo with an outline of his hacking process and Python code. However, we don't know if Cullen is the winner, so this may not be the $20K winning hack method.

Specifically, the RP2350 comes with a quartet of new security features, that Raspberry Pi was keen to highlight. These are Secure Boot, TrustZone, Redundancy Coprocessor (RCP), and Glitch Detectors. The setters of the challenge hid a secret on one of these 'fully secured' chips, which would be supplied to hackers who applied, and the first demonstrable success story would get $20,000 and the kudos of being the winner of the challenge. Attacks using hardware and/or software means were permissible by the competition rules, so it was almost an anything-goes situation.

Raspberry Pi and Hextree would hide the secret in the RP2350's OTP (One Time Programmable) memory on the chip, said to be a once-set but never-forget binary code. Picotool was used to write the covert code to the OTP. Then the RP2350's OTP memory was locked behind the Page Locks hardware protection feature, set to an 'inaccessible' state '13:12' as per the table above. Firmware was also signed, with Secure Boot enabled, and they disabled the chip debug feature, so prying eyes couldn't get to the secret via a Serial Wire Debug (SWD) interface. Furthermore, all other bootkeys were disabled, the RP2350 Glitch Detector was turned on and then set to its highest sensitivity. It certainly sounds like it was locked down.

Cullen says he started his hacking process by studying the RP2350 data sheet and the dependencies outlined in the documentation. Then Cullen drilled down on how the RP2350 boots and establishes its security settings, with particular attention to the OTP.

Cullen's first idea was to get the OTP to misread its critical bit settings, you could get the chip to work in a non-secure way. Cullen even X-rayed the RP2350 as part of his investigations and annotated the chip blocks. However, he stresses that this was just a pursuit of interest and not really instrumental to beating the challenge.

Research compelled Cullen to focus on Pin 53, labeled USB-OTP_VDD, as it is connected to OTP (and USB) functions. Perhaps a hacker could "mess with this power supply externally" to affect these functions, he pondered. So he took off the chip and isolated Pin 53 (physically cutting PCB trace), so it was ready to be electrically tampered with separately on a reassembled board.

With this hardware-modified setup, Cullen probed Pin 53 to "inject whatever voltages I want" and checked what happened. An unprotected RP2350 board was kept on hand for side-by-side comparisons. Once the hardware was set up he watched what normally occurs when a secured and a non-secured RP2350 started up – according to the probe readout on an oscilloscope.

16 groups of spikes were seen, corresponding with 16 initial OTP reads on startup. Cullen then tested injecting power glitches to Pin 53 at certain points in the boot process. Disappointingly, the debug remained locked down. Next, a Python script was used to sweep the position of a glitch power input through the entire 600-microsecond range of OTP reads during startup. The debug functionality was checked but never became available. So Cullen looked at the unlocked RP2350 board again, with debugging enabled, for clues.

Then, something interesting was observed, as the RISC-V cores showed up via the glitch on the unsecured RP2350. Cullen then used another script to check where the RISC-V debug access port shows up. This technique could also be triggered on the secured RP2350 – and a debugger could now be connected to the secured RP2350 and the secret read from the OTP!

Secret gets busted

The 'permanently disabled' RISC-V cores had been woken by the glitch to enable this access. Cullen explains the odd underlying reason that the glitch 0x00030033 works is that it disables both Arm and RISC-V cores but, the Arm disable instruction has higher priority, leaving RISC-V turned on. Importantly the glitch successfully clears Debug_Disable.

For more information about the background to this hack, particularly bypassing the guard read mechanism, we advise watching the video recorded during the 38c3 (linked top). There's also an interesting Q&A at the end of the session. You might find attendees ask similar questions to those you may have.

Cullen concluded his presentation with three pithy points:

• Human communication factors are huge. Sidense [the company behind OTP NV memory tech used] knew how to do guards properly, and RPi missed out.
• “Permanent” is not a thing unless it involves chip destruction. There is some copper somewhere with each signal…
• Remember to glitch in the places they don’t tell you.

The semiconductor industry produces many kinds of distinct processors, but RISC-V startup Ubitium says it’s working on a single architecture that can rule them all.

Emerging from stealth sometime this year, Ubitium has gone public to announce the development of its Universal Processor, which is based on a “workload-agnostic microarchitecture.”

“Our Universal Processor does it all – CPU, GPU, DSP, FPGA – in one chip, one architecture. This isn’t an incremental improvement. It is a paradigm shift. This is the processor architecture the AI era demands,” Ubitium CEO Hyun Shin Cho says.

The Universal Processor is based on the RISC-V architecture, traditionally used for CPUs. However, Ubitium’s upcoming chip isn’t something like AMD’s MI300A or Nvidia’s Grace-Hopper Superchip, which combine distinct CPU and GPU chips into one package. Instead, Ubititum claims all of the transistors in its Universal Processor can be reused for everything; no “specialized cores” like those in CPUs and GPUs are required.

In concept, Ubitium’s RISC-V processor sounds like an FPGA, which can be reprogrammed to change its functionality, sometimes also known as hardware emulation. But while FPGAs tend to come short of chips designed for specific uses in areas like performance, efficiency, and value, Ubititum says the Universal Processor will be “smaller, more energy-efficient, and significantly less costly.”

The developers behind Ubitium’s Universal Processor are a handful of semiconductor veterans who worked at companies like Intel, Nvidia, and Texas Instruments, as well as smaller chip firms such as PACT XPP Technologies. Incidentally, PACT, which focuses on FPGAs and parallel computing, has been involved in a few patent lawsuits against Intel (twice in fact) and Xilinx (now part of AMD).

Although the Ubitium team has a decent amount of talent and experience, they don’t have a ton of funding yet. So far the company has raised $3.7 million, which Ubititum says will be used to develop prototypes and create development kits, ahead of the Universal Processor’s launch date sometime in 2026.

While $3.7 million isn’t nothing, it’s almost certainly not enough to get Ubitium’s “breakthrough” chip off the ground. It usually costs a few hundred million dollars to get a chip to the tape-out phase, when the first samples are fabbed. With $3.7 million, Ubitium can use hardware description languages like Verilog to design its architecture, and potentially emulate it using an FPGA to test it further. But at some point, Ubitium will undoubtedly require greater financial backing to launch its Universal Processor.

Even if Ubitium had much more funding, being able to launch in 2026 is still a very tall order. Traditional microarchitectures made by industry titans such as AMD, Intel, or Apple can take years to develop; launching an architecture that’s supposed to “revolutionize” the industry in just two years would be challenging, to say the least.

Ubitium isn’t just working on a single chip, either, and envisions having a “complete portfolio of chips that vary in array size but share the same microarchitecture and software stack.” These chips would cover everything from “small embedded devices” (similar to AMD’s Ryzen embedded CPUs) to “high-performance computing systems,” which would compete with the fastest and biggest processors in the industry.

This isn’t the first chip startup in 2024 to make claims about transforming the semiconductor industry with just a few million dollars in the bank. Earlier this year, Flow Computing announced it was working on a Parallel Processing Unit, or PPU, that could increase CPU performance by a hundredfold after rewriting software. Flow’s PPU however sounds a lot like a GPU, much like how Ubitium’s Universal Processor sounds like an FPGA.

RISC-V computer firm DeepComputing announced that it offers early access to its new motherboard for the Framework Laptop 13.

The DC-ROMA RISC-V Mainboard features the JH7110 CPU made by chip designer StarFive. The processor sports four SiFive U74 cores that clock up to 1.5 GHz and an integrated GPU from Imagination. 8GB of memory and a 64GB SD card are also on the board, and through different tiers, DeepComputing optionally offers USB type A and HDMI ports and a WiFi 6 card. Users can choose the Ubuntu or Fedora Linux distros (or even both) for their operating system, as Linux is the most RISC-V-friendly OS today.

It’s not DeepComputing’s first time designing laptop hardware with RISC-V in mind. The company was the first to bring a RISC-V-powered laptop to market.

Even considering the DC-ROMA Mainboard is targeted at low-power laptops, it’s not expected to deliver outstanding performance. RISC-V is still relatively new, and not all software is optimized for the architecture yet, which is a significant obstacle to good performance. However, the availability of RISC-V systems from companies like DeepComputing could help improve software compatibility and optimization.

DeepComputing says the early access program is available only to “enterprise and business customers.” Still, for those who fit the bill, the DC-ROMA motherboard can be bought for as little as $199 via the Basic tier. Alongside the board, the $199 tier comes with two USB type-C expansion cards and a case made by Framework and Cooler Master, meaning the cheapest tier is technically enough to build a primary mini-PC.

For $100 extra, the Standard tier adds in USB type-A and HDMI ports plus the WiFi card and antennae, which seems a little expensive for what you’re getting. The $799 Pro and $999 Enterprise tiers may be a better deal, including the Basic and Standard tiers and the Framework 13 Laptop, maybe a better deal.

DeepComputing offers “value-added services” for $99 to $169, depending on the tier. Those who opt into this add-on will get mass-produced DC-ROMA boards for half off, 15% off any DeepComputing product in the company’s catalog, and an opportunity to provide feedback to DeepComputing about the board.

DeepComputing Founder Yuning Liang confirmed to Tom’s Hardware that orders for the DC-ROMA Mainboard will be open to the general public next year. Liang also confirmed that pricing won’t change after the early access program ends.

RISC-V firm Milk-V demonstrated that it can get AMD’s RX 7900 XTX graphics card to work on one of its RISC-V boards.

The PC shown in the video uses Milk-V’s Megrez board, which is equipped with Chinese RISC-V chip maker Eswin’s EIC7700X, a system-on-chip (SoC) that hosts four P550 CPU cores designed by SiFive. The P550 core has been around since 2021, so it’s nothing cutting-edge at the tail end of 2024. The SoC sport H.265 encoding and decoding at 8K, and has a 20 TOPS NPU, which are both reasonably robust for PCs.

The particular 7900 XTX that Milk-V used was made by XFX and ran on Debian Linux. There wasn’t much choice in terms of the OS, as Linux boasts the best support for RISC-V at the moment. The brief demo showed the system running the glmark2 benchmark, which renders 3D objects at the highest framerate possible.

However, Milk-V got a 7900 XTX up and running on this RISC-V board, which marks another milestone for RISC-V’s ambitions in PCs. So far, the open-standard architecture has been primarily used for data centers, AI, and tiny, low-function chips that form just one small part of a whole product. Although the usage of RISC-V has been growing steadily for the last few years, the architecture hasn’t penetrated the PC market, the domain of x86, and now Arm.

A few RISC-V laptops have made it to market, such as DeepComputing’s DC-ROMA and the Lichee Console 4A, but you could count them all on one or maybe two hands. No fully assembled RISC-V-powered desktop exists, but some motherboards come with RISC-V chips, such as those made by Milk-V.

Although no RISC-V CPU is in a position to realistically take advantage of support for AMD’s flagship gaming CPU, the support’s existence certainly won’t hurt. It will undoubtedly be difficult for RISC-V to make inroads into the PC ecosystem if Arm’s example is anything to judge by. Arm chip designer Qualcomm struggled for years to make its Snapdragon laptops an appealing choice until this year with the Snapdragon X Elite. Estimates show Arm CPUs will power as much as 40% of notebooks sold in 2029.

It is important to note that Arm has the full support of Microsoft, which is crucial for Arm’s success in PCs since Windows is the most important OS for consumer desktops and laptops. Getting supported on Windows will probably be essential for RISC-V’s adoption in the PC market. Otherwise, RISC-V companies will have to bet on Windows getting serious competition from Linux or some other OS, which doesn’t seem likely to happen any time soon.

Although Nvidia's GPUs rely on proprietary CUDA cores that feature their instruction set architecture and support for various data formats, these cores are controlled by custom cores that rely on the industry-standard RISC-V ISA, albeit with some extensions, the company revealed at the RISC-V Summit this month (via NickBrownHPC).

Modern GPUs are highly complex system-on-chips with a massive number of functions and resources — starting from compute resources and power management and all the way to display engines and security — that must be managed.

These things are now managed by 10 to 40 custom RISC-V cores developed by Nvidia, depending on chip complexity. Nvidia started to replace its proprietary microcontrollers with RISC-V-based microcontroller cores in 2015, and by now, virtually all of its MCU cores are RISC-V-based, according to an Nvidia slide demonstrated at the RISC-V Summit.

By now, Nvidia has developed at least three RISC-V microcontroller cores: NV-RISCV32 (RV32I-MU, in-order single-issue core), NV-RISCV64 (RV64I-MSU, out-of-order dual-issue core), and NV-RVV (RV32I-MU, NVRISCV32 + 1024-bit vector extension). These cores (and perhaps others) replaced the proprietary Falcon microcontroller unit based on a different instruction set architecture. In addition, Nvidia has developed 20+ custom RISC-V extensions for extra performance, functionality, and security.

Perhaps the most important RISC-V-based part of Nvidia GPUs is its embedded GPU System Processor (GSP). According to Nvidia's website, the first GPUs to use RISC-V-based GSP were based on the Turing architecture. This GSP offloads Kernel Driver functions, reduces GPU MIMO exposure to the CPU, and manages how the GPU is used.

Since MCU cores are universal, they can be used across Nvidia's products. As a result, in 2024, Nvidia is expected to ship around a billion RISC-V cores built into its GPUs, CPUs, SoCs, and other products, according to one of the demonstrated slights, which highlights the ubiquity of custom RISC-V cores in Nvidia's hardware.

Nvidia ships millions of GPUs every year. In 2023 alone, Nvidia shipped 31 million desktop discrete GPUs (according to Jon Peddie Research), around the same number of standalone GPUs for laptops, several millions of data center GPUs, and plenty of other types of hardware. That said, multiple RISC-V cores exist in all of Nvidia's chips.

Those looking for PC management solutions like KVMs, particularly in the server space, may be interested to hear of Sipeed's new KVM expansion card, which just opened up for preorders ahead of a planned October-November shipping window [h/t LinuxGizmos]. The first 500 preordered units will ship in October, and all subsequent preorder customers will receive shipments in November. Sipeed's new expansion card, the Sipeed NanoKVM-PCIe, is powered by RISC-V architecture and offers several connectivity solutions with full 1080p streaming support if you use it over the Internet. 

A few different models are also available during this preorder window, and all enjoy a 10% discount. The base model is the NanoKVM-PCIe Eth, available for $40. Then there's NanoKVM-PCIe Eth + Wi-Fi ($45), NanoKVM-PCIe Eth + PoE ($50), and the all-inclusive NanoKVM-PCIe Eth + Wi-Fi + PoE ($55). "Commission fees" of $2-$3 also apply per model, though truthfully, this sounds like something that should have been included in pricing from the get-go.

In any case, the NanoKVM-PCIe does look pretty nice. While the connectivity and power methods will differ depending on your specific model, the flexibility is quite nice. The device can be powered off the PCIe slot, USB, 9-Pin, or PoE power. It should function even when the PC is powered off, allowing for Wake over LAN functionality.

Regarding connectivity, only the Wi-Fi models include Wi-Fi, but if you opt for those, you'll enjoy reasonably high-speed Wi-Fi 6 support once you attach an antenna. Alternately, you can stick with Ethernet, which is most common in these server- and enterprise-centric use cases, where you're expected to manage multiple PCs as terminals. Wired and Wireless will stream at 1080p and 60 FPS, with a range of 100-160 milliseconds of video delay. At 60 FPS, 160 ms of delay is equivalent to roughly 9.6 frames, so gamers shouldn't even consider something like this— not that this is targeted at them, anyway.

One particularly nifty feature of the device is a minuscule OLED display alongside the rest of the I/O that gives status readings, including current streaming resolution and FPS. It's more than a little gimmicky, but it's nice if such a thing suits your configuration needs.

Cambridge-based Pragmatic Semiconductor has demonstrated its Flex-RV bendable non-silicon RISC-V processor. On Wednesday, the firm published a blog, Nature paper, and video to showcase what it calls “the world’s first 32-bit microprocessor in a flexible technology that is fully functional while flexed.” Pragmatic also boasted that the Flex-RV is machine learning capable and can be produced for less than a dollar.

In the video, you can see a Flex-RX processor sample being wrapped around a pencil while executing simple commands. The demo shows that the physically flexible general-purpose RISC-V processor can be coiled tighter than a 5mm radius. Then, we see it put through some tensile bending, flattened, and compressive bending before being unfurled again. Programs can always continue to execute without missing a beat (or crashing or freezing).

Flex-RV builds on Pragmatic’s prior flexible electronics works, namely FlexPCB (a flexible printed circuit board design) and FlexIC (flexible integrated circuits) fabricated with IZGO tech on TFTs. The processors are less than 80µm thick, including the PCB, consume less than 6mW of power, and offer outstanding flexibility plus affordability.

Above is an overview of the Flex-RV system architecture. If you look carefully at the schematic, you can see that a programmable ML hardware accelerator accompanies the open Servant RISC-V CPU. Other SoC bits and pieces include a register file (RF), a debug switch, a multiplexor switch, an arbiter, a RAM interface, an on-chip RAM block, and a General-purpose Input/Output (GPIO) interface. Programs are loaded into the on-chip RAM through the debug switch and external memory access.

However, the Flex-RV’s tech performance specs will not excite many readers. Test samples feature 12,600 logic gates and have average and maximum clock speeds of 52 kHz and 60 kHz, respectively.

Emre Ozer, Pragmatic’s Senior Director of Processor Development and lead researcher, has high hopes for the Flex-RV. The press release quotes Ozer as characterizing the flexible new processor as an exciting step forward for the industry. Moreover, the collaborative work between Qamcom and Harvard scientists “will democratize access to computing, unlocking emerging applications while opening the door to sub-dollar computing,” claimed Ozer.

The Pragmatic boss reckons that open-source flexible processors with ML processing capability and such a low cost could be attractive for applications such as FMCG, wearables, and single-use healthcare equipment.

Flex-RV outflexes previous similar projects physically and computationally. For example, the earlier PlasticArm was a collaboration between Pragmatic and Arm in 2021. PlasticArm used Arm Cortex M0 cores but was non-programmable, was limited to three hardwired programs in its read-only memory, and ran at an even slower sub-30 kHz while consuming 3.5X as much power (21mW).

The freshly released Raspberry Pi Pico 2 comes with two different CPUs onboard. A dual core Arm cortex M33 or a Dual Core RISC-V Hazard3, yes the first RISC-V product from Raspberry Pi! The latter CPU has a performance that falls somewhere between the older Raspberry Pi Pico’s dual core Arm Cortex M0+ and the new Arm Cortex M33. The RISC-V CPU was developed by Raspberry Pi employee Luke Wren as an interesting side project.

Right now there are two ways to use this new CPU, via the C++ workflow, and using a preview of the latest MicroPython firmware. We’re going to use the latest MicroPython firmware for RISC-V to show that it is as easy as the version of MicroPython used for the Arm CPU.

The goal of the project is to create a WS2812B “NeoPixel” light sequence, demonstrating that the RISC-V CPU is capable of handling the timing critical WS2812B protocol and producing a rather splendid “disco light” effect for the office.

For this how to you will need

• Raspberry Pi Pico 2
• Good quality micro USB cable
• Half-size breadboard
• WS2812B “NeoPixel” stick
• 3 x Male to male jumper wires

Installing MicroPython for RISC-V on the Raspberry Pi Pico 2

1. Download the RISC-V MicroPython UF2 file from the MicroPython resource. Ensure that you download the RISC-V preview. Note that as this is a preview, things are liable to break, so do not build any mission critical projects with this firmware.

2. Push and hold the BOOTSEL button on the Pico 2, then connect to your computer using a micro USB cable. Release BOOTSEL once the drive RP2350 appears on your computer.

3. Drag and drop the UF2 file onto the RP2350 drive. The Raspberry Pi Pico 2 will reboot and will now run MicroPython.

If you have never used MicroPython, it is a version of Python 3 developed for microcontrollers. If you can write Python, then you can write MicroPython. To write MicroPython code, we need to use a dedicated editor and the default, basic editor is Thonny which is what we shall use for this tutorial.

4. Download and install Thonny for your OS.

5. Open Thonny.

6. Connect the Raspberry Pi Pico 2 to your computer and in Thonny go to Tools > Options and click on the Interpreter tab. From the interpreter, dropdown list select MicroPython (Raspberry Pi Pico). The port dropdown menu can be left to automatically detect the Pico. Click Ok to close.

7. Check the Python Shell (REPL) for “Raspberry Pi Pico2 with RP2350-RISCV” to confirm that it has been installed correctly.

Building the Circuit

The circuit is a simple connection between the Pico 2 and the WS2812B “NeoPixels” that uses only three wires. We need connections for power and data.

You may need to solder header pins to your Neopixels, for that you will need the best soldering iron or soldering station, and a quick refresher on how to solder.

Writing the code

The goal of the code is to create a pseudo random light sequence along the full length of NeoPixels.

1. Create a new blank file in Thonny (File >> New).

2. Import a series of modules (pre-written code.) The first is machine, this enables the code to talk to the Pico 2’s GPIO. Next is NeoPixel, an abstraction that makes working with the WS2812B RGB LEDs much easier. Then we import time, used to add delays to the code. Finally we import the random integer generator from the random module. This is used to generate random numbers in our code.

import machineimport neopixelimport timefrom random import randint

3. Create an object, np, and use it to tell the code that we have NeoPixels connected to pin 16, and that we have 8 “pixels” (individual LEDs) in the chain. Change this value to match how many you have.

np = neopixel.NeoPixel(machine.Pin(16),8)

4. Create a try, exception handling sequence. Essentially this tells the Pico 2 to try and run the code that is indented inside of it. If it fails, an exception is raised, and we will catch that later.

try:

5. Indented to show that this is the code to “try” and run, add a while True loop to run the code forever. Thonny will auto-indent the code as we type.

   while True:

6. Create four objects, r,g,b and n to store randomly generated numbers between a range of 0 and 128 (r,g,b) and 0 to 7 (n, the number of NeoPixels in our chain, we have eight, but Python starts counting from zero.) The value 128 is half brightness for the NeoPixels. You can set this to be 255 for full brightness, but it does consume more power, and could affect those with photosensitivity.

       r = randint(0,128)       g = randint(0,128)       b = randint(0,128)       n = randint(0,7)

7. Print the current color mix values to the Python Shell. This is the mix of R,G and B that makes up the randomly chosen color.

       print("This color is: ","{} {} {}".format(r,g,b))

8. Set the value of the randomly chosen pixel (n) to the color mix stored as r,g,b using the np object that we created earlier.

       np[n] = (r,g,b)

9. Write the changes to the NeoPixels, and then wait for 0.1 seconds. This adds a short delay before the code goes back to the start of the while True loop and repeats the process.

       np.write()       time.sleep(0.1)

10. Create the exception handler part of the code to detect when the user clicks Stop, or press CTRL + C.

except KeyboardInterrupt:

11. Print a message “EXIT” to the Python Shell. This tells the user that the exception has been successfully raised and the handler process is now in control.

   print("EXIT")

12. Using a for loop, iterating through all of the NeoPixels (8 for us). Set all of them to off, and write the changes to take effect.

   for i in range(8):       np[i] = (0,0,0)       np.write()

13. Save the code to the Raspberry Pi Pico 2 as pixels.py.

14. Click on Run > Run Current Script, or click on the green run button to start the code.

All of the NeoPixels in the chain should soon be a random color, changing every 0.1 seconds. The Python Shell will show the current color as an RGB value.

When you want to stop, click on the stop button, or press CTRL + C on the keyboard.

Complete Code Listing

import machineimport neopixelimport timefrom random import randintnp = neopixel.NeoPixel(machine.Pin(16),8)try:    while True:        r = randint(0,128)        g = randint(0,128)        b = randint(0,128)        n = randint(0,7)        print("This color is: ","{} {} {}".format(r,g,b))        np[n] = (r,g,b)        np.write()        time.sleep(0.1)except KeyboardInterrupt:    print("EXIT")    for i in range(8):        np[i] = (0,0,0)        np.write()

RISC-V, the open source, royalty-free CPU architecture, is in the very early stages of development and adoption compared to mainstream ARM and x86/x64 CPUs— but despite that, Box86/Box64 developers still managed to get last-gen AAA title The Witcher 3: Wild Hunt running on a RISC-V PC. Besides Box64, which was used to emulate x86 instructions in general, Wine and DXVK helped fill the gaps using Linux instead of Windows. The developers wrote a detailed blog post on how this was accomplished and uploaded video footage of the game running on YouTube.

So, before you get too excited about a future where PC gamers don't need to rely on Microsoft, Intel, or AMD to play games, The Witcher 3 is only managing a measly 15 FPS in these conditions. However, even being launch-able, much less semi-playable on RISC-V, the game is still a significant technical achievement and bodes exceptionally well for the future of open-source architecture. A high-complexity, high-fidelity game like The Witcher 3 truly pushes the architecture to its limits. Still, it proves its capabilities simultaneously, even though a genuinely playable, immersive experience remains out of reach.

As explained by the FOSS (Free and Open Source Software) project Box86 developers in their blog post, the significant issues with running The Witcher 3 on RISC-V start with x86_x64 CPU instructions. Games and other software, in general, rely on specific CPU instructions, so when that software must be run on another hardware architecture, the new architecture needs to be able to substitute or duplicate those instructions. 

So, the major challenge of x86 emulation on RISC-V architecture is translating those x86/x64 CPU instructions into something RISC-V can actually understand. The original blog post details a few x86 instructions that are particularly tough to translate efficiently on RISC-V, which results in a lot of hardware power being spent on excessive "translation" of what used to be simple x86 instructions made complex by RISC-V architecture.

Last August, we discussed these same Box86 developers making a breakthrough by achieving fully playable 2D games on RISC-V, like Stardew Valley and World of Goo. For The Witcher 3, the developers needed to acquire a Milk-V Pioneer, a 64-core RISC-V PC with a PCIe slot. One AMD Radeon RX 5500 XT installation later, and a RISC-V PC is now capable of playing last-gen AAA titles, at least in a very limited form.

For now, this realistically isn't a big deal for anyone who wants to play games or buy a PC that can play games today. However, like the ongoing development of Windows on Arm and Proton on Linux, ongoing efforts like these show us that today's Big Tech companies won't have complete control of the PC gaming market forever. At this rate, a competent RISC-V gaming PC could be on the market within the next decade— maybe even half the time.

DeepComputing, one of the leaders in RISC-V development, just announced its DC-ROMA RISC-V Pad II tablet. This mobile device is powered by a SpacemiT Key Stone K1 SoC, the same processor found in its upgraded DC-ROMA Laptop II. Thus, it is easier for developers already familiar with the system to use the new tablet.

The Pad II runs Ubuntu Desktop 24.04 and supports touch inputs, too, allowing developers to test and develop RISC-V mobile apps directly on it. Of course, writing code using an on-screen keyboard will likely be a punishment for a developer, so DeepComputing ensured that the Pad II also supports external keyboard connectivity.

The DC-ROMA RISC-V Pad II starts at $149 for the 4GB RAM version and is already available for pre-order on the DeepComputing store. If you get the 16GB RAM variant, the tab is compatible with the Android Open-Source Project (AOSP) Android 15 operating system. Here are the complete specifications of the DC-ROMA RISC-V Pad II tablet.

The Premium variant of the tablet is expected to be available starting September 15, 2024, while the Android 15 upgrade should arrive by 4Q24 for all 16GB-equipped Pad IIs. This RISC-V-powered tablet is helping developers build more mobile apps for the open standard, which suggests that DeepComputing is seeing a future where more users use it daily.

This development is crucial for companies in China, especially as the U.S. is continuously trying to block access to proprietary hardware via bans and sanctions to hold back its progress. Since RISC-V is an open-standard instruction set, with the entity overseeing its development, RISC-V International, based in neutral Switzerland, the U.S. cannot legally stop anyone, including Chinese companies, from using this technology.

Washington D.C. has tried to investigate how it can prevent its East Asian competitor from using the technology, saying that the Chinese government is using RISC-V to develop chips it needs to overcome American dominance in semiconductors. However, Callista Redmond, the chief executive of RISC-V International, is adamant that it remains open to all. Redmond said, “RISC-V is an open standard and has incorporated meaningful contributions from all over the world. As a global standard, RISC-V is not controlled by any single company or country.”

Nevertheless, owing to RISC-V’s open-standard/open-source nature, advancements in this technology will benefit the entire world, not just China. So, as DeepComputing and other entities continue investing in this technology, we hope to see a future where we have multiple competing processor architectures, giving consumers the option to pick and choose what works best for them.

Unisoc, formerly Spreadtrum, a well-known developer of various application processors from China, has introduced what it claims to be the world's first security chip based on RISC-V, an open instruction set architecture (ISA). The E450R is said to offer significant performance for security algorithms, reports IT Home.

The key feature of the E450R is its asymmetric cryptographic PKE algorithm engine, which is said to work 50% faster than on the predecessor. Even when the key length is increased, the chip maintains its performance, ensuring robust security without sacrificing speed, according to the source report. The E450R also offers a 50% improvement in typical transaction-based applications, which makes the chip particularly suitable for high-demand environments where quick processing is crucial, IT Home claims.

In addition to its cryptographic enhancements, the E450R offers a 15% boost in the erase/write speed of its non-volatile memory (NVM). This improvement allows the chip to store more data within the same time frame, making it more efficient for applications requiring frequent memory operations. 

The thing that makes Unisoc particularly proud is the use of the open-source RISC-V ISA. This allowed the company to tailor its processing cores for its workloads, offering more performance at lower power compared to the traditional approach when using off-the-shelf Arm R that leverages a lot of legacy features to maintain ISA integrity, to ensure compatibility with a range of software. This takes die space and power, unlike the case of RISC-V. Given the fact that Unisoc provides an API and maintains the software/firmware stack, there is no problem with software (in)compatibility of the E450R, at least IT Home and Unisoc do not mention this factor specifically. 

Speaking of software, Unisoc claims that the chip's tailor-made microarchitecture reduces application code size by 30% and speeds up application load time by 120%, which is crucial for real-time applications.  

The E450R has already achieved several important certifications, including National Cryptography Level 2, UnionPay chip and embedded software security certifications, and the CCRC IT EAL4+ certification. 

The only question we now have is can China's secret services bypass the level of security that the Unisoc E450R offers? 

While Intel is busy laying off thousands of employees some of its most experienced CPU architects, with a combined 80+ years at the firm, have left to form a RISC-V startup. AheadComputing was co-founded by Debbie Marr, Mark Dechene, Jonathan Pearce, and Srikanth Srinivasan, with the goal of “creating compelling open specification core IP.” This proactive move by the quartet of architects and engineers must be congratulated, as they founded AheadComputing and went public on July 18 – just a couple of weeks before Intel’s harsh workforce reduction plans were announced.

AheadComputing’s website is rather basic and threadbare at the time of writing, but it does contain a mission statement of sorts, some short bios detailing the ex-Intel co-founders, a single blog post (launch announcement), and a call for new recruits with experience in CPU design and verification roles.

As indicated above, the work of AheadComputing is going to begin with work on the RISC-V architecture. Specifically, the fledgling firm has set out with a plan “dedicated to designing, verifying, and licensing compelling RISC-V core IP.” For any deeper dive into the goings-on behind the doors of the new Oregon-based firm, you will have to chat with them directly or wait for further blogging. However, they will also meet with people during Happy Hour on Tuesdays, between 4 - 5:30 pm, at Cornelius Pass Roadhouse, Hillsboro…

The most compelling feature of AheadComputing is, for now, its co-founders, so let’s take a closer look at their resumes.

Co-founder, CEO, & President, Dr. Debbie Marr was an Intel Fellow and Chief Architect of the Advanced Architecture Development Group (AADG) at Intel and spent 33 years at the chipmaker on products spanning the i386 all up to the present day. A highlight of her career seems to have been bringing Intel Hyperthreading Technology from concept to finished product. Marr also authored over 40 patents in CPU, AI accelerators, and FPGA fields.

Co-Founder, Mark Dechene was an Intel Principal Engineer and CPU Architect in the Advanced Architecture Development Group. During his 16 years at Intel Dechene worked on architecture development for Intel CPU products including Haswell, Broadwell, Goldmont, Goldmont Plus, Tremont, and Skymont. Dechene has authored over 15 patents, focused on microprocessor performance.

Co-Founder, Jonathan Pearce was an Intel Principal Engineer, CPU Architect, and a key technologist & strategist in the Advanced Architecture Development Group until recently. Pearce worked for 22 years at Intel. During his career, Pearce has worked in both pre-silicon and post-silicon roles on multiple generations of Intel Core SOCs. He also authored 19 patents in the CPU, AI, and GPU fields.

Co-Founder, Dr. Srikanth Srinivasan has over 20 years of technical leadership experience in product R&D. At Intel he taped out some well-known chip designs like Nehalem, Haswell, and Broadwell. However, most recently, Srinivasan led the frontend and backend CPU teams at the Advanced Architecture Development Group at Intel. The highlight of his career / achievements so far is probably the authoring of more than a dozen highly cited papers and over 50 patents.

With its pedigree, surely we will hear about AheadComputing again, in the not-too-distant future. On the flip side, PC enthusiasts may rightly worry about the future of Intel when it has just instigated the most severe layoff plans in its 56-year history, some of its ambitious construction plans have come into question, and severe brain drain, as evidenced by this new RISC-V startup, could slow any chances of revival.

SiFive has introduced the SiFive Performance P870-D, a new RISC-V processor core designed for data center applications. The new P870-D not only sets the stage for RISC-V processors with up to 256 cores, but also enables building CPUs for mission-critical systems demanding the utmost reliability.

SiFive's Performance P870-D builds upon the regular P870, which is a six-wide out-of-order core with an RVA23 profile of the RISC-V instruction set architecture with vector and vector crypto processing acceleration. The P870-D adds an open AMBA CHI bridge for energy-efficient cross-cluster communications (each cluster has from one to four cores with shared L2 cache) as well as cross-cluster reliability, availability, and serviceability (RAS) features to enable building CPUs with up to 256 cores aimed at mission-critical applications. 

Additionally, the P870-D supports the RISC-V Sv57 extension, providing a 57-bit virtual address space that enhances its memory management capabilities. The processor also includes a distributed and scalable IOMMU, accelerating virtualized device IO, and meets modern safety and security standards.

"The new P870-D enhances our proven Performance architecture to bring new levels of performance, flexibility, and scalability," said John Ronco, SiFive SVP of Product. "The full solution offering from SiFive — including software, IOMMU, interrupt controller, and other uncore blocks — combined with our intelligence processors for dedicated AI compute makes it easy for our customers to achieve the most effective performance/watt/dollar metrics on AI and datacenter workloads."

To build processors with up to 256 cores, chip designers will have to license Ncore cache coherent network-on-chip from Arteris. Essentially, the SiFive P870-D allows CPU designs that are on par with those from AMD and Intel. In fact, given energy efficiency of RISC-V designs compared to x86, we can expect CPUs based on the P870-D to have an edge over rivals when it comes to performance-per-watt metrics.

"Network-on-Chip IP significantly helps streamline the process of building complex, multi-core heterogeneous SoCs with the lowest latency and high bandwidth to accommodate AI workloads," explained Michal Siwinski, CMO of Arteris. "We are pleased to continue the collaboration with SiFive, enabling the ecosystem to create high-performance and low-power RISC-V-based systems on time and budget while reducing risk." 

Currently, SiFive is offering samples of the P870-D to select customers (though it is unclear with how many cores), with full production of samples scheduled for the end of 2024. SiFive expects the first processors based on the P870-D to emerge already next year.

At the Black Hat cybersecurity conference in Las Vegas, a team of researchers just let the cat out of the bag about a new vulnerability affecting a very popular RISC-V CPU. The so-called GhostWrite attack affects the XuanTie C910 and C920 CPUs by Chinese chip company T-Head. The flaw allows attackers to gain root access or even pull the administrator password from system memory.

The researchers, from CISPA Helmholtz Center for Information Security in Germany, unveiled the flaw and noted several devices susceptible to it. While they say the vulnerability does not yet appear to be exploited in the wild, it’s a serious issue. Most of the CPU attacks found in recent years have been side-channel or transient execution attacks, but that’s not the case with GhostWrite.

GhostWrite is the result of an architectural flaw, a hardware bug in the XuanTie C910 and C920 CPU. These are only two of many RISC-V CPUs, but they are widely used for a variety of applications. According to the research team, vulnerable devices include:

• Scaleway Elastic Metal RV1, bare-metal C910 cloud instances
• Milk-V Pioneer, 64-core desktop/server
• Lichee Cluster 4A, compute cluster
• Lichee Book 4A, laptop
• Lichee Console 4A, tiny laptop
• Lichee Pocket 4A, gaming console
• Sipeed Lichee Pi 4A, single-board computer (SBC)
• Milk-V Meles, SBC
• BeagleV-Ahead, SBC

Since GhostWrite is a hardware flaw, it cannot be fixed with a simple software update or patch. The team found the attack 100% reliable, taking only microseconds to execute. It’s even able to bypass Docker containerization and other forms of sandboxing.

The only way the researchers found to mitigate the vulnerability was to disable the vector extension for the CPU. RISC-V processors use the vector extension add-on to handle larger data values than the base Instruction Set Architecture (ISA) can process.

Disabling the RISC-V vector extension means disabling roughly 50% of the instruction set for the CPU. In testing, the researchers found an overhead of up to 77% (PDF) when disabling the vector extension. This, naturally, may not be an acceptable solution for most uses.

The CISPA Helmholtz team reported the bug to T-Head, which acknowledged and reproduced it. However, the manufacturer hasn't commented on any fixes for the flaw.

There's a vast difference between hardware and software developers, which opens up pitfalls for those trying to coordinate the two teams. Arm and x86 researchers encountered it years ago -- and Linus Torvalds, the creator of Linux, fears RISC-V development may fall into the same chasm again.

“Even when you do hardware design in a more open manner, hardware people are different enough from software people [that] there’s a fairly big gulf between the Verilog and even the kernel, much less higher up the stack where you are working in what [is] so far away from the hardware that you really have no idea how the hardware works,” he said (video embedded below).

“So, it’s really hard to kind of work across this very wide gulf of things and I suspect the hardware designers, some of them have some overlap, but they will learn by doing mistakes — all the same mistakes that have been done before.”

RISC-V is an open-standard ISA for processors that is slowly gaining traction, especially in China, where some tech companies are using it to bypass America’s sanctions on the country. Companies like DeepComputing and Framework have started developing, building, and selling consumer laptops powered by these new processors.

But even though RISC-V is slowly being built up, it’s still not at the performance level that it could compete against current generation x86 and Arm processors. It would still take several years or decades of development to play AAA games on a RISC-V chip. But even though Arm, which also uses a reduced instruction set computer (RISC) architecture, has already undergone intensive development, Linus fears RISC-V will still make the same mistakes.

“They’ll have all the same issues we have on the Arm side and that x86 had before them,” he says. “It will take a few generations for them to say, ‘Oh, we didn’t think about that,’ because they have new people involved.”

But even if RISC-V development is still expected to make many mistakes, he also said it will be much easier to develop the hardware now. Linus says, “It took a few decades to really get to the point where Arm and x86 are competing on fairly equal ground because there was al this software that was fairly PC-centric and that has passed. That will make it easier for new architectures like RISC-V to then come in.”

According to a report from Phoronix, version 6.11 of the mainline Linux kernel, which seems set to launch soon, will add support for RISC-V memory hot plugging. The Linux kernel already offered this feature for other CPU architectures, but it's a very important addition for the long-term health of the open-architecture RISC-V CPUs since server applications and the like wouldn't be as resilient without easy hot plugging support.

For those unfamiliar with RAM hot plugging or hot swapping, it's very similar in concept to HDD/SSD hot plugging and hot swapping — the user can replace the specific component without powering down the system. However, hot plugging storage drives is a pretty mainstream feature of consumer operating systems and motherboards, whereas hot plugging RAM certainly is not.

Memory hot plugging has existed in some form or another for quite a long time—it was even available on the ultra-retro Zilog Z80 CPUs of the 1980s. Today, though, it's mostly locked down to server motherboards and, with them, dedicated server versions of Windows or most Linux distributions. 

In any case, RISC-V CPUs getting the functionality should help expand the potential use cases of RISC-V architecture in the future. For now, the enterprise and server spaces are quite firmly ruled by the overlords of x86 CPUs from Intel or AMD and AI-accelerating GPUs from Nvidia— but at quite a price premium, which makes every improvement to RISC-V architecture and other alternatives just a little more compelling. Once a single RISC-V CPU can start pushing comparable compute to mid-range desktop CPUs, the PC and server market alike should start looking like a very different place.

It helps that there are quite a few moves in the marketplace to adopt RISC-V or improve support for it. Framework's customizable laptops (down to CPU, of course) recently announced upcoming support for a RISC-V Framework laptop mainboard, and XSi even managed to run CPU, GPU, and NPU workloads on RISC-V cores. And, of course, the existing major players in enterprise, AI, and Big Tech also have a vested interest in the continued growth of RISC-V.

Milk-V has announced the Jupiter, a mini-ITX motherboard with a RISC-V processor pre-installed. A respected vendor of microcontrollers and RISC-V products, Milk-V brings "RISC-V for everyone" with Jupiter, which will ship soon.

At the Milk-V Jupiter's core is the SpacemiT K1 or M1 processor, a duo of processors powered by eight SpacemiT X60 CPU cores. Specs on the processors and their cores differ based on your source; our best estimation is that the K1 and M1 are virtually identical CPUs running their cores between 1.6 and 2.4 GHz. The processors both contain 819 MHz Imagination BXE-2-32 graphics with Vulkan 1.3 and OpenCL 3.0 support and can produce 2 TOPS of AI performance.

The Jupiter will come with either 4GB, 8GB, or 16GB of LPDDR4X soldered memory. It also supports M.2 drives as long as the M.2 2280 form factor on a PCIe 2.0 bus — limiting speeds to 500 MB/s — alongside a microSD reader and eMMC connector. Jupiter provides a PCIe 2.0 x8 slot for other connectivity, providing space for a slower graphics card or more storage expansion.

At a standard 170 x 170mm mini-ITX form factor, the board provides all the standard I/O you'll use to build a machine. Motherboard headers include 2x USB 3.0 and 2x USB 2.0 and the standard front panel connectors, plus typical ATX 24-pin power, SATA power, and PWM fan headers (no RGB headers, a real shame for the board's target demographic). Rear-panel I/O is listed below.

• 1 x USB 2.0 Type-C
• 2 x USB 3.0 Type-A ports
• 2 x USB 2.0 Type-A ports
• 1 x HDMI (up to 1920 x 1440 pixels @ 60 Hz)
• 2 x Gigabit Ethernet
• 1 x 3.5mm headphone
• 1 x 3.5mm microphone
• 1 x 12V DC power input

Milk-V's Jupiter is a silly method to bring RISC-V to the mainstream, but it stands a chance. A computer built on Jupiter will natively support only the Ubuntu and Fedora distros of Linux, leaving the average Windows or MacOS user in the dust. And while the CPU's 2 TOPS and 50 kDMIPS performance is far from impressive (when was the last time you saw a company advertise with kDMIPS?), the machine may appeal to enthusiasts as a NAS with its CASA OS support.

Currently, Milk-V's website only lists shipping options to China, but the company's X (formerly Twitter) has confirmed U.S./worldwide shipping to begin in the first week of July. Most RISC-V fans will be looking past Jupiter to the release of the Milk-V Oasis, a similar upcoming mini-ITX product expected to offer performance orders of magnitude beyond Jupiter's. RISC-V's continued steady growth thanks to the AI bubble and the growing success of Arm-based processors will continue to provide dividends to low-power computing fans.

The Holy Grail of supercomputing chip design is an architecture that combines the versatility and programmability of CPUs with the explicit parallelism of GPUs, and InspireSemi strives to achieve just that. InspireSemi's Thunderbird 'supercomputer-cluster-on-a-chip' packs 1,536 RISC-V cores designed specifically for high-performance computing, but it also supports a general-purpose CPU programming model. It also has incredible scalability — four chips can be placed on a single accelerator card, which comes in a standard GPU-like form factor (AIC), bringing the total of cores per card up to 6,144, with extended scalability to 360,000 cores per cluster. 

InspireSemi's Thunderbird processor packs 1,536 custom 64-bit superscalar RISC-V cores with plenty of high-performance SRAM, accelerators for several cryptography algorithms, and an on-chip low-latency mesh fabric for inter- and intra-chip connectivity. The chip also supports LPDDR memory, NVMe storage, PCIe, and GbE connectivity. It has been taped out and will be fabbed at TSMC, then packaged at ASE. 

InspireSemi aims to install four Thunderbird chips onto a single board to offer developers 6,144 RISC-V cores. The current Thunderbird architecture supports scale-out capability to up to 256 processors connected using high-speed serial transceivers.  

When it comes to performance, InspireSemi says that its solution offers up to 24 FP64 TFLOPS at 50 GFLOPS/W (at 480W), which is a formidable performance. To put this into context, Nvidia's A100 delivers 19.5 FP64 TFLOPS, whereas Nvidia's H100 reaches 67 FP64 TFLOPS. It's unclear if we are dealing with the performance of a single-chip Thunderbird card or a 4-way model. Delivering 1920W to an add-in card is hardly possible, so it is likely that we are dealing with four Thunderbird processors on a card that can offer 24 FP64 TFLOPS per chip. 

The superscalar cores support vector tensor operations and mixed-precision floating point data formats, though there is no word that these cores are Linux-capable, which is why InspireSemi calls Thunderbird an accelerator rather than a general-purpose processor. Still, this processor can be programmed like a regular RISC-V CPU and supports a variety of workloads, such as AI, HPC, graph analytics, blockchain, and other compute-intensive applications. As a result, InspireSemi's customers will not have to use proprietary tools or software stacks like Nvidia's CUDA. The only question is whether industry-standard tools and software stacks will be enough to extract maximum performance from the Thunderbird I in all kinds of workloads. 

"We are proud of the accomplishment of our engineering and operations team to finish the Thunderbird I design and submit it to our world-class supply chain partners, TSMC, ASE, and imec for production," said Ron Van Dell, CEO of InspireSemi. "We expect to begin customer deliveries in the fourth quarter." 

Speaking of customers and partners, InspireSemi has a long list of companies it works with, including Lenovo, Penguin Computing, 2CRSI, World Wide Computing, GigaIO, Cadence, and GUC, just to name a few. 

"This is a major milestone for our company and an exciting time to be bringing this versatile accelerated computing solution to market," said Alex Gray, Founder, CTO, and President of InspireSemi. "Thunderbird accelerates many critical applications in important industries that other approaches do not, including life sciences, genomics, medical devices, climate change research, and applications that require deep simulation and modeling."

Rain AI, an AI hardware processor developer backed by OpenAI's Sam Altman and investment banks, has hired Jean-Didier Allegrucci, a former Apple chip executive, to lead its hardware engineering. This high-profile hire indicates that Rain AI has serious plans for its processors.

Jean-Didier Allegrucci, who has yet to update his LinkedIn profile, worked on Apple's system-on-chips (SoCs) for over 17 years since June 2007 and oversaw development of more than 30 processors used for iPhones, Macs, iPads, and Apple Watch. Based on a Rain AI blog post, Allegrucci was instrumental to build Apple's world-class SoC development team, overseeing areas such as SoC methodology, architecture, design, integration, and verification, so his experience will be extremely valuable for Rain AI. Before Apple, J-D Allegrucci worked at Vivante and ATI Technologies, both developers of graphics processing units.

"We could not be more excited to have a hardware leader of J-D’s caliber overseeing our silicon efforts," said Rain AI CEO William Passo. "Our novel compute-in-memory (CIM) technology will help unlock the true potential of today's generative AI models, and get us one step closer to running the fastest, cheapest, and most advanced AI models anywhere."

At Rain AI, Jean-Didier Allegrucci will collaborate with Amin Firoozshahian, Rain AI's lead architect, who transitioned from Meta Platforms after a five-year tenure. This partnership combines deep industry experience and innovative thinking to drive the company's ambitious goals. Yet, it will take quite some time before Amin Firoozshahian and Jean-Didier Allegrucci build their first system-on-chip at Rain. The process typically takes many years.

Rain AI's focus is on in-memory compute technology, which processes data at the storage location, mimicking the human brain. It promises to enhance energy efficiency significantly compared to traditional AI processors, such as Nvidia's H100, or B100/B200 or AMD's Instinct MI300X.

Earlier this month Rain AI licensed Andes Technology's AX45MPV RISC-V vector processor with the ACE/COPILOT instruction customization and partnered with Andes's Custom Computing Business Unit (CCBU) to accelerate development of its compute-in-memory generative AI solutions. This collaboration aims to enhance Rain AI's product roadmap and deliver scalable AI solutions by early 2025.

Given the time it usually takes to develop a complex processor from scratch and the fact that Rain AI is tasking Andes to help it build its first SoC by early 2025, it looks like processors which development will be led by Jean-Didier Allegrucci are at least a couple of years away and his input to the 2025 product will be limited (if any).

China Mobile has announced its upcoming CC2560A "super SIM card", the world's first SIM card with a RISC-V core onboard. The CC2560A is an IoT product which improves on every aspect of a traditional SIM card: more storage, better security algorithms, and new functionality like NFC support.  

China Mobile, the largest mobile provider in the world, held a 5G IoT product conference on Wednesday. Among other IoT solutions and new releases, China Mobile announced the RISC-V super SIM. Powered by a single RISC-V core running at 120 MHz, the company claims the new SIM offers ten times the communication rate of a standard SIM card, around two times the rate of current high-end super SIMs already seeing use in the IoT field. The RISC-V SIM's onboard flash storage capacity of 2.5MB is also ten times larger than a standard SIM's storage and twice that of other super SIMs.

Unfortunately for the power phone users in the audience, average users will not be seeing the RISC-V super SIM in their devices anytime soon — not least because the card is a China Mobile exclusive which will possess intense security features and encryption. SIM cards are needed anytime a device needs to be uniquely identified over a network; the use case we are all familiar with is as an identifier within a smartphone to our phone carriers. 

Super SIMs, considerably more powerful and versatile than traditional consumer SIMs, have already become an important product in the IoT field, allowing elite features such as multi-network connectivity and automatic network failover for highly connected devices. While thankfully your new smart fridge won't need a SIM card, super SIMs are popping up in shared rental scooters, fleet tracking devices, and digital billboards.  

China Mobile's example use cases for the super SIM include electronic student ID cards, digital car keys, public transportation, and other instances regarding controlling access. The RISC-V powered super SIM is certainly a unique product; no one would think of a boosted CPU core on a SIM card besides a company aiming to gain the dollars of a hungry IoT field. Future innovation on the chip may not see the light of day, however; U.S. lawmakers are anxiously engaged in blocking China's access to the RISC-V protocol.

Framework has announced that it’s partnering with DeepComputing to create a mainboard powered by a RISC-V processor. This mainboard will be a drop in replacement for the modular Framework Laptop 13, giving more people easy access to the RISC-V CPU architecture. You can also purchase the RISC-V mainboard separately from the laptop, perhaps instead buying the Cooler Master Mainboard Case to use it as a Mini-PC.

DeepComputing is the company behind the first RISC-V laptop and has recently been released in its second generation. But despite all its work on the DC-ROMA RISC-V Laptop II, the company was also busy in the background, building the Framework RISC-V Mainboard. In fact, the company already has a working prototype, and it will show it off at the RISC-V Summit Europe next week.

Framework’s philosophy of ‘an open system ecosystem is more powerful than the sum of its parts’ is a perfect fit with RISC-V’s open standard Instruction Set Architecture (ISA). Contemporary Framework laptops are available with either an Intel Core Ultra or AMD Ryzen 7040 processor — proprietary x86 chips owned by Intel and AMD. Aside from these two chips, which own most of the PC market, we also have the Apple M-silicon and Qualcomm Snapdragon chips, with the latter going on-sale yesterday as Microsoft Copilot+ PCs. However, these chips are based on the ARM ISA, which is owned and licensed by Arm Holdings.

On the other hand, because RISC-V is an open and royalty-free standard, anyone can use and build on it without needing to ask for permission from RISC-V International, the Swiss-based non-profit association that maintains the ISA, or pay licensing fees.

This means building on RISC-V could be cheaper than competing proprietary architectures, that’s why many companies and startups are interested in iterating on it. The recent AI boom is even forecasted to grow this standard’s industry adoption by 50% annually until 2030. Some examples of this include SiFive, which partnered with a Chinese manufacturer to build a RISC-V development board, and Google, which uses RISC-V cores for its AI silicon. X-Silicon Inc. has even created a RISC-V chip that runs CPU, GPU, and NPU workloads simultaneously.

Aside from cost considerations, RISC-V’s open nature means the U.S. cannot restrict other companies and countries from accessing it. The RISC-V Foundation, which was based in the California, even moved to Switzerland in 2019 because of Washington’s restrictive trade regulations and renamed itself to RISC-V International. This move to a historically neutral country meant laws cannot be used to limit anyone’s access to the ISA.

Nevertheless, American lawmakers are still investigating China’s access to this technology, especially as Washington is working hard to restrict Beijing’s access to advanced tech. However, since it remains open, many Chinese startups and companies are taking advantage of this ISA, allowing them to produce chips that aren’t restricted by American sanction.

Framework sees this trend, so by working with DeepComputing to introduce a RISC-V mainboard, it would make it easier for more people to get interested in and experiment with the standard. Although the company says that this RISC-V laptop will not have the performance of its AMD and Intel processors, it will be “a great way to start playing with RISC-V though (sic) inside of a thin, light, refined laptop.”

DeepComputing, the maker of the DC-ROMA RISC-V Laptop, just released an upgrade of its groundbreaking RISC-V-based computer. Dubbed the DC-ROMA RISC-V Laptop II, this revamped PC gets a SpacemiT SoC K1, which features 8 cores that run up to 2.0 GHz. This is a massive improvement over the previous version of the laptop, which only had a quad-core CPU limited to 1.5 GHz. The DC-ROMA RISC-V Laptop II also benefits from an AI Fusion Computing Engine and can be specced out to have 16GB of RAM.

The SpacemiT K1 chip is the same one found in the MuseBook, which the company launched recently and is focused on developers and engineers. While the MuseBook is a budget computer priced at just $300, the DC-ROMA RISC-V Laptop has a regular price of HK$7,820 or approximately $1,000, although it’s currently on sale at HK$5,865 or around $750.

Another big development with the Laptop II is its use of Canonical Ubuntu as its operating system. The previous version only supported openKylin and Debian, meaning you had to install an OS after purchase. On the other hand, the new laptop comes with Ubuntu right out of the box, making it easier for users to get up and running with the device.

RISC-V is an open-standard instruction set architecture developed at the University of California, Berkley, and uses the same reduced instruction set computer (RISC) architecture that Arm bases its designs on. The latter went on to dominate the consumer market, with most smartphones using Arm-based chips. Even Microsoft’s new Copilot+ PCs, which are powered by Qualcomm’s Snapdragon X SoCs, use Arm designs.

But even though RISC-V did not gain mass adoption in the consumer space, it still has a solid presence in data servers, high-performance computing, AI and machine learning, and even automotive systems. RISC-V is actually forecasted to grow quickly until 2030, especially as the demand for AI is growing exponentially.

RISC-V is an open-source architecture, so it’s much cheaper for companies to use their designs instead of licensing one from Arm, for example. Google is even reportedly set to use RISC-V as the base of its new custom AI silicon for its AI servers. Demand for this architecture is also driven by China, especially as it’s grappling with bans and sanctions from the US.

These sanctions have forced Chinese tech companies to look elsewhere for technologies, and RISC-V’s open-source nature is crucial for some of their plans. U.S.-imposed limitations have allowed the East Asian country to build innovative solutions based on this architecture. SiFive, the American semiconductor company behind the general-purpose cores of Google’s TPUs, even chose the faster Chinese Eswin SoC instead of an Intel processor for its HiFive Premier P550 development board.

Some of the news behind RISC-V’s advancement has put it in the spotlight of American lawmakers. The U.S. Department of Commerce then started to investigate China’s access to the open-source standard, and the risks that it poses to American technological supremacy. However, Calista Redmond, the CEO of Swiss-based RISC-V International, is adamant that RISC-V remain open. She said, “RISC-V is an open standard and has incorporated meaningful contributions from all over the world. As a global standard, RISC-V is not controlled by any single company or country.”

As long as RISC-V remains open to the world, many companies, both from the East and the West, will likely want to take advantage of its open-source nature. This will bring competition to Arm, Intel, and AMD, forcing these companies to innovate, not just in technological advancements, but in price efficiency, too.

RISC-V chips are set to become a global powerhouse in the 2020s, with a market share of almost 25% by 2030, according to research by Omdia. The forecast outpaces even RISC-V International's own ambitious expectations from November.

RISC-V is an open-standard instruction set architecture (ISA) — the structure that tells CPUs how to interpret instructions, with alternatives being Arm or x86. RISC-V is unique in the chip world due to its open standard, allowing developers to use and even edit RISC-V to develop their own CPUs. 

Between 2024 and 2030, Omdia expects RISC-V-based chip shipments to increase by 50% annually, reaching a peak of 17 billion chips shipped in 2030 alone. The largest industry for RISC-V will be industrial applications, set to make up 46% of sales, but the greatest growth will be in automotive, with an expected 66% growth in automotive annually. 

"RISC-V has unique, desirable aspects for the automotive industry," says Edward Wilford, Senior Principal Analyst for IoT at Omdia. "You can own your design in RISC-V in a way that you simply can't with a licensed ISA, and in conversations in the industry, that's really highlighted as an important element." Bespoke use cases for RISC-V are how the ISA got a hold in the tech industry, with chips for IoT devices like smart fridges. The automotive world is excited for RISC-V not just for its customizability, but also for its ability to handle AI workloads.

Wilford chiefly highlights the continual growth of the nascent AI market as a contributor to RISC-V's success in the coming years. "RISC-V makes the most sense in novel applications, where a developer doesn't already have an existing Arm product in place. The rise of AI, the increase in use cases and capabilities, means a lot of new territory is being revealed and all of it has potential for RISC-V." This has already proven true for RISC-V, highlighted in this RISC-V microprocessor which can run CPU, GPU, and NPU workloads simultaneously on the same core. 

Omdia's forecast is believable, based on today's RISC-V trends. Major players in the tech world like Google and Meta are investing in RISC-V to power their AI datacenters, and chip producers like Qualcomm are creating their own RISC-V chips for consumer use. Chinese manufacturers are already using RISC-V in consumer laptops, much to the chagrin of angry U.S. lawmakers who have determined that Chinese entities cannot be allowed to have any access to the international open standard. 

Tech gadget builder bitluni recently unveiled his latest build, a 256-core RISC-V megacluster. The YouTube content creator demonstrated the miniature supercomputer in a video that highlighted the design, production, assembly, and testing phases. Not everything went as planned, but the results are actually pretty nerdy and cool.

For the design, bitluni combined 16 RISC-V superclusters into a single megacluster. Each supercluster consisted of 16 CH32V003 RISC-V microcontrollers connected with an 8-bit bus. Each supercluster contains its own LED because bitluni wanted to be able to display a line of text.

To deal with potential problems inherent in building an extremely large (and power-hungry) single PCB for the megacluster, bitluni installed the superclusters in pairs on eight “cluster blade” designs. The inventor used two additional CH32V203 microcontrollers on each blade to serve as a bridge between each supercluster and the main 8-bit megacluster bus.

In the video, you can watch the assembly in time-lapse as bitluni attaches the microcontrollers to the PCB, solders the GPIO headers, and puts the entire megacluster together for testing. The blades all attach to a single main board, and as bitluni demonstrated first the LEDs blinking, he also found one of the mistakes he made in the design.

Without an internal clock source, bitluni discovered his LEDs blinked out of sync with each other. So, even though the lights initially blinked simultaneously, they quickly lost that synchronicity and flashed randomly. (Still, it’s almost hypnotic to watch.)

The creator went on to describe how to programmatically deal with bus collisions as all the microcontrollers talked at once.

Ultimately, bitluni’s megacluster used 256 RISC-V microcontrollers at 48 MHz and 17 RISC-V chips at 144 MHz. It includes 640 GPIO pins and 256 ADC circuits. He describes the 14.7 GHz combined single-core clock rate as "not that impressive but also not too shabby."

Considering bitluni designed and built a supercomputer that is small enough to sit on a TV tray, that description may be a bit of an understatement. Let’s also not forget that what he built cost far less than you would spend on even the used and leaky Cheyenne supercomputer.

Chinese startup SpacemiT has unveiled its next computer, a laptop based on the K1 octa-core RISC-V chip. It is not exactly a standard laptop, but the MuseBook, as it’s called, has features and capabilities aimed at hardware engineers, developers, and DIY enthusiasts. While no official launch date is available, it’s expected to be available soon at a relatively low price of $300.

The MuseBook looks vaguely like an Apple MacBook, primarily from the printed name at the bottom of its display bezel. A 14.1-inch IPS panel with a 1920 x 1080 resolution and 60Hz refresh rate is standard. The keyboard is more akin to Windows machines, but the dedicated Windows button has been replaced by a RISC-V button. There’s no news yet on what function that button might provide since the unit provided to CNX Software would not power on.

The laptop weighs in at 1.3kg and is approximately 18mm thick. It provides a MicroSD card slot, two USB-C ports, two USB 3.0 Type-A ports, a 3.5mm headphone jack, and an 8-pin header with pins for power, multiplexed I2C, UART, PWM, GPIO, and more. The full specifications for the K1 SoC are listed below:

The laptop's storage includes up to 128GB of onboard eMMC flash memory, M.2 NVMe SSD options up to 1TB, and a MicroSD card slot. The K1 RISC-V System-on-a-Chip (SoC) is configured with up to 16GB of LPDDR4X RAM. Wireless networking connectivity is available via the installed RTL8852BE-based WiFi 6 module.

The MuseBook runs Bianbu OS, an operating system based on Debian and optimized for the K1 RISC-V SoC. Presumably, it will include common office software such as LibreOffice and the Chromium browser. It will also include optimized OpenCV, OpenBLAS, Slam Eigen, libpng, libjpeg, XNNPACK, and other algorithm libraries for development purposes.

If preferred, you can also install the Linux flavor of your choice or RTOS on the laptop. Of course, finding RISC-V packages in standard repositories might prove problematic.

Of course, this isn’t the first RISC-V laptop to come to market. We’ve reviewed the Sipeed Lichee Console 4A in the past, and there’s also the ROMA laptop. However, the K1 is the first RISC-V SoC to comply with the RISC-V Foundation’s RVA22 and 256-bit RVV 1.0 standards. While not exactly blazing fast compared to, for example, the Intel Core Ultra CPU, SpacemiT’s K1 SoC does provide 2 TOPS of AI computing power.

The U.S. Department of Commerce is investigating the risks of China's access to the RISC-V instruction set architecture (ISA) for processors, Reuters reports, heeding calls from lawmakers.

RISC-V (pronounced risk-five) is an ISA, a software instruction standard that tells processors how to receive instructions (e.g. x86 and ARM). RISC-V's low complexity is easier to work with than x86, and is a fully open standard — unlike Arm, its primary competitor. While not popular in mainstream computing products, the standard has a high potential for most processor use cases, concerning U.S. lawmakers attempting to limit China's access to advanced computing power in the ongoing trade war over tech. 

The RISC-V standard is a fully open standard, licensable by anyone, and is currently held by a Swiss trust to keep its open standard nature intact. But this has not stopped U.S. lawmakers from calling it a U.S.-based tool and declaring China's use of it to be wrong — and perhaps dangerous.  

"The CCP (Chinese Communist Party) is abusing RISC-V to get around U.S. dominance of the intellectual property needed to design chips," said Michael McCaul, chairman of the House Foreign Affairs Committee in his first attack on China's access to RISC-V back in October. 

This is not the first time the U.S. government has tried to stop China's access to RISC-V. In October, McCaul and other lawmakers called for China's access to RISC-V to be hampered, which RISC-V International was swift to push back on. Callista Redmond, chief executive of RISC-V International, responded that unhampered open standards are important: "RISC-V is an open standard and has incorporated meaningful contributions from all over the world. As a global standard, RISC-V is not controlled by any single company or country." 

Open standards, such as Ethernet, HTTPS, and USB have revolutionized the internet and technology, and restricting access to any of these would have catastrophic impacts on both the embargoed entity and the success of the open-source projects that would now find their reach limited. 

In November 2023, a new group of 18 lawmakers again attacked China's access to RISC-V. Yesterday, the Department of Commerce responded to their claims, stating it is now "working to review potential risks and assess whether there are appropriate actions under Commerce authorities that could effectively address any potential concerns." 

The Department of Commerce also addressed RISC-V International's worries about the restriction of the open-source standard, however, noting that it would need to act carefully to "avoid harming U.S. companies that are part of international groups working on RISC-V technology." 

The chip war between China and the U.S. will likely continue for as long as the U.S. fears military development or losing economic ground to their superpower competition. And while the U.S. continues attempting to ban China's access to any powerful technologies, China is not making relations easier, with a report yesterday finding that Chinese universities have been sidestepping sanctions on Nvidia GPUs.

Allen Wu, formerly the chief executive of Arm China, has reportedly founded a new company that will develop chips based on the RISC-V instruction set architecture. The company – Zhongzhi Chip (Shanghai) Technology Co. — will of course challenge both Arm and Arm China in some respect. Meanwhile, rumor has it that the company could be a Tenstorrent 'representative' in China.

Details about the Zhongzhi Chip are scarce, but the word chip in the name implies that we are talking about an entity that designs RISC-V processor IP and computing platform solutions rather than microcontroller units, though this is our assumption not a fact cast in stone. In fact, the information was made public by TrendForce, a respected market tracker, citing a report from Chip_Inside, so the details might be inaccurate and should be taken with a grain of salt.

Under the leadership of the controversial Allen Wu, Zhongzhi Chip is reportedly attracting a notable influx of talent, including numerous former employees of Arm, indicating the new company's serious ambitions in the chip sector. 

Meanwhile, the company's recruitment strategy highlights its commitment to securing top-tier expertise, the company's operational focus remains partially unclear, with speculation around whether it will primarily engage in its own research and development initiatives or represent Tenstorrent in China as its agent. 

Tenstorrent, which develops HPC CPUs and AI processors based on the RISC-V ISA, could be a formidable partner, though the role of Allen Wu is unclear in this case. Given the fact that Tenstorrent's roadmap seems to be flexible enough to add new products, it could well be that Zhongzhi Chip's task is to attract clients, understand their requirements, and then use Tenstorrent's technology to meet their needs. This essentially makes Zhongzhi Chip a contract chip designer, or a custom-chip developer.  

Based on the source report, Zhongzhi Chip is leveraging its connections and forming alliances with several other leading global RISC-V chip developers. Technically, these partnerships are strategic, aiming to enhance the company's technical prowess and accelerate its growth in the industry, which implies that Zhongzhi Chip is aiming at a broader market than Tenstorrent. 

The report further details that the company is positioning itself as a key player in the processor IP market by maintaining a stance of technological neutrality, which it believes will support the growth of China's domestic applications. 

SiFive has unveiled the HiFive Premier P550, a new development board using the RISC-V architecture. It will be the first commercially available out-of-order RISC-V development board. Also intriguing (and surprising) is that the new hardware includes a Chinese-made Eswin SoC, even though SiFive is an Intel partner. The new development board is designed for many different market segments and applications, including machine vision, video analysis, and AI.

The P550 comes with 16GB of LPDDR5-6400 memory and a 128GB eMMC SSD for "fast bootable" storage. Connectivity comes in the form of a single PCIe 3.0 x4 interface connected to an x16 slot on the motherboard along with five USB 3.2 Gen 1 ports.

The Eswin EIC7700 SoC features four P550 cores, 256KB of L2 cache, and 4MB of L3 cache. The main selling point of the new chip is its out-of-order capabilities, which allow the processor to reorder instructions to increase throughput and performance. The superscalar P550 can issue three instructions per cycle per core.

Out-of-order CPU designs have been around for a long time, with Intel first adding the feature in the Pentium Pro back in 1995. Out-of-order architectures tend to use more power but offer greater performance. Out-of-order chips are also more vulnerable to side-channel attacks. Smartphones stuck with in-order designs until after 2010, but today, nearly all modern smartphones also feature out-of-order chip architectures.

The P550 SoC also comes with an integrated GPU (no details were provided other than that it offers 2D/3D acceleration), hardware video encoder and decoder, NPU, DSP, MIPI DSI, and a security subsystem. The P550 is designed as a cheaper alternative to the P550 Pro, which debuted last year. The latter sports significantly better connectivity and includes an Intel-made RISC-V "Horse Creek" SoC. Again, it's interesting that the P550 and P550 Pro use completely different core designs.

SiFive partnered up with Canonical to make the P550 compatible with Ubuntu — one of the most popular flavors of Linux. According to Gordan Markus, Silicon Alliances Director at Canonical: “Thanks to our collaboration with SiFive, developers using the HiFive Premier P550 board will be able to innovate at speed with Ubuntu. Additionally, Canonical’s software and services will accelerate time to market, and ensure long-term support and security maintenance for our enterprise partners.”

The P550 has a lot of potential, but availability might be its Achilles heel. According to The Register, the HiFive Pro P550, which launched a year ago, is still almost impossible to find. Hopefully, this same fate doesn't befall the P550.

Since the P550 uses an entirely different CPU from its Pro counterpart, that could help improve availability. SiFive partnered with Intel to create the Horse Creek SoC found in the P550 Pro, but Intel hasn't had a great track record with RISC-V and appears to have no problems killing its own RISC-V projects if necessary.

Due to the P550 Pro's lack of availability, it seems like the Horse Creek CPU was a complete failure — even though Intel says this wasn't the case. Regardless, there must be a very good reason why SiFive (again, a partner with Intel), decided to swing the pendulum the other direction and chose a Chinese-made RISC-V CPU for the P550.