As advanced packaging technologies like EMIB and CoWoS become yet another battlefield in the semiconductor industry, outsourced semiconductor assembly and test (OSAT) companies are trying new tools in a bid to offer services that others do not. This week, LG Electronics Production Technology Institute (PRI) signed a contract with an OSAT to supply it with a maskless laser direct imaging (LDI) lithography tool that can be used to build metal-interconnect patterns in semiconductor packaging, potentially with higher yields than currently available tools, reports ETNews.

LG-PRI's Laser Direct Imaging (LDI) system is a maskless lithography machine designed to pattern fine metal interconnects for advanced semiconductor packaging. While the company has developed various versions of the machine, its highest-resolution version can produce 1.5-µm line-and-space (L/S) patterns, which should be fine to 'print' wiring pitches of about 3 µm. The production equipment uses a 405-nm laser-diode light source and can process substrates as large as 600 × 600 mm, according to various media reports.

LG positions its LDI system primarily for advanced semiconductor packaging using organic and then glass substrates, displays, and MEMS. Yet, it can also be used to build high-density printed circuit boards (PCBs) for mobile devices or prototype purposes.

LG is entering an already established direct-imaging market led by KLA, Screen Holdings, Limata, and ORC, but participated in by a dozen manufacturers from Germany, France, Switzerland, Japan, and even China. What is notable is that LG is offering LDI systems with line/space capability down to 1.5-µm, which means it is targeting the higher end of the market. Yet, to establish a position, LG plans to price its LDI system competitively.

Another way to pattern substrates

There are many ways to pattern substrates, including photolithography, e-beam lithography, nanoimprint lithography, and laser direct imaging, just to name a few. LDI is a maskless lithography process in which a laser exposes a digitally generated circuit pattern directly onto a photoresist-coated substrate, rather than transferring the pattern through a physical photomask. Instead of a photomask, an LDI system uses a digitally controlled pattern generator and projection optics, which resembles how a laser cinema projector projects a digital image onto a screen, except that LDI projects a circuit pattern onto photoresist. After development, the exposed resist leaves a pattern that defines where metal interconnects will be formed in later processing steps.

LG's LDI machine can produce down to 1.5-µm line-and-space patterns, which is good enough for chip substrates and even redistribution layers (TSMC CoWoS-R/-L uses RDL interposers with a minimum 4-µm pitch, or 2-µm line width/spacing). In contrast, competing products offer 1-µm, 3-µm, and 5-µm versions for different applications. While LDI in general cannot boast the resolutions offered by modern DUV, EUV, or e-beam lithography machines, LDI trades ultimate resolution for vastly higher throughput and large-area processing, exactly what the doctor ordered for production of PCBs or chip packaging. With current-generation LDI, the RDL interposer is the most advanced thing that these devices can pattern, as both CoWoS-S and CoWoS-L/EMIB-like technologies require considerably higher resolution. Meanwhile, there is another advantage that LDI machines have over lithography systems that rely on photomasks.

Because the image is generated digitally, the system can create and calibrate patterns in real time, while projection optics, precision alignment, and stage control position the pattern accurately on the substrate. This capability is important because the dimensions/geometry of packaging substrates can vary and because organic substrates can expand, contract, or warp during processing. Given that we are talking about a 1.5-µm-scale wiring pattern, any shift from the nominal layout may result in a solder bridge or a faulty contact, which means yield loss. That said, the ability to adjust the pattern to the peculiarities of a substrate may be a game-changer for OSATs, their customers, and a major selling point for devices that can do it.

A new kid on the block? Not really

Unlike competing chaebols Samsung and SK Group, LG Group does not produce chips, even though its divisions supply various materials and components for the semiconductor industry. To that end, it is perfectly reasonable for the company to enter the market for tools for the production of chip packages or PCBs.

In fact, LG PRI is not entering the exposure-equipment business from scratch. PRI traces its history to the Goldstar Production Technology Research Institute, established in 1987, and has worked on manufacturing and productivity technologies covering semiconductors, displays, and rechargeable batteries. Specifically, LG had already commercialized LDI technology for display manufacturing and supplied such equipment to LG Display.

As a result, the semiconductor packaging-grade equipment represents an expansion of an existing LG technology into a new market rather than the development of an entirely new exposure platform from scratch and without any experience. Interestingly, LDI is the first element of LG's semiconductor equipment ambitions. The company reportedly plans to expand its portfolio into high-bandwidth memory (HBM) inspection equipment as well as through-glass-via (TGV) laser systems for glass substrates.

Prospects

Before LG expands to inspection or laser drilling tools, it will have to establish itself as a producer of reliable tools used for chip packaging, which will likely take years. For now, the significance of the deal with the undisclosed OSAT is less about business and more about the fact that an OSAT decided to give LG's LDI machine a try. Moving from university R&D installations to an OSAT mass-production facility provides LG a starting point for pursuing additional external orders.

Whether LG can establish itself alongside Applied Materials, ORC, or Screen will depend on how its equipment performs in production and whether its emphasis on competitive pricing proves sufficient to persuade more packaging companies to adopt the system.

In any case, a new Wafer Fab Equipment player is here, which is good news considering shortages of virtually all chipmaking tools. While LG's entrance will hardly have any noticeable impact on the market for at least a couple of years, another supplier could eventually add much-needed capacity, increase competition, and give chipmakers and OSATs another source of advanced packaging equipment.

Nvidia has rejected a report claiming that it plans to begin small-batch shipments of a language processing unit tailored for Chinese customers by the end of 2026, with several Chinese orders already placed. "The reporting in The Information on NVIDIA's LPU is incorrect. We have no LPU sales in the China market today, and no China-specific LPU product in our roadmap," an Nvidia spokesperson told Tom's Hardware on Thursday. The Information's story, which cited two Nvidia employees, said the chip is a variant of the Groq 3 LPU Nvidia announced at GTC in March, and that its silicon is unchanged because it already falls within U.S. export rules.

The LPU was designed as a decode co-processor for the Vera Rubin platform, and Vera Rubin can't be sold in China. The Information's sources said Nvidia rewrote the software that splits work between the GPU and the LPU so the accelerator can run alongside processors that are available in the country.

The publication said Nvidia didn't respond to requests for comment over several days before publishing, and that it's unclear whether Beijing would allow the orders to proceed. Chinese officials blocked purchases of the H20 last year and only recently told companies they'd permit some H200 imports, so U.S. compliance alone doesn't guarantee the chips can be delivered.

Back in March, it was reported that Nvidia was preparing LPUs for China, with Jensen Huang saying two days later that the story was "totally false.” Thursday's statement is narrower than Huang's, addressing current sales and a China-specific product. Nvidia hasn’t clarified whether the standard LPU will ship to Chinese buyers. Huang told CNBC in May that Nvidia had "largely conceded" China's AI chip market to Huawei.

The Groq 3 LPU is built on Samsung's 4nm process with 512MB of SRAM per die and no HBM, and Nvidia said at GTC that it would ship in Q3 2026 to customers including OpenAI. U.S. export thresholds for China are set on compute density and bandwidth, and an SRAM-only decode accelerator with no HBM stack is the kind of part that can still be exported under them without a cut-down SKU, which is the mechanism The Information's sources described.

Huawei's Ascend 950DT, which the outlet named as the LPU's direct competitor, is optimized for decode and training and is due in Q4 2026, with the prefill-focused 950PR already in production since April. ByteDance and Tencent each took delivery of roughly 10,000 H200s in recent weeks, according to a Financial Times report this week, the first meaningful Nvidia accelerator volume to enter mainland China since December's U.S. approval.

Synopsys has published silicon results for what it calls the first 3D PCIe 6.0 test chip, a 5nm PHY built into a face-to-face stacked package that runs 64 GT/s per lane and up to 128 GB/s across an eight-lane link using PAM4 signaling, with receiver eyes clearing the standard's bit error rate requirement. The company says it got there by pulling apart an existing 2D PCIe 6.0 test chip, adding through-silicon vias, and redoing circuit design and signoff against 3D process design kits, according to its blog post.

In monolithic chips, PCIe PHYs sit at the perimeter of the die, right next to the package I/O connections, helping keep traces to the substrate short so attenuation and reflections remain manageable. A 2.5D package preserves that layout by parking the PHYs along the outer edge of the outermost chiplets. Face-to-face hybrid bonding removes the option. The bottom die is flipped so its redistribution layer meets the redistribution layer of the logic die above it, which leaves the PCIe PHYs facing away from the substrate they need to reach. Instead, the signals travel down through vias cut into the silicon.

Every TSV passes through active silicon and needs a buffer around it, so the vias can't be dropped wherever the PHY happens to sit. "You rarely drill straight down into the package substrate," Manmeet Walia, executive director of product management at Synopsys, said to Electronic Design, which reported that routing has to climb to one of the upper metal layers and reverse direction before descending.

Walia told the publication that electromigration and layout rules change substantially in 3D, that via count is a tradeoff between bandwidth and signals corrupting each other, and that customer logic sitting over the PHY's path down to the substrate is a challenge that Synopsys expects to work through iteratively, design by design. PAM4 leaves less room for that kind of error than the NRZ signaling used through PCIe 5.0, since it packs two bits into each symbol.

Fujitsu's Monaka processor takes the opposite approach, instead stacking four N2 compute chiplets carrying 144 Armv9 cores face-to-face on N5 SRAM chiplets using hybrid copper bonding, then putting the memory controllers and the PHYs for its 12 DDR5 channels on a separate and comparatively large I/O die rather than inside the bonded stack.

PCIe generations arrived roughly five to seven years apart for most of the standard's life and now release about every two years, with the Gen 8 specification due in 2028 at 256 GT/s per lane. Walia told Electronic Design that a further shift is coming with 3.5D packaging, where the PCIe PHYs get stripped out of the bottom die entirely, replaced with UCIe, and relocated to a side chiplet on the interposer that acts as a multi-protocol hub for Ethernet, PCIe, and CXL. Synopsys hasn't put a date on that. Its blog says leading-edge customers are evaluating angstrom-class process technologies for the top dies in their stacks.

SMIC posted its first $3 billion quarter earlier this month, with revenue up 36.1% year on year, net profit nearly tripling to $479.2 million. Co-CEO Zhao Haijun told analysts the next day that the Shanghai foundry will charge more for wafers processed in the third quarter after price negotiations concluded in the first. Utilization hit 93.7% against demand Zhao said SMIC can't fully meet, driven by Chinese AI data center buildouts that U.S. export controls have cut off from TSMC and Samsung at the leading edge. "Since there's still a big gap between industry-leading wafer prices and SMIC's current prices, we need to negotiate with customers for fairer pricing," Zhao said on the call.

The quarter blew SMIC's own out of the water on every front. The company had guided to 14% to 16% sequential revenue growth and a 20% to 22% gross margin; it delivered 20% growth to $3.01 billion and a 25.3% margin, up from 20.1% in Q1. Wafer shipments rose 14% quarter-on-quarter to 2.9 million 8-inch equivalents, blended selling prices climbed 5.7%, and Q3 guidance calls for a 26% to 28% gross margin. China accounted for 90% of revenue.

Demand isn’t coming from GPUs, however, with Zhao commenting that the surge came mostly from AI chips other than CPUs and GPUs, such as logic ICs, BCD power-management parts, and optical transceiver components, all in short supply. Meanwhile, growth in SMIC’s AI peripheral segment is expected to be around 40% for the quarter, while industrial and automotive chips rose to 16.5% of wafer revenue from 10.6% a year earlier.

From bust to boom

SMIC's utilization sat at 68.1% in the first quarter of 2023 and averaged 75% that year as net profit fell more than 60% and gross margin dropped 16.4 points to 21.9%. As late as early 2025, it was reported that SMIC and Hua Hong were cutting mature-node prices to defend share against a wall of new Chinese capacity. The company that spent 2023 and 2024 discounting into overcapacity spent 2026 raising prices by around 10% in December, negotiating targeted increases in capacity-constrained segments in February, and applying another round to Q3 wafers.

Export controls did most of the work, with Washington’s restrictions keeping China's AI accelerator demand away from TSMC. Beijing has been redirecting that demand inward: the government wants 70% of silicon wafers sourced domestically this year, and a Bloomberg Intelligence survey of 60 Chinese tech executives in June found firms plan to spend 46% of their AI accelerator budgets on local chips over the next 12 months, up from 30% now. SMIC is the only Chinese foundry that mass-produces 7nm-class logic, which makes it the sole domestic route to silicon for Huawei's Ascend line and Cambricon's accelerators. A protected buyer pool, along with a mandated shift to domestic supply and a single qualified supplier at the leading edge, produces a textbook seller's market.

Hua Hong, China's second-largest foundry, reported utilization of 102.8% in the same week, with record revenue of $717.5 million, up 26.8% year on year. TrendForce data shows foundry prices across China rose 5% to 15% between Q1 and Q2, with a third round of increases being prepared for the second half. TSMC is reportedly raising prices across all its advanced nodes too, so SMIC's hikes track a global trend, but SMIC is doing it from a captive position TSMC doesn't have: its customers have no other choice.

China's AI chip designers post record first halves

Cambricon's first-half revenue rose 108% to 6 billion yuan (c. $890 million) with net profit up 122.6% to 2.3 billion yuan, per its Shanghai Stock Exchange filing reported by the South China Morning Post. Moore Threads grew first-half revenue 147% to 1.74 billion yuan and cut its net loss by 96%, and Biren projected first-half revenue growth of more than 1,850% off a small base ahead of a Hong Kong IPO. Memory maker CXMT raised $8.6 billion in Shanghai's biggest-ever semiconductor listing last month and surged 466% on debut to become the most valuable company on any mainland exchange. Every one of these firms sits on the U.S. Entity List or depends on suppliers that do, and every one just posted record or near-record numbers.

Beijing had until recently been blocking Chinese imports of U.S. accelerators. The US approved around 10 Chinese firms to buy Nvidia's H200 in May, but China had been blocking the purchases to protect domestic suppliers. Under Secretary of Commerce Jeffrey Kessler told a congressional hearing on July 14 that "very few" H200s had actually shipped. Officials have relented as of August 19, with ByteDance and Tencent each having received around 10,000 H200 chips, the first meaningful deliveries since the U.S. approved around 10 Chinese firms as buyers.

Some 20,000 delivered accelerators against Huawei's target of 600,000 Ascend 910Cs this year leaves Chinese cloud spending, which Goldman Sachs pegs at roughly $102 billion for 2026 in combined AI capex across Alibaba, Tencent, ByteDance, and Baidu, landing overwhelmingly on domestic silicon.

SMIC's 7nm yields and the HBM shortage

SMIC's leading-edge economics remain brutal, however, with industry sources cited by the Financial Times putting SMIC's 5nm and 7nm prices 40% to 50% above TSMC's with yields of less than a third, a consequence of running multi-patterned DUV on nodes designed for EUV. The wafers SMIC is repricing are overwhelmingly mature-node parts, where its cost position is sound; the advanced capacity that feeds Ascend production stays yield-limited and expensive per good die regardless.

Memory, not logic, caps accelerator output anyway, and SemiAnalysis estimates Huawei has been drawing down a stockpile of roughly 13 million Samsung HBM stacks acquired before the late-2024 controls, and domestic HBM from CXMT will cover only a fraction of 2026 Ascend targets.

SMIC's own profit surge also comes with a glaring asterisk: CFO Wu Junfeng said the near-tripling was boosted by a one-time gain from a subsidiary. Demand for its silicon rests largely on policy rather than proven end markets, with an analyst tally cited by Asia Times putting China's top 11 listed chip firms at a combined average of roughly 122 times projected 2026 earnings.

Japanese chemical maker Ajinomoto has reportedly told customers in mainland China that it will cut supply of ABF, the insulating build-up film that's used in nearly every high-end processor package, by 30%, according to a report from the Chinese outlet JW Insights, which cites unnamed supply chain sources.

If true, that would be painful for Chinese customers like Shennan Circuits, Xingsen Technology, and Shenghong Electronics, who rely on Ajinomoto's reported 95% global market share of the film. In contrast, China's self-sufficiency rate is thought to sit below 5%.

JW Insights attributes the cut to Ajinomoto prioritizing Japanese customers and core overseas accounts, which supply the FC-BGA substrates under Nvidia, AMD, and Intel accelerators, over mainland buyers. Whether or not the 30% figure holds up, the squeeze is well documented, and China's response was underway long ago.

A confirmed shortage

Ajinomoto's ABF production ran at roughly 2 million square meters per month at full utilization in the second quarter. The company has committed ¥25 billion (around $156 million USD) since 2023 to expand capacity by about 50% by 2030, and land purchased in Kani City, Gifu Prefecture, hosts a third plant not expected to come online until around 2032.

In the fiscal year ended March 31, Ajinomoto reported that ABF sales grew 25% with margins above 50%, and the share of its film going into servers and networking silicon reached 70%, up from 40% in fiscal 2017. According to Goldman Sachs, the gap between ABF substrate supply and demand will widen from around 10% in the second half of 2026 to 21% in 2027 and 42% in 2028.

Ajinomoto notified substrate makers in May of a roughly 30% price hike taking effect this quarter, two months after UK activist fund Palliser Capital disclosed a top-25 shareholding on March 31 and publicly demanded the company raise ABF prices by more than 30%. That hike is confirmed, even if the volume cut isn't. ABF material accounts for about 30% of a substrate's bill of materials, so the increase flows directly into the cost of every FC-BGA package built on it. We've been tracking ABF crunches since the shortage that constrained GPU production in 2021 and 2022, and the current cycle looks to be extending a pattern that's already hit BT resin substrates and T-glass cloth, where single Japanese suppliers also dominate.

China has three films in qualification

Huazheng New Material's CBF, developed with the Shenzhen Institute of Advanced Electronic Materials, is the most mature of China's three named alternatives. The film uses a modified epoxy resin with spherical silica filler, which routes around Ajinomoto's IP rather than copying it. According to reports coming from Chinese media, its mass-production yield sits at above 85%, with reliability testing reportedly having passed inside Huawei Ascend systems and validation underway at Xingsen and Shennan Circuits. Huazheng's first production line of 3 million square meters per year is said to be running at full utilization, and a second line doubling that is slated to come online at the end of 2026.

Lotus Holdings, best known in China as a producer of MSG, acquired 51% of Shenzhen Newface, the developer of NBF, in April for roughly ¥103 million. Newface is said to have qualified all products below nine build-up layers, with nine- to 11-layer films in development and validation underway at Taiwanese substrate makers. Ajinomoto itself is a food and seasonings company that derived ABF from its amino acid chemistry in the 1990s.

Hongchang Electronics' GBF, co-developed with Taiwan's Jinghua Technology, has been validated at a leading domestic OSAT and is in small-volume trial production, with scale-up targeted for the fourth quarter. All three films face the same challenge of downstream reliability qualification taking one to three years of thermal cycling, damp-heat aging, and electrical testing, often longer than the R&D itself, and the highest layer-count films under flagship AI accelerators remain unmatched domestically. Upstream inputs, including specialty resins and spherical silica filler, are themselves partly import-dependent.

Huawei's Ascend packaging sidesteps ABF

Huawei's Ascend 910C reportedly connects two compute dies on separate silicon interposers through an organic substrate, an approach SemiAnalysis has described as trading die-to-die bandwidth for yield and cost against Nvidia's CoWoS.

That architecture makes Huawei less dependent on the high layer-count ABF-based FC-BGA substrates that Nvidia's B200 and GB200, AMD's MI300X, and Intel's accelerators sit on, and Chinese reporting seems to position Ascend as the anchor qualification target for both CBF and GBF. Cambricon, Biren, Moore Threads, and Alibaba's T-Head, which package on conventional FC-BGA, are directly exposed to any mainland ABF supply disruptions.

China banned exports of dual-use items to Japanese military-linked end users back in January through Ministry of Commerce Announcement No. 1, following Prime Minister Sanae Takaichi's November remarks on a Taiwan contingency, with measurable fallout. Chinese exports of restricted rare earths to Japan fell roughly 51% year-over-year in the first half of 2026, Nikkei Asia reported, and Japan imported just 13 tons of dysprosium in the period, down 82% from two years earlier, per TrendForce.

Ajinomoto's move to cut ABF supply to China eight months later has obvious retaliatory optics, despite every account of the alleged cut attributing it to capacity allocation under AI demand. China's rare-earth controls have so far targeted materials where China holds the leverage, and ABF is a market where it holds none.

Meanwhile, BOE signed a three-year glass substrate agreement with Corning in May and designated glass-core packaging a strategic business in July, and Lens Technology announced a through-glass-via collaboration with Intel the same month, extending China's push into glass substrates as the longer-term route around Japanese film.

A glass core swaps out the middle layer of a substrate, but the chip package still needs insulating film built up on either side, so glass doesn't remove the need for ABF or its substitutes. None of China's glass projects has reached mass production either. Until that changes, China's answer to the reported cut depends on whether Shennan, Xingsen, and Shenghong qualify their domestic films.

Intel is set to raise $19.7 billion by selling new common stock in a bid to finance the building out of new production capacity, the development of next-generation leading-edge process technologies like 14A and others, and day-to-day operations. While the company does not assign money to a particular project, Intel needs to build capacity to land orders from large external clients, so capacity expansion will likely be a priority. According to Bloomberg, the share sale attracted $100 billion in demand.

Intel will sell 210,526,315 shares for $95 apiece through an underwritten public offering. In addition, participating banks have 30 days to acquire as many as 31,578,947 more shares at the same $95 price, minus applicable underwriting discounts. Should they exercise all their options, Intel could sell approximately 242.1 million shares altogether and increase the proceeds to roughly $23 billion. Without the additional shares, Intel expects net proceeds of approximately $19.7 billion after underwriting discounts, commissions, and estimated expenses. The transaction is scheduled to close on August 12, 2026.

Intel's market capitalization increased from roughly $90 billion last August to $491 billion at press time, so the time is right to sell some shares and raise some much-needed cash, as the company must compete against giants like TSMC and Samsung, which spend tens of billions of dollars every year on new fabs and advanced process technologies. Meanwhile, Intel's capitalization reached its all-time high of $673 billion on June 20, 2026.

Intel has not assigned the money it is going to raise to particular projects and says the capital can be used across the business, including for capital expenditures and working capital. The company is currently ramping up its Fab 52 in Arizona and is on track to start using adjacent Fab 62 when it needs to. In addition, the company still has to build its fab complex in Ohio, which is expected to cost over $100 billion when fully built, so it badly needs money.

In its risk disclosures, the company specifically mentioned Intel 14A — which is due to enter mass production in 2028 — and other advanced process technologies, manufacturing expansion required to support them, and the need to secure design wins and volume commitments from major external foundry customers. While Intel does caution that these long-term investments amounting to tens of billions may not generate adequate returns, it is impossible to land sizeable contracts from external customers without having production capacity readily available.

Interestingly, Intel also mentioned alternative financing arrangements, government grants, and the U.S. government's significant equity position in the company among relevant factors.

House Select Committee on China Chairman John Moolenaar has written a letter that demands the U.S. government enforce an existing export control measure designed to prevent Chinese companies from getting advanced chips produced by contract chipmakers like TSMC or Samsung Foundry.

When Joe Biden was about to leave the office in early 2025, he signed a law that required chipmakers to determine their end customers in a bid to prevent contract manufacturers from unknowingly fabricating chips using American technologies for companies that served as intermediaries for restricted organizations tied to the Communist Party or the People Liberation Army. The regulation was introduced after it was discovered that chips made by TSMC for China-based Sophgo were actually Huawei's Ascend 910B AI accelerators. However, the Trump administration announced in May 2025 that it would not enforce this semiconductor regulation known as the 'Foundry Due Diligence Rule,' which naturally created uncertainty about whether the foundry-focused requirements would be actively implemented at all.

"The announcement created ambiguity as to whether front-end fabricators like TSMC can export unpackaged advanced dies to non-approved designers located outside of China, without performing the due diligence specified in the Foundry Due Diligence Interim Final Rule (IFR)," the letter reads. "These exports enabled Huawei to obtain millions of controlled Ascend logic dies from TSMC, using its front company, Sophgo in 2023 and 2024."

Before the adoption of the 'Foundry Due Diligence Rule,' Chinese companies and/or their intermediaries could misrepresent chip specifications and end users when placing orders with TSMC or other foundries, which allowed restricted devices to be made despite U.S. export controls. Under the rule, foundries and OSAT providers exporting chips produced on 14/16nm-class process technologies or more advanced nodes must presume those devices qualify as controlled AI processors subject to a global licensing requirement, unless they meet an exemption. According to the letter, foundries have generally complied with these requirements since the rule took effect. As a result, Moolenaar essentially asks the government to enforce the existing controls rather than introduce stricter export controls.

Moolenaar believes that the Commerce Department's Bureau of Industry and Security could clarify its current stance on the Foundry Due Diligence Rule in two ways:

• By issuing guidance, which confirms that the worldwide Regional Stability (RS) licensing requirement still applies to exports from front-end foundries;
• By formally annulling the AI Diffusion IFR and amending §744.23 to explicitly restore that requirement for both foundries and OSAT providers.

Either approach would eliminate conflicting interpretations and reinforce enforcement of existing export controls, Moolenaar believes.

Apple used to be among a few companies willing to buy memory and other components worth billions of dollars under long-term supply contracts at fixed prices. But the artificial intelligence era represents a new reality with new purchasing champions, marking a tectonic shift in the high-tech world. Alphabet, Microsoft, Meta, and Amazon have purchase commitments totaling about $2 trillion, and a significant portion of these commitments are for memory, according to estimates by analyst Claus Aasholm. While the commitments are approximate, span many years, and should be generally taken with a grain of salt, they still reflect the direction the industry is moving.

Combined purchasing commitments from the four major hyperscalers shown in the chart —Amazon, Alphabet, Meta, and Microsoft — reached nearly $2 trillion by Q2 2026, with Alphabet and Microsoft accounting for the overwhelming majority of the total.

The rapid expansion suggests several major findings. Firstly, the AI infrastructure race is accelerating, not stabilizing. Secondly, AI infrastructure investments are driven by a handful of hyperscale cloud service providers (CSPs) whose long-term procurement commitments now vastly exceed those of traditional consumer electronics companies such as Apple.

Thirdly, memory has become a strategic asset — perhaps a competition weapon — rather than a commodity. Fourthly, suppliers of memory — both 3D NAND and DRAM — are gaining pricing power. Finally, demand for memory will likely drive major capacity expansion at Micron, Samsung, and SK hynix, even though so far these companies have been exceptionally disciplined about their capacity investments.

Almost $2 trillion commitments

Google shows by far the most aggressive increase in purchasing commitments, rising from roughly $140 – $150 billion in Q3 2025 to around $811 billion by Q2 2026 (though these are total purchase commitments by Alphabet, not specifically memory purchase commitments), while Microsoft follows a similar trajectory and reaches approximately $678 billion in total obligations, which includes, but is not limited to memory.

Meta is also ramping commitments substantially to around $349.3 billion (again, these are total commitments), whereas Amazon increased its commitments more gradually to roughly $130 billion. By contrast, Apple — which makes the world's most popular smartphone, and which was the largest consumer of memory just a couple of years ago — remains almost flat throughout the period at approximately $57 billion (of which $56.2 billion is payable within 12 months). Apple's commitments fall well short of Nvidia's commitments of $119 billion.

Again, we are talking about total purchase commitments, which include foundry capacity, 3D NAND, and DRAM memory, but are not limited to them. Alphabet, Amazon, Meta, and Microsoft all build custom silicon and custom servers, so a significant portion of these commitments is to various EMS providers.

While $1.968 trillion of purchase commitments for memory and storage alone would be an absurdly large amount of money, a huge portion of these commitments consists of contract manufacturing obligations as well as memory chips. This suggests that the foundry, 3D NAND, and DRAM markets are entering a new phase in which hyperscalers are willing to make vastly larger forward purchasing commitments than traditional consumer-electronics companies, giving suppliers a strong incentive to prioritize customers prepared to secure future capacity on that scale.

Strategic assets

While Claus Aasholm's chart is explicitly dedicated to memory, it does describe total purchase commitments of tech giants, so the chart can reasonably be read as evidence that memory and capacity at TSMC, Samsung Foundry, and GlobalFoundries are becoming a strategic asset rather than merely another component to procure at the best available price.

AI infrastructure requires enormous quantities of AI accelerators, DRAM (including HBM), and 3D NAND. Meanwhile, the supply of high-end memory (HBM) is constrained by fab capacity at major DRAM makers, whereas the supply of AI accelerators is constrained by both wafer capacity and foundries and packaging capacity at foundries and their OSAT partners. As a result, hyperscaler CSPs have an incentive to lock in supply years ahead, even if doing so requires exceptionally large purchasing commitments.

That also changes the relationship between semiconductor suppliers and their customers. In theory, a company willing to guarantee hundreds of billions of dollars of future purchases can effectively help underwrite expansions of foundry, memory, and advanced packaging capacity and, in return, secure priority access to scarce products and future process technologies. In reality, TSMC can well afford capacity expansion using the money it gets from hyperscalers and give priority to its largest customers. In this environment, access to DDR5, HBM, and 3D NAND memory becomes part of the competitive advantage rather than merely a procurement exercise.

This is also what makes Apple's position in the graph interesting: its purchasing commitments barely move while those of Alphabet, Amazon, Meta, and Microsoft surge. If the trend continues, Apple may remain one of the world's largest semiconductor buyers in absolute terms, but the question is whether it will be among the key customers that foundries, memory makers, and OSATs plan their future capacity expansions.

An inflection point

Perhaps the most interesting takeaway of the findings revealed by long-term purchase commitments is that the industry's center of gravity appears to have shifted.

During the smartphone era, foundries (well, TSMC has won) and memory suppliers often competed aggressively for Apple's business because of its enormous purchasing power. Today, hyperscalers building AI infrastructure are making purchasing commitments that dwarf those of traditional CE companies like Apple, which may well represent a strategic inflection point akin to the one Andy Grove described in his 'Only the Paranoid Survive' book.

Will this tectonic shift result in prioritization of customers capable of enabling future capacity expansions through massive long-term purchase agreements, or will foundries and memory makers remain more or less disciplined with their capacity expansions so as not to lose a lot when demand declines? This is a question that has yet to be asked.

In any case, the AI megatrend has transformed semiconductors — from foundries to advanced packaging and from DDR5 to HBM4 — into strategic assets that can no longer be treated as ordinary components procured on demand. And this is something that will continue in the long run.

Most megafactories usually take years to go from conceptualization to construction, but a recent drone flyover of the Terafab showed that progress has already started on the ground less than five months after Musk unveiled it. However, the video doesn’t do justice to the true scale of its footprint, so X user Nic Cruz Patane created a visualization to help us understand how large the chip manufacturing facility is.

The site will reportedly have a floor space of at least 100 million square feet, making it larger than Giga Texas (10 million sq. ft), the Pentagon (6.6 million sq. ft), Apple Park (2.82 million sq. ft), and the Mall of America (5.6 million sq. ft), combined. This also makes it significantly larger than New Century Global Center in Chengdu, China, with has an interior space of “just” 18.9 million sq. ft.

While this might seem like an absurd amount of space for chip manufacturing, it appears that the Terafab will need it because it’s going to be more than just a chip fab making AI processors — instead, it will be an all-in-one facility that will produce logic and memory chips, as well as have lithography, packaging, and testing under one roof.

Elon Musk started talking about building his own chip manufacturing facility in late 2025 and officially announced the project in March of this year. The reasoning behind this project is that both SpaceX and Tesla will require at least 1TW of compute, which is more than ten times that current global chip supply.

Nvidia CEO Jensen Huang warned that a project like this will be an “extremely hard” challenge, but it appears that Musk is willing to put his massive resources on the line for this. Intel CEO Lip-Bu Tan even said that he can “think of no better partner than Elon Musk” to explore “unconventional” ways of chip manufacturing.

Musk is no stranger to both leading and funding projects that otherwise seemed impossible. Although he did not found Tesla, his investment and leadership in the company led it to become an industry trailblazer in EVs. He fundamentally changed commercial space travel with SpaceX; something that used to be the purview of NASA and other national governments, and he also broke a record when he set up 100,000 Nvidia H200 GPUs in just 19 days back in 2024 — a process which Huang said usually takes four years.

It seems that Terafab is Musk’s biggest project to date, which is estimated to require up to $119 billion in investments. But even though it seems that this project already has a secure customer base in SpaceX and Tesla, the former acknowledges that there’s a risk that this ambitious megafactory may not be successful.

SpaceX and Tesla on Thursday formally unveiled plans for the initial phase of their Terafab project. The first stage of the plan — which is expected to use Intel's 14A process technology — is expected to require $16.8 billion in investment, while the completed campus is planned to encompass more than 100 million square feet of manufacturing space. The massive semiconductor manufacturing complex will be built in Grimes County, Texas, at a location that belongs to SpaceX.

According to SpaceX and Tesla, their combined demand for semiconductors is projected to exceed 1 terawatt (TW) of compute per year, which significantly exceeds today's global supply. In fact, SpaceX, Tesla, and xAI already consume a significant portion of contract chipmaking services available today, and can potentially justify building a dedicated fab that will exclusively serve Elon Musk's companies. In particular, Terafab is envisioned to exclusively produce AI inference processors for Tesla Optimus humanoid robots and Cybercab autonomous vehicles, as well as 'high-power' processors intended for SpaceX's space-based data centers. Meanwhile, SpaceX and Tesla have not disclosed when their combined demand for compute per year will hit the 1 TW benchmark.

Unlike a conventional semiconductor fab, Terafab is envisioned as a vertically integrated manufacturing campus where advanced logic devices, memory chips, packaging, and testing operations are housed together. Normally, logic and memory are produced at different fabs using different process technologies, whereas packaging and testing services are performed at different facilities. However, the companies believe that consolidating logic, memory, packaging, and testing in one location will not only shorten the production cycle but will also shorten time-to-yield by enabling faster iterative improvements.

Given the description and the goal of the project, this will be a massive facility. Yet, SpaceX and Tesla have said little about its capabilities; The only thing they have disclosed is that the current facility in Grimes County will feature '100 million square feet of manufacturing space.' The 100 million square feet (9.3 million square meters) figure immediately stands out because it is far beyond anything ever announced for a semiconductor manufacturing facility. For example, the total area of Samsung's Pyeongtaek campus is approximately 2.89 million square meters, or 31.1 million square feet. A single Samsung fab occupies about 120,000 square meters, or 1.29 million square feet. However, the key wording is important: '100 million square feet of manufacturing space' does not mean 100 million square feet of cleanroom space.

Based on an image published by SpaceX, the Terafab facility will occupy four massive buildings. It is unclear whether these buildings will be four phases of the project (i.e., logic, memory, and packaging will be made under one roof) or will serve different purposes (i.e., one building makes logic, another produces memory, yet another does testing and packaging). In any case, when fully built, Terafab will be a massive semiconductor production campus that will require significantly more than $16.8 billion.

The announcement claims that the Terafab facility will employ at least 3,000 people, and that between 60% and 80% of them will be Grimes and nearby Brazos County residents.

Terafab is expected to use water from Gibbons Creek Reservoir instead of local groundwater and feature on-site wastewater treatment as well as water recycling and conservation measures.

The announcement follows Tesla's groundbreaking earlier this year on a research semiconductor facility at the North Campus of Tesla's Giga Texas campus, which the companies describe as a precursor to Terafab.

China has started low-volume production of domestically developed immersion DUV lithography machines, with around five systems planned for this year and roughly 20 in 2027, according to a report from July 27, which wiped roughly $44 billion off ASML's market value.

The manufacturer was named as Shanghai Aishengna Electronic Technology Group by Reuters the following day, a state-owned company established in August 2023 with 7 billion yuan (around $1 billion) in registered capital that absorbed engineering teams from Huawei-affiliated startup Yuliangsheng and state scanner maker SMEE. The first units are due at SMIC, Hua Hong, and CXMT this year for production-line validation rather than volume output, but the machines are far from matching ASML's models and still require further testing.

Five machines represent about 3.8% of the roughly 130 immersion systems ASML deploys in a typical year (a class of lithography machines that put a super thin layer of liquid over the wafer during processing), with the European giant holding an estimated 98.7% of the total immersion market. The Chinese tool reportedly prints 28nm-class features in a single exposure and reaches 7nm, and theoretically 5nm, through multipatterning, the same route SMIC already runs on its installed ASML fleet. Neither company has confirmed the report, no machine has been shown publicly, and no throughput or overlay figures have been disclosed, against the 330 wafers per hour and 2.5nm overlay of ASML's current flagship immersion tools.

SMIC’s scanner

SMIC has been running a domestic immersion scanner, developed under the codename Mount Everest, since September last year, when the Financial Times reported that China's largest foundry had begun testing the Yuliangsheng tool with production-line integration targeted from 2027 after qualification.

FT compared the machine against ASML's Twinscan NXT:1950i, a system that entered the market in 2008, which puts the design roughly a decade and a half behind the tools ASML sells today. Yuliangsheng, founded in Shanghai in 2022 with 1 billion yuan (around $149 million) in registered capital, is understood to have delivered three lithography machines to fabs for testing by late last year, but this hasn’t been officially confirmed.

Many of the critical components needed for the machines are still imported from Japan, and delays at those local suppliers are what have capped 2026 output at around five units. The 2027 target of 20 machines is therefore an ambitious target that assumes a domestic component base that hasn't been established yet, and the imported parts remain within reach of any future export-control round.

18% litho localization

SMEE's most advanced shipping product remains the SSA600 series, a 90nm-class dry ArF scanner that was in mass production as of May last year. The 28nm-capable SSA/800 immersion tool the company announced in 2023 has never been deployed, and a state-media claim of its successful development was deleted shortly after publication. In December last year, SMEE won a roughly RMB 110 million ($16 million) single-source government contract for a KrF scanner specified at 110nm resolution and 15nm overlay, a useful indicator of where its production-grade capability is at the moment.

Domestic equipment took 35% of Chinese fab purchases in 2025, beating Beijing's 30% target and up from about 10% three years earlier, according to figures from China's semiconductor industry association. Etch and thin-film deposition passed 40% localization, and metrology reached 25%, while lithography managed just 18%, most of it in trailing-edge and packaging tools. From the end of 2025, new fab capacity additions are required to source at least half their equipment domestically, a mandate that guarantees the new scanners a customer base, whatever their specs turn out to be.

Etch, deposition, and everything else

Naura Technology became the world's fifth-largest chip equipment maker by 2025 sales, trailing only ASML, Applied Materials, Lam Research, and Tokyo Electron, and moving ahead of KLA. The company booked RMB 27.14 billion ($4 billion USD) in revenue in the first three quarters of 2025 against RMB 6.05 billion ($589 million USD) for all of 2020, holds an order backlog stretching into 2027, and has started developing lithography tools for the first time. AMEC grew revenue and net profit by more than 30% in 2025, while cleaning specialist ACM Research posted $901.3 million for fiscal 2025 and guided to as much as $1.18 billion for 2026.

SiCarrier, the Shenzhen firm widely linked to Huawei, debuted around 30 tools at SEMICON China in March 2025, spanning etch, deposition, metrology, and test, and was reportedly valued at RMB 65 billion ($9.63 billion USD) by September 2025 with more than RMB 10 billion ($1.48 billion USD) in orders. The U.S. added it to the Entity List in December 2024.

The sector's own leadership is less triumphant than the numbers suggest. In March, SMIC co-founder Wang Yangyuan and the heads of YMTC, Naura, and EDA firm Empyrean jointly described China's tool industry as "small, fragmented, and weak" and called for national consolidation, with Big Fund III's $47.5 billion being redirected toward lithography and EDA. The Aishengna venture, which merged the Yuliangsheng and SMEE teams into one state-owned vehicle, looks like the first product of that pressure to consolidate. China spent a record $49.5 billion on wafer fab equipment in 2024, per SEMI, and remains the world's largest buyer through 2027, even after a pullback in 2025.

EUV lithography

A Reuters investigation in December 2025, dubbed China’s “Manhattan Project,” described an operational prototype EUV light-source machine in a high-security Shenzhen lab, completed in early 2025, that generates EUV photons but hasn't yet exposed a wafer. More than 3,000 researchers are said to work across the program, with Huawei playing the coordinating role and SMEE handling system integration.

Two teams are chasing the light source: one led by Lin Nan, a Beihang University professor who worked at ASML from 2015 to 2021, has a solid-state laser-produced-plasma design running at 3.42% conversion efficiency against the roughly 5.5% commercial viability required, while Zhao Yongpeng's laser-assisted discharge plasma group at Harbin Institute of Technology has reached around 100W of EUV output against the roughly 600W that ASML's production sources deliver.

Beijing's target is chip output from the machine by 2028, with Reuters' sources calling 2030 more realistic. A separate strand of reporting described a reverse-engineered prototype built around an intercepted Cymer light source that has likewise produced nothing. Earlier claims of a Huawei EUV trial production in 2025 and mass production in 2026, which circulated via Chinese media in March 2025, were never confirmed by any primary source. Tsinghua University's accelerator-based SSMB concept, which would need a synchrotron of a staggering 100 to 150 meters in circumference, remains an academic project.

Export controls

The MATCH Act, introduced in the House and Senate in early April, would ban not only sales of immersion DUV tools to SMIC, Huawei, Hua Hong, CXMT, and YMTC but also the servicing of machines already installed, and would give the Netherlands and Japan 150 days to align.

At this stage, it remains a bill, not a law, but servicing restrictions would strike directly at the installed ASML base that produces every advanced chip China currently makes, including SMIC's N+3 node in Huawei's Kirin 9030. Chinese fabs have been preparing for exactly that scenario by using third-party engineers and gray-market parts to Frankenstein older ASML machines.

ASML's China exposure is already shrinking on schedule, with the country representing 20% of system sales compared to 41% in 2024 and 33% last year, even as the company raised full-year guidance to €43 to €45 billion in July. Likewise, Applied Materials expects to lose $600 to $710 million in China revenue this fiscal year.

Ultimately, three markers will indicate whether China’s domestic DUV program is a legitimate rival or yet more state-sanctioned hot air. The main one would be validated production wafers from an Aishengna tool at SMIC, Hua Hong, or CXMT with published throughput and yield, followed by delivery of anything close to the 20 machines planned for 2027, and a first exposed wafer from the Shenzhen EUV prototype before the 2028 target set by Beijing.

China has revised its regulations concerning protection of integrated circuit (IC) layout designs developed domestically. The new regulations are intended to make it harder for Chinese companies to obtain legal protection for copied chip designs by tightening originality requirements, registration procedures, and infringement remedies, Reuters reports. As a result, it will get harder for underperforming China-based companies to copy ICs developed by their more successful rivals. Meanwhile, Chinese chipmakers will be allowed to produce their designs in Taiwan or South Korea.

The amended regulations apply to physical chip layout designs that define how circuit elements are arranged on silicon and represent a substantial amount of engineering work, including for companies that specialize in chip design rather than manufacturing. To qualify for legal protection of their IC layouts, applications must now demonstrate that the layout was independently developed, formally attest that the design is original, and specify which parts of the layout constitute their own creative contribution (perhaps to give authorities an idea about which were licensed or obtained from open sources). As a result, authorities will be able to filter out weak claims and distinguish companies with strong technological capabilities. Furthermore, they will also be able to determine whether a particular chip was designed and built in China, or its alleged developer obtained its product elsewhere and attempts to disguise it as a 'Made in China' silicon.

The new rules also strengthen enforcement. From mid-October and onwards, in infringement disputes, courts may determine compensation based either on losses suffered by the rights holder or profits earned by the infringing party. Punitive damages will also become an option. In addition, the regulations clarify procedures for licensing, transferring, or using IC layout-design rights as collateral. Organizations that develop protected layouts are also required to provide reasonable rewards and payments to personnel responsible for creating those designs.

Chinese policymakers were also reportedly considering measures to prevent strategically important domestic technologies from being transferred abroad, acquired by foreign companies, or produced overseas. If these strict proposals were approved by the CCP and the government, Chinese chip designers would be unable to produce their chips at TSMC in Taiwan or Samsung Foundry in South Korea, and would force them to exclusively make them domestically at Semiconductor Manufacturing International Corp., Hua Hong, and other domestic contract producers that are decades behind market leaders.

The report claims the updated regulations reflect the strategic importance China now assigns to technologies developed by its domestic semiconductor industry. For now, it is evident that China is not ready to implement overseas production of advanced designs. However, the report does not explicitly claim they are completely off the table, according to Reuters.

The updated rules were signed by Premier Li Qiang on July 23 and will take effect on October 15.

Drone flyovers of Elon Musk’s new Advanced Technology Chip Fab (ATCF) in Texas have been shared on social media. The videos and photos come courtesy of flight instructor and drone videographer Joe Tegtmeyer (@JoeTegtmeyer), who regularly documents the progress of Giga Texas and Starbase projects. Considering that the fab was only announced on March 21 this year, groundwork has been brisk, and in a follow-up post, Tegtmeyer states progress has “hit another gear.”

In the above post, the all-things-space enthusiast notes that the ATCF already appears to be very well defined. “GeoPiers are at work on the part of the foundation that has had gravel mix placed on the top soil and more work grading on the south end,” he explains.

A few days later, there was an update with progress clearly accelerating, according to Tegtmeyer. As well as commenting on the shape of the facility becoming ever clearer and construction materials continuing to be stockpiled, there are other important signs of progress. Specifically, “4 new permits were filed in the past few days for the large trailer complex that houses the general contractors and the temporary Tesla offices for the new facility,” noted the enthusiast. “[It is] a great sign that things are progressing rapidly behind the scenes to fit out the facility when construction progresses far enough to allow for equipment installation.”

Importantly, Tegtmeyer reminds his followers that the ATCF is not the Terafab that will be built ~ 100 miles or so to the East in Grimes County, Texas. Rather, the ATCF is the equally vital but “smaller development facility that is the first part of the overall AI Chip development program.”

The ATCF is a joint Tesla–SpaceX facility, and is a keystone for the Tesla, SpaceX, and xAI accelerator chips to come. It is expected that chips from the ATCF will combine logic, memory, and advanced packaging under one roof. Projects spawned from here are destined to support Tesla cars and Robotaxis, Optimus robots, and upcoming Earth-orbiting AI data centers.

That’s distinct from the much larger, multi-phase, vertically integrated, 1TW/year Terafab megaproject, which will see collabs between Tesla, SpaceX, xAI, and Intel. It has massive AI computer production ambitions to feed terrestrial and space-based AI systems. We are still awaiting evidence that the Terafab has moved beyond the pre-construction phase.

If there were any doubt about the seriousness of Musk's semiconductor design and fabrication ambitions in these and other progress reports, ASML CEO Christophe Fouquet recently confirmed talks with Musk had taken place about building one of the largest chip manufacturing operations ever attempted. SpaceX has also already filed for a $55 billion facility in Grimes County, Texas, with potential expansion costs reaching $119 billion, and phase one potentially beginning before the end of the year. Meanwhile, it is good to see the rapid progress of the smaller ATCF.

Lumentum CEO Michael Hurlston told an audience at the RAISE Summit in Paris earlier this month that indium phosphide, the compound semiconductor behind every laser in an AI data center, is heading into a supply squeeze worse than what we've already seen with DRAM / NAND, and that Nvidia's decision to fund Lumentum and its biggest competitor at the same time was a response to exactly that.

In his remarks, Hurlston said that telecom customers bought lasers in the hundreds, while Nvidia and the hyperscalers are asking for hundreds of millions. While Lumentum runs five indium phosphide fabs, it's still shipping more than 30% below what customers want. Nvidia's answer, in March, was to write $2 billion checks to Lumentum and Coherent, the two suppliers that, between them, make most of the world's high-speed datacom lasers, with purchase commitments and future capacity access attached to both.

"Between the two of us, I don't think we can service the demand that Nvidia and others are now putting on us to solve this resistance problem in the data center," Hurlston added.

Silicon doesn't emit light

Indium phosphide has a direct bandgap of roughly 1.34 eV, which lets it convert electrical current into photons efficiently. Silicon's bandgap is indirect, so it can guide, split, and modulate light but can't generate it. Every silicon photonics platform in production, including those of Nvidia, Broadcom, Marvell, and Cisco, still needs an indium phosphide laser somewhere in the package to supply the light for silicon to manipulate. Moving from pluggable transceivers to co-packaged optics changes where that laser sits and how it's mounted, but it doesn't remove it from the bill of materials.

Nvidia's marketing claims its photonics switches use four times fewer lasers than an equivalent pluggable deployment, alongside 3.5 times better power efficiency and ten times better network resiliency, all of which are vendor figures. Those savings are per port, and it's that port count that's exploding.

The high-end Spectrum-X Photonics configuration runs 512 ports at 800 Gb/s for 400 Tb/s of switching, and Quantum-X Photonics InfiniBand runs 144 ports at 800 Gb/s. Co-packaging also shifts the laser type toward high-power continuous-wave sources and external laser modules that feed multiple channels, which are harder to build than the electro-absorption modulated lasers inside a conventional pluggable. Coherent's Nvidia agreement covers that category of high-power CW lasers, external laser source modules, and fiber array units.

Capacity at Lumentum and Coherent

Lumentum posted record revenue of $808.4 million in its fiscal third quarter, up 90% year over year, with components revenue of $533 million and pump laser shipments up 80%. On the May earnings call, Hurlston told analysts the company expects its supply line to increase 50% measured from one December quarter to the next, and in the same breath said the supply-demand imbalance on EMLs had widened from the 25% to 30% given a quarter earlier to "somewhere greater than 30%," with pump lasers tighter still. A supplier growing output by half a turn per year and losing ground anyway is a clean measure of how steep the demand curve is.

Coherent's 6-inch indium phosphide line yields more than four times as many devices as its 3-inch line at less than half the cost, CEO Jim Anderson told investors on the company's fiscal Q3 call. Anderson said EMLs, CW lasers, and photodiodes are all in production on the 6-inch line with yields above the legacy 3-inch lines, and that internal capacity would double by the end of the June quarter, one quarter ahead of plan, then more than double again by the end of 2027. Coherent's revenue hit a record $1.8 billion, up 21%, with data center and communications now 75% of the total against roughly 41% a year earlier, and backlog stretching into 2028.

Logic and memory moved to 300mm wafers in the early 2000s. Indium phosphide is a brittle, expensive, small-boule material where the industry-wide upgrade currently underway is 3-inch to 6-inch, roughly the transition silicon completed in the 1980s. Lumentum's fifth fab, announced in March, is a converted Qorvo gallium arsenide plant in Greensboro, North Carolina, described as 4-inch and 6-inch compatible and ramping around 2028.

Running through China

Indium is recovered as a byproduct of zinc refining, so its output can't be scaled independently of zinc economics, no matter how much laser demand there is. The USGS Mineral Commodity Summaries 2026 put China at an estimated 760 tonnes of roughly 1,100 tonnes of global primary refined indium in 2025, about 69%, and recorded a 72% year-over-year fall in unwrought indium exports between September 2024 and September 2025 after Beijing placed the metal under export controls in February last year. The U.S. warehouse price averaged about $390 per kilogram in 2025 against $340 in 2024.

AXT's Chinese subsidiary Tongmei had to obtain Ministry of Commerce export permits, granted in June and August 2025, before it could resume shipping indium phosphide substrates out of China. The fabs Nvidia is funding sit downstream of that licensing regime, and the wafers going into them aren't made in the United States in meaningful volume.

DRAM contract prices rose 90% to 95% quarter over quarter in Q1 2026, the largest quarterly increase TrendForce has recorded, and the firm forecast a further 58% to 63% in Q2 with NAND up 70% to 75%. HBM is sold out for 2026. Hurlston is measuring his warning against a genuinely historic crunch, which makes it a strong claim rather than a throwaway one, and he runs a company whose valuation depends on the shortage persisting.

LightCounting's April 2026 market forecast puts current transceiver demand about 30% above supply, matching Lumentum's own figure, but states that the shortages should be gone by the end of 2026 and cuts expected Ethernet transceiver growth to 65% for the year after 82% in 2025 and 93% in 2024. Coherent, hitting its capacity doubling a quarter early, points the same way. The distinction from memory is that the fix here is a wafer-size transition already running in production with yields ahead of the old node, not a new fab that takes three years to build.

Reuters has named Shanghai Aishengna Electronic Technology Group as the state-owned company producing China's first domestic immersion deep ultraviolet lithography (DUV) scanners, a day after news of the program broke without identifying the manufacturer. Aishengna was established in August 2023 with RMB 7 billion, around $1 billion, in registered capital and is thought to have absorbed engineering teams from Shanghai Yuliangsheng Technology and Shanghai Micro Electronics Equipment.

Aishengna has been named by a single source who declined to be named, and its shareholders, SMEE and Yuliangsheng, didn’t respond to requests for comment. SMIC has been testing a Yuliangsheng immersion tool since September 2025, and first deliveries are slated for SMIC, Hua Hong Semiconductor, and ChangXin Memory Technologies.

Photoresist, coater tracks, and light sources

Tokyo Electron held an 89% share of the global coater/developer market in 2022, per Shared Research's analysis of the company's own disclosures, with its chief executive putting the figure near 90% and at 100% for EUV production. A scanner only exposes the wafer, however. It’s the track that's responsible for applying the resist film, baking it, and developing the pattern after exposure, and it has to be mechanically and thermally matched to the scanner in a single cluster, which is why the two are bought together. Shenyang Kingsemi has reached 28nm-class track capability and is currently targeting 14nm.

JSR, Tokyo Ohka Kogyo, Shin-Etsu, and Fujifilm hold a combined 72.5% of the ArF photoresist market, while Chinese suppliers hold under 1% of ArF immersion resist specifically. Nata Opto-electronic built a 25-ton ArF line, later expanded to 50 tons, passed customer qualification in December 2020, and completed project acceptance in 2024 with little volume to show for it. Xuzhou B&C says its ArF immersion products cover 45nm to 28nm and can stretch to 14nm, and chairman Fu Zhiwei has put mass production of China's core advanced resists five years out.

Cymer, Gigaphoton, and Coherent hold more than 80% of the ArF excimer laser market between them, and Cymer has been an ASML subsidiary since 2013. Beijing RSLaser shipped China's first high-power domestic excimer laser in 2018 under the national Project 02 program and has a 4 kHz 193nm ArF prototype aimed at 90nm and 65nm-class tools, generations behind what 28nm immersion requires.

Carl Zeiss SMT has been ASML's sole projection optics supplier since 1983, and Zeiss SMT revenue grew from €1.2 billion in 2016 to €4.1 billion in 2024. It’s not currently known what, if any, Japanese tooling is inside the Aishengna machines, but excimer sources and precision optics are areas where Chinese substitution is believed to be lacking.

CXMT

CXMT is projected to reach around 350,000 wafer starts per month by the end of 2026, roughly 25,000 short of Micron, up from 40,000 in 2020. DRAM scaling at 1a and 1b-class nodes runs on immersion multipatterning because CXMT has no EUV access, which makes any potential ramp lithography-gated rather than cleanroom-gated. DRAM contract prices rose 93% to 98% quarter on quarter in Q1 2026, and TrendForce projected a further 58% to 63% in Q2, lifting DRAM industry revenue 81% to $97 billion. A domestic immersion source is therefore worth having to CXMT, even at inferior overlay and throughput.

A DUV-only 7nm flow needs roughly 19 spacer-defined multipatterning masks from the front end through the second metal layer, against about 10 for an EUV-based N7+ process, by one published comparison of SMIC's process. SemiAnalysis has put SMIC's 7nm defect density near 0.14, around double TSMC's N5 and N6. ASML CEO Christophe Fouquet told analysts during the company's July earnings call that rising DRAM lithography intensity partly reflects "the increased replacement of multi-patterning with more cost-effective single-exposure EUV." As such, every exposure China adds to compensate for the missing EUV burns scanner hours a thin domestic fleet doesn't have.

The MATCH Act

China fell to about 14% of ASML's sales in Q2 2026 from 33% across 2025, and installed base management, the service and upgrade business, brought in €2.8 billion of ASML's €9.3 billion in second-quarter revenue. H.R. 8170 would ban both the export and the servicing of immersion DUV systems to any destination in China and designate SMIC, Hua Hong, Huawei, CXMT, and YMTC as restricted entities by statute. Former ASML chief executive Peter Wennink has said the company can service most Chinese tools, but not with spare parts of U.S. origin that fall under export control, which is the mechanism that the MATCH Act would widen.

The bill remains in committee after clearing the House Foreign Affairs Committee in April, with a Senate companion filed as S. 4281, and no floor vote yet scheduled. Its 150-day allied-alignment clause would also reach Nikon, which sold 11 ArF immersion systems in FY2024 and none in the first three quarters of FY2025, and which plans to deliver a new immersion prototype to a major chipmaker by 2027. ASML expects about 130 immersion shipments this year and intends to raise immersion capacity 30% in 2027, with a further 30% under investigation for 2028.

As for Chinese providers, SMEE prototyped its SSA600 ArF tool in 2011 and never reached sustained commercial sales, and a late-2023 shareholder claim that the company had developed a 28nm machine was subsequently retracted. SiCarrier showed etch, CVD, PVD, and ALD tools at SEMICON China 2025 without a lithography system, and a December 2025 government contract reported as a lithography award turned out to cover a KrF tool at 110nm. We’ve previously assessed that China’s toolmakers are more than a decade behind the market leaders.

The AI Futures Project's June forecast puts a commercially viable domestic 7nm-capable immersion scanner between 2032 and 2038, with a median of 2035, and claims ASML holds 98.7% of the immersion market today. Five machines in 2026 would be under 4% of ASML's annual immersion output, and each would still need a coater track, a qualified ArF immersion resist, and an excimer source to print a single wafer; China leads in none of those three.

A state-backed company in Shanghai has begun mass-producing immersion deep ultraviolet lithography machines and is due to deliver the first units this year to SMIC, Hua Hong Semiconductor, and memory maker ChangXin Memory Technologies, according to The Information, citing two people familiar with the program. Output targets around five machines in 2026 and roughly 20 in 2027, and all three named recipients sit on the list of Chinese firms that a bill now moving through Congress would cut off from ASML sales and servicing by statute.

The Information didn't name the manufacturer, but its sources described the operation as having pulled DUV development teams from several Chinese companies, one of them the state-backed startup Shanghai Yuliangsheng Technology. SMIC has been testing a Yuliangsheng immersion tool since September 2025. Most components in the new systems are domestic, though some critical parts still come from Japan, and delays at local suppliers have held back output this year.

U.S. House Resolution 8170 designates SMIC, Hua Hong, CXMT, Huawei, and YMTC as restricted entities in law, and three of those five are the named first customers for the domestic scanner. The MATCH Act, introduced in April, was reported out of the House Foreign Affairs Committee on April 22 and has a Senate companion filed as S. 4281. Its immersion DUV provisions cover servicing and technical assistance, not just new exports, which extends its scope to installed tools already operating in Chinese fabs, fabs which have spent the past two years stretching that installed fleet through secondary-channel upgrades.

ASML expects to ship about 130 immersion systems in 2026, matching 2025, CFO Roger Dassen told analysts during the company's July earnings call. Dassen added that ASML intends "to increase capacity by 30% in 2027" for immersion, and is investigating another 30% for 2028. China accounts for around 20% of ASML's net sales this year, down from 33% in 2025, driven mainly by mainstream logic demand.

Immersion DUV prints 28nm-class features in a single exposure and reaches 7nm through multipatterning, at a cost in overlay errors and yield. ASML CEO Christophe Fouquet told the same call that rising DRAM litho intensity partly reflects customers replacing multipatterning with cheaper single-exposure EUV.

Independent analysis from the AI Futures Project in June put commercial-scale Chinese immersion DUV in the mid-2030s, with ASML holding 98.7% of the immersion market. Qualifying the new machines for production lines could take many months, and they trail ASML's tools on performance and build quality. China's domestic EUV effort, which Reuters first reported as a working prototype in December, remains years away.

A new semiconductor firm, TYLsemi (pronounced Tile Semi), publicly revealed itself this month, alongside $43 million in early-stage funding and an ambitious plan to simplify the development of custom processors for AI infrastructure.

Dozens of contract chip designers can develop custom processors of different complexity. However, only a few companies can offer custom silicon design services using standard chiplets to speed up and derisk the development cycle. TYLsemi is aiming to join their ranks. We spoke to their founders to find out how the nascent business might pull it off.

Emerging from stealth

Rather than compete solely as another custom ASIC design house, TYLsemi intends to offer reusable, standards-based connectivity, power delivery, and eventually memory chiplets that customers can combine with their own differentiating compute silicon to build a unique system-in-package. For companies that do not intend to conduct semiconductor development themselves, TYLsemi will also provide an end-to-end service that includes design and implementation of a differentiating chiplet, packaging, qualification, and high-volume production, essentially enabling companies without any silicon development skills to offer their own multi-chiplet processors.

TYLsemi was co-founded by Mohit Gupta and Sunil Bhardwaj, semiconductor veterans who have led global engineering, operations, and business teams at Alphawave, SiFive, Cadence, Rambus, and other chip companies, and who collectively have plenty of experience with both standard and custom silicon. Mohit Gupta, a co-founder and chief executive of TYLsemi, believes that the time to establish a company that specializes in pre-approved chiplets and custom ASIC design is right now.

"Chiplets have been discussed for seven or eight years, but several things have changed in the last three or four years," Gupta told Tom's Hardware Premium. "First, advanced packaging has matured significantly. There are now multiple 2.5D and 3D integration options in volume production. Customers are not limited to one packaging technology or supplier; there are options from foundries and OSATs, including TSMC, Intel, ASE, and Amkor. Second, die-to-die standards have arrived. In the past, most chiplet implementations relied on proprietary interfaces. UCIe is now moving into production deployments, including at hyperscalers, which makes heterogeneous integration much more practical. Third, supply-chain resilience has become critical. Customers increasingly want modular and potentially multi-source strategies rather than a single point of failure. Those factors have created an environment that did not exist four or five years ago."

AI accelerators will be among the primary applications to benefit from multi-chiplet design, as we have already learned from AMD and Nvidia.

"The AI accelerator market is on track to reach $604 billion by 2033, and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment," Gupta said. "At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon."

Chiplet economics

The vast majority of AI and HPC accelerators today feature large die sizes, in many cases approaching the size of a reticle. However, as modern process technologies are becoming more complex, foundries tend to increase their quotes for new nodes. A leading-edge wafer used to cost around $15,000 to process around five years ago, but today that price is around $30,000. As a result, large chips at a size close to the reticle limit implemented on a leading-edge node become an option for a select few chip designers who can afford it. For newcomers, multi-chiplet designs enabled by advanced packaging and standardized interconnects such as UCIe start to make a lot more sense.

"Once dies get into the 500 – 600 mm² range, the yield curve becomes increasingly difficult. Timing closure on a reticle-sized die is also challenging," Gupta explained. "I have worked on a reticle-sized accelerator, and getting from 99% to the final 1% can require disproportionately more engineering effort."

TYLsemi estimates that its chiplet approach could reduce total cost of ownership by 57% at a volume of 100,000 devices, from $350 million for a monolithic 700 mm² 3nm-class chip to $150 million for a design combining a 500 mm² 3nm-class compute die with four 100 mm² I/O chiplets built on an N-1 process. TYLsemi believes that the unit price of a monolithic chip would be $3,000, whereas the cost of an SiP would be around $600. The company attributes the saving to higher yields, reusable I/O silicon, lower IP licensing and engineering costs, and substantially lower per-unit silicon costs. However, the company stresses that the figures are illustrative estimates rather than actual manufacturing costs. Additionally, multi-chiplet designs can enable faster product refreshes compared to large monolithic dies as they are faster to develop and yield.

"Compute may move to 2nm or A14, while high-speed I/O can remain on 3nm, since I/O does not scale in the same way as logic," Gupta said. "Our power-delivery chiplets can use an even less advanced process. Customers therefore do not have to use the most expensive silicon real estate for every function. […] There is no single answer for every design. You have to determine the right disaggregation points based on the architecture, thermal requirements, package, and how multiple accelerators communicate. […] The exact partitioning will vary by application, but you still get a better total cost of ownership."

TYLsemi primarily targets AI infrastructure, so it generally envisions multi-chiplet designs to be used for AI accelerators, data-center CPUs, high-performance computing, networking and telecom silicon, and heterogeneous SoCs. However, TYLsemi has also ignored the fact that multi-chiplet designs are already widely used for consumer CPUs and GPUs.

Foundation chiplets

At the core of TYLsemi's proposition are its foundation chiplets, which are reusable building blocks intended to handle common non-compute functions in custom AI and infrastructure processors and are implemented using various process technologies from TSMC. The foundation chiplets include the following:

• TYL.IO — a family of connectivity chiplets that includes TYL. IO PCIe, a 32-lane PCIe 7.0/CXL chiplet connected to the compute die via UCIe; TYL.IO Scale, a 224G+ SerDes for ESUN/UALink scale-up connectivity; and TYL.IO EIC for co-packaged optics.
• TYL.Power — a 16nm in-package IVR chiplet with embedded passives, designed to provide power closer to compute dies and use closed-loop control and die telemetry to improve power delivery.
• TYL.Mem — a planned family of memory-connectivity chiplets. TYLsemi has not yet disclosed the architecture or specifications, though it is safe to assume they are talking about memory controllers and PHYs.

Not all of these chiplets will be available immediately, as the company has certain priorities amid limited resources.

"The first TYL.IO product disaggregates the PCIe functionality that would normally sit on a large server processor, it is a 32-lane PCIe Gen7/CXL chiplet connected to the host compute die using UCIe," Gupta explained. "The idea is that the CPU cores can move to 2nm, A14, or another leading-edge process, while the I/O chiplet remains on 3nm. The next product in the family will address scale-up connectivity between XPUs within a rack using high-speed SerDes. That device will be considerably larger, with around 72 lanes and approximately 14 TB/s of bandwidth. We also have an EIC roadmap for co-packaged optical connectivity. We expect samples of our first I/O product in the second half of 2027."

These chiplets can be used as standalone components or integrated with a customer's compute dies designed by the customer to TYLsemi through TYL.Forge, TYLsemi's end-to-end custom silicon platform.

TYL.Forge

TYL.Forge is arguably one of the key enablers of TYLsemi's business, as the program is aimed at companies that have their own compute architecture or even a compute die, but cannot build their own SiP or manage the entire semiconductor supply chain.

"There are larger custom silicon companies in the market, but many of them focus on a relatively small number of customers that can generate billions of dollars in annual business," Gupta explained. "We see an opportunity among emerging AI companies and system companies that need advanced custom silicon but also need a partner capable of taking responsibility for the entire implementation and supply chain."

Such clients can provide their proprietary compute RTL, while TYLsemi handles physical implementation and integrates the resulting compute die with its pre-validated connectivity, power, and eventually memory chiplets. The company then manages tape-out, packaging, assembly, testing, qualification, and high-volume production.

"For example, a customer building a large accelerator can bring us its matrix-multiplication engine," Gupta said. "We can implement the custom compute die and integrate it with our chiplets, so the customer does not have to reinvent the I/O and other common functions. This reduces risk and time to market."

In fact, TYL.Forge appears flexible about where the customer enters the development process. TYLsemi describes the platform as covering everything from architecture and front-end design through implementation, tape-out, assembly, qualification, and production. So instead of RTL, customers can come to TYLsemi with an architecture/concept, and then the company will help develop and implement the silicon. Nonetheless, TYLsemi does not intend to invent the customer's core compute architecture itself. In addition, customers can bring in an existing compute die, which TYLsemi can combine with its chiplets, package, test, and bring to production.

"We are also talking with companies developing Arm- and RISC-V-based server processors," Gupta said. "They can develop the architecture, while we implement the rest of the silicon and bring the product to production. That gives customers an economic and engineering advantage because they do not need to build teams for every part of the chip."

The key advantage of TYL.Forge is the reuse of pre-validated components. Instead of developing common functions such as PCIe connectivity and power delivery for every new processor, customers can use TYLsemi's pre-validated foundation chiplets and focus engineering resources on differentiated compute architectures, software, and system design. In theory, TYLsemi could integrate third-party chiplets (not from a customer, but from a third-party chiplet provider). Still, the company's focus remains on offering its own pre-validated chiplets and custom silicon with SiPs it builds.

"Potentially, [we could integrate third-party UCIe chiplets into a TYLsemi-based system], UCIe has done a very good job defining the electrical interface, but the ecosystem is still maturing at the protocol level," Gupta explained. "In some cases, if we provide a chiplet to a customer, we may also need to provide or enable the UCIe IP on the other side of the connection. We are committed to UCIe and industry standards because standardization ultimately wins. […] We can consider customization for a large strategic customer or hyperscaler, but we do not want those projects to derail our standard product roadmap. […] Even when customers buy our standalone chiplets, I expect many of them will ask us to handle packaging and testing because heterogeneous integration and supply-chain management are difficult "

TYLsemi estimates that its approach can cut development time and cost by up to 50% compared with traditional custom silicon programs. In the best-case scenario, TYLsemi envisions that the development cycle can shrink considerably compared to today's cycles that can be two, three, or more years long. According to TYLsemi, once a customer provides sufficiently mature RTL or a netlist, the company can take a custom compute die to tape-out in around six to nine months or so, which includes fabrication, assembly, testing, and qualification.

"If a customer provides mature final RTL or a netlist and uses our standardized I/O chiplet, we believe we can take the custom compute die to tape-out in approximately six months in some cases," Gupta explained. "More generally, our target is six to nine months from a mature design to tape-out. The architecture and front-end phase is more customer-dependent. For a first-generation product, that can take around six months; for a more mature second- or third-generation design, it could be closer to three months, and some of that work can overlap with implementation. After tape-out, fabrication can take roughly four to five months depending on the process, followed by perhaps another two months for assembly, testing, and qualification. If the architecture is already mature, it may therefore be possible to reach production samples in about a year."

Still, the company stresses that architecture development and implementation typically include feedback loops, which greatly slow the development process. This is why the company provides the relatively conservative '50%' figure.

TYL.IO and TYL.Power samples will be available to qualified customers in 2027, in partnership with TSMC, and the company is looking forward to designing processors for its clients in time for them to reach the market in 2029 – 2030.

Speaking of TSMC, TYLsemi will initially only offer designs and services adhered to the TSMC ecosystem, though eventually it may offer other options for packaging technologies, such as Intel's EMIB and Foveros, or Amkor's packaging methods.

"We are initially focused on the TSMC ecosystem, but we also intend to explore other advanced-packaging supply chains," Gupta said. "We do not want to limit ourselves to one packaging option. Over time, that could include other OSATs and packaging technologies. […] That could include Intel, ASE, Amkor, or others. Amkor, for example, is building significant packaging capacity in Arizona."

Intel will design, package, and fabricate Fortinet's sixth-generation Security Processor (SP6) on its Intel 4 node, the companies announced on July 21, giving the process its first named external foundry customer, roughly three years after it entered production. Intel told Tom's Hardware the agreement reflects "the strategy Intel outlined for Intel 4 several years ago," including support for custom networking ASIC workloads. Intel's own record from those years reads differently, however, with the company's 2021 roadmap having scoped Intel 4 to two internal products. And through 2022, it told engineers and investors that Intel 3, not Intel 4, would be its first process offered to foundry customers.

Intel 4's record

Intel's Accelerated announcement back in July 2021 said that Intel 4 would reach production readiness in the second half of 2022 for products shipping in 2023, naming "Meteor Lake for client and Granite Rapids for the data center." The release and its accompanying fact sheet, however, contained no reference to foundry customers, networking, or custom ASICs on the node.

At VLSI 2022, Intel disclosed that it wasn't building a high-density library for Intel 4 and that Intel 3 would be the first new node offered through what was then Intel Foundry Services. A 2024 post on Intel's own foundry blog describes Intel 3 as "Intel Foundry's first leading-edge process node," and Intel's fiscal year 2024 annual report listed the processes available to external customers as 18A, Intel 3, Intel 7, Intel 16, and a 12nm node co-developed with UMC. Intel 4 appears nowhere on that list.

Ericsson's RAN Compute processors, announced in November 2023, were built on Intel 4, so Fortinet's part won't be the first third-party silicon to come off the node. That work grew out of a bespoke Intel-Ericsson collaboration, though, and Ericsson's formal foundry agreement with Intel, announced in July 2023, covered 18A. Fortinet is the first named customer buying Intel 4 as a foundry service, and the first cybersecurity vendor on any Intel node. The Ericsson engagement is also the closest thing in the public record to networking silicon on Intel 4, two years after the strategy Intel now says it outlined for the node.

Fab 34 economics

Intel 4 entered high-volume manufacturing at Fab 34 in Leixlip, Ireland, in September 2023, producing the compute tile for Meteor Lake-based Core Ultra chips, and shares the fab with Intel 3. Intel sold a 49% stake in the facility to Apollo-managed funds for $11.2 billion in June 2024, then bought it back in April 2026 for $14.2 billion, funded with $7.7 billion in cash and $6.5 billion in new debt. That buyback returned 100% of Fab 34's wafer economics to Intel at a premium of roughly 27%, and it only pays off if the fab's EUV capacity stays loaded.

Meteor Lake is aging out of Intel's lineup as 18A-based Panther Lake ramps through 2026, which leaves open the question of what fills Intel 4 capacity next. A multi-generation firewall ASIC program is a reasonable answer with mature yields, a customer that values supply stability over bleeding-edge density, and a part Intel described as tailored for cost-sensitive applications. Intel said in April that yields were improving across Intel 4, Intel 3, and 18A.

Fortinet's supply chain

Fortinet's 2025 annual report names Renesas and Toshiba America as the contract manufacturers for its ASICs, utilizing foundries in Taiwan and Japan operated either by TSMC or by the contract manufacturers themselves. The current SP5, a monolithic 7nm Arm-based SoC announced in February 2023, sits in that supply chain, so SP6 on Intel 4 moves Fortinet's next flagship security processor out of a TSMC-linked flow and into Intel's. The disaggregated design language in the announcement points to a chiplet-based part, a first for Fortinet's SP line.

Fortinet re-engineered three FortiGate models in 2022, the 70F, 600F, and 3700F, to accept alternative components during the chip shortage, and CMO John Maddison told SDxCentral at the time that the company wouldn't wait for parts to arrive in 2023. The "resilient and diversified" supply chain used in the SP6 press tracks back to that experience. Ken Xie called Fortinet "the #1 firewall leader with a 55% unit market share" in the company's 2025 results in February, with approximately six million FortiGates deployed, so there’s real, substantial volume here even if the parts are relatively inexpensive.

Intel Foundry reported $307 million in external revenue for 2025, up from $159 million the year before, against total foundry revenue of $17.8 billion and an operating loss of $10.3 billion. External revenue in Q1 2026 was $174 million. Fortinet's hardware business runs at roughly 30% of its revenue, and, per analysis from ServeTheHome, SP6 is ultimately a component of a portion of an annual hardware stream around $2 billion, so the deal won't move Intel's foundry line materially, even at full production.

CEO Lip-Bu Tan told CNBC in May that he expected commitments from multiple foundry customers in the second half of 2026, and Intel told investors in January that two prospective customers were evaluating 14A test chips. The SP6 announcement comes inside Tan's stated window, and it finally gives Intel something its foundry marketing has lacked in a named customer with shipping volume on a node with mature yields. Meanwhile, an 18A or 14A commitment from a major external customer is still missing, and Fortinet's cost-sensitive parts on a 2023 node don't substitute for one.

Intel and Fortinet have announced a strategic collaboration to develop the Fortinet Security Processor 6 (SP6), the next generation of the custom silicon behind Fortinet's FortiGate firewalls. Intel will contribute chip design, advanced packaging, and manufacturing to the SP6 program, making Fortinet the first cybersecurity vendor named as an Intel silicon customer.

Intel told Tom's Hardware that SP6 will be built on Intel 4, the EUV process the company has so far used only for its own products, making Fortinet both the first cybersecurity vendor named as an Intel silicon customer and the first named external customer for the node. However, the announcement specifies no production timeline, and it comes in the same Q3-Q4 2026 window in which CEO Lip-Bu Tan said the company expects commitments from multiple foundry customers.

SP6 will draw on what the companies described as Intel's expertise in disaggregated semiconductor design and advanced packaging tailored for both AI-enabled and cost-sensitive applications.

That points to a chiplet-based part, which would be a departure from the current SP5, a monolithic 7nm Arm-based SoC that Fortinet launched in 2023 for its entry-level and mid-range FortiGate appliances. The deal will help Fortinet "accelerate and strengthen our ASIC strategy," said Ken Xie, founder, chairman, and CEO of Fortinet, in the announcement.

Intel 4 was the company's first process node to use EUV lithography and entered high-volume manufacturing at Fab 34 in Ireland in September 2023, where it produces the compute tile for Meteor Lake-based Core Ultra chips. The node didn't appear among the processes Intel listed for external foundry customers in its fiscal year 2024 annual report, which named 18A, Intel 3, Intel 7, Intel 16, and a 12nm process co-developed with UMC. Intel said the SP6 work reflects plans it laid out for Intel 4 several years ago, including support for custom networking ASIC workloads.

Microsoft agreed in early 2024 to build an unnamed custom chip on Intel's 1.8nm-class 18A node, a deal that reportedly covers a next-generation Maia AI processor. That announcement followed a similar pattern, with no product details, node variant, or timeline at signing and specifics emerging over the following 18 months.

Intel CFO David Zinsner said in March that the company was fielding inbound interest in 18A-P from prospective foundry customers as yields improved, and Tan told CNBC in May that foundry commitments were expected in the second half of 2026.

Fortinet does bring real volume, though, if not marquee volume. IDC ranked Fortinet first in firewall appliances shipped as of early 2023, with a 48% unit share. The company ships its own ASICs across its entry-level and high-end FortiGate ranges, and SP6 extends a silicon program now in its sixth generation.

Neither company committed to work beyond SP6, though the release described the agreement as a starting point, with further collaboration on chip technology and manufacturing under discussion.

TSMC intends to raise base quotes on advanced chip production services by up to 10%, according to Nikkei, which cites people with knowledge of the matter. The price hike reflects increased demand for sophisticated processors by the AI sector, raising costs of tools and materials, as well as amplified investments in new production capacities.

For advanced process technologies — which TSMC considers 7nm-class and below — TSMC plans to raise baseline prices by 5% to 10%, depending on the particular production node and customer, the report claims. Furthermore, customers that need additional HPC chip capacity beyond their original volume requirements will reportedly have to pay another 10% to 15% premium on top of the standard increase, which means that some services will get a price hike of around 25%, if the report is accurate.

TSMC also intends to increase prices for mature manufacturing technologies, including its 12nm, 16nm, and 28nm-class nodes as well as other legacy fabrication technologies, the report claims. Increases could reach 10%, although certain nodes will reportedly see smaller adjustments, according to Nikkei.

Advanced technologies generated around 77% of the foundry's revenue in Q2 2026, whereas mature nodes accounted for 23%, which essentially means that TSMC is hiking prices on all of its services.

The company reportedly began discussing the new pricing with customers around June and completed negotiations in July. Rather than introducing higher rates immediately, TSMC opted to implement them from the beginning of 2027 to give clients like Apple, AMD, Nvidia, and MediaTek additional time to accommodate the changes and adjust their prices accordingly.

Since TSMC produces the lion's share of advanced processors for AI, HPC, networking, and smartphone applications, its price hikes will inevitably create a ripple effect in the industry and will make almost all electronics more expensive.

TSMC is not alone in raising prices these days. Vanguard International Semiconductor has also raised prices, while UMC began implementing increases in July. Also, memory makers have increased prices significantly, making TSMC management jealous. Intel also recently increased prices of its client and data center CPUs, citing market demand.

"I am really jealous about memory companies' 86% gross margin," said C.C. Wei, chief executive of TSMC, during the company's earnings call with financial analysts and investors. "86% [margin at memory makers] – 68% [margin at TSMC], I will be happy about that."

TSMC rarely comments on its prices to a large degree because they vary based on volumes and relationship with a particular client. Nonetheless, the head of the company stressed that the company has no intentions to increase prices suddenly or dramatically.

"So we do not suddenly increase our price by which I like to have 4x or 5x," Wei said. "You cannot survive for that kind of... for your customer to survive for that kind of price increase. So we earn our value, and we make sure that our profit, our gross margin, is enough for our long-term sustaining expansion, that is to the benefit of my customers and TSMC also, that is our philosophy."

An analysis of Huawei's Kirin 9030 system-on-chip (SoC) for smartphones conducted by SemiAnalysis revealed that SMIC's third-generation 7nm-class fabrication technology (N+3) has smaller metal pitch than Intel's 18A fabrication technology and that China's leading foundry has managed to achieve transistor density on par with manufacturing process that rely on EUV lithography. But does this make SMIC's N+3 node as competitive as Intel's 18A or TSMC's N2 and N3? Not really.

SemiAnalysis' teardown indicates that SMIC's N+3 fabrication process supports a minimum metal pitch of 32.5nm, which is nominally tighter than the approximately 36nm pitch used for many high-performance cells in Intel's Panther Lake CPU, even though 18A can support approximately 32nm metal pitches. The video from SemiAnalysis and High Yield does not reveal other important characteristics of SMIC's N+3, such as contacted gate pitch (CGP), standard cell height (tracks or nm), or fin pitch, so we cannot make direct comparison of this node to Intel's or TSMC's technologies. What it does reveal is estimated transistor density of around 113.4 million transistors per square millimeter (Mtr/mm²), which is even higher than transistor density of TSMC's N6, 107.7 Mtr/mm².

TSMC's N6 uses multiple EUV layers, so achieving higher transistor density without using EUV lithography is an indisputable technological achievement of SMIC. The foundry achieves this density by using DUV multi-patterning, including self-aligned quadruple patterning on the tightest layers, and extensive design-technology co-optimization (DTCO). In addition, SemiAnalysis believes that SMIC used techniques like reduced fin counts, placing contacts directly over active gates, and tightening cell isolation. Such methods allow for increased transistor density, but at the cost of increased process complexity, cost, yield risks, and design constraints.

Meanwhile, transistor density does not equal overall process competitiveness. Despite its compact layout, the Kirin 9030 reportedly delivers performance comparable to flagship application processors from roughly three years ago and has a substantial energy-efficiency disadvantage compared with modern Apple, Qualcomm, MediaTek, and Samsung designs. Huawei's highest performing CPU core is characterized as roughly Cortex-X2-class in IPC, while Apple's much smaller efficiency cores reportedly outperform it in integer workloads and consume considerably less power.

Given the fact that Kirin 9030 is neither a performance nor efficiency champion, the provocative comparison with Intel 18A is not exactly justified. Although SMIC N+3 has 32.5nm minimum metal pitch that is nominally tighter than the approximately 36nm pitch used in Panther Lake, 18A offers both higher transistor density and considerably higher performance efficiency. In addition, 18A uses gate-all-around transistors and backside power delivery, which make it particularly suitable both for mobile SoCs and for data center applications.

SemiAnalysis concluded that while export restrictions have slowed China's technological progress, progress is still being made. SMIC could potentially continue increasing density by tightening upper and lower metal layers, shorter standard cells, smaller gate pitches, and eventually backside power delivery. If the company continues scaling, N+4 could approach TSMC N5-class density, while N+5 with backside power might reach Intel 18A-class density, according to SemiAnalysis. Still, transistor density alone does not necessarily bring substantial improvements of performance or power efficiency.

ASML is reportedly considering increasing prices of its existing Low-NA EUV lithography tools. The potential price hikes have already upset TSMC, ASML's largest client, reports The Information. But can ASML rapidly raise the prices of the tools it sells to chipmakers? Price adjustments are not going to happen overnight, said Roger Dassen, CFO of ASML, said during the company's quarterly earnings call. But there is one thing to remember about ASML's price hikes: They are going to affect the entire semiconductor industry.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. […] Given the long order lead times that we have, that does not translate into pricing effects tomorrow."

ASML just reported record results for its second quarter of 2026, with total net sales of €9.326 billion ($10.67 billion) and net income of €2.918 billion ($3.338 billion). The company now expects net sales between €43 billion ($49.2 billion) and €45 billion ($51.5 billion) in 2026, a range that comfortably exceeds its own guidance and the expectations of industry analysts.

More complex, more expensive

ASML has generally increased the average selling price of EUV scanners over successive generations as they increase in complexity and productivity, so the idea of higher pricing of EUV tools is not particularly new. The company calls the concept of 'value-based pricing' and gradually increases its average selling price (ASP) based on the value that its tools provide to its operators.

Early ASML Twinscan NXE systems were commonly discussed in the roughly €100 million–€120 million ($115 million-$137 million) range, while later production models such as the NXE:3400C and NXE:3600D moved toward roughly €140 million–€170 million ($160 million-$195 million). The latest NXE:3800E is climbing even further. High-NA EXE systems represent another major step up, at more than €350 million ($400 million) per machine according to industry reports.

Meanwhile, both productivity and performance of ASML's Twinscan NXE systems have been steadily increasing: While the NXE:3400C and NXE:3600D can process 160 – 170 wafers per hour (WPH) and feature a matched machine overlay (MMO) of ≤ 1.1nm, the NXE:3800E and NXE:3800F increase productivity to 220 WPH and 260 WPH, respectively, while increasing MMO to 0.9nm. With the NXE:4200G and NXE:4200H (which will likely feature an all-new light source), we are looking at productivity beyond 300 WPH and MMO of ≤0.8nm - ≤0.7nm.

ASML makes no secret that more advanced EUV lithography tools carry a higher average selling price than their predecessors.

"You should also recognize that the tool mix that we are going to ship next year is a different tool mix from the tool mix that we shipped this year," Dassen said. "When it comes to EUV in particular, the tool mix that we are going to ship next year will be EXE: 3800E and EXE:3800F [tools], while this year it is a combination of EXE:3600D and EXE:3800E [systems]."

ASML's value-based pricing logic is essentially: if an upgraded Low-NA machine processes more wafers and therefore generates more economic value for a fab, ASML can capture part of that additional value through a higher system price. This is what ASML has been doing for some time. That said, the important nuance in Dassen's statement is that he appears to be discussing further price increases for Low-NA EUV tools.

ASML's EUV dominance

ASML is the only supplier of EUV lithography systems on the planet; every single chipmaker must comeq to the company to get one of these scanners, so the company sells these machines years in advance. This year, the company expects to have the capacity to build 65 EUV tools and intends to increase capacity by 30% next year to around 84 – 85 EUV systems. In 2028, ASML plans to produce 110 EUV scanners.

"For 2027, we are now close to being fully covered with orders for Low-NA EUV, and we are planning to increase our Low-NA EUV capacity by around 30%," Dassen said. "Looking ahead to 2028, we have already received a significant number of Low-NA EUV orders. Strong demand forecasts from our customers have led us to investigate a further 30% capacity increase for that year."

Given the strong demand for ASML's tools, the company is in a position to increase prices, at least according to the rules of the free market. As always, comments on pricing are made in opaque corporate language, so one can make a lot out of it, or nothing at all.

"Clearly, the environment that we live in today, with the [substantial] value that our products bring to customer, of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, it is not that easy for ASML to just hike prices overnight, and there are important things to note. When ASML gets an order, and that order enters the reported backlog (which totaled €38.8 billion as of late Q4 2025), it already carries a sales value (with a possibility of inflation adjustments), so there is necessarily an agreed or otherwise contractually determined price basis attached to it.

This makes Dassen's comments particularly interesting. If ASML is already close to fully booked for 2027 Low-NA EUV capacity and has received a significant number of Low-NA orders for 2028, then much of that capacity is already represented by customer orders with associated sales values. As a result, unless ASML can subsequently renegotiate the fixed price before delivery, it cannot hike prices on tools that it intends to ship in 2027 and part of 2028. This essentially means that ASML could only book new orders that it intends to ship in 2028 (presumably for the second half of the year) and onwards at higher prices. However, ASML has not confirmed this directly.

ASML's next-generation NXE:4200G is on track to arrive in 2029. That scanner is poised to be more expensive than the NXE:3800E/NXE:3800F anyway, so the company's Low-NA EUV ASPs will inevitably get a bump that year. Of course, ASML is set to continue shipping its EXE:3800-series after 2029. The big question is whether the company will adjust the prices of these units that will ship starting in 2028 or not.

We do not know the answer to this question, unfortunately. But during the conference call, ASML's financial chief implied that the company would like to get 'rewards' from its customers not only for improved productivity, but also for other improvements of its tools, which means that ASML will stick to its value-based pricing model, but may adjust the pricing for the EXE:3800 model.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. [But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out, which, put in another way, customers were paying for the productivity upgrade, and the value that we gave them for free was the value associated with, let us say, overlay improvement, imaging quality […]. In the current environment, with the value that we bring, we are also having conversations with customers on how we get rewarded for that additional value."

TSMC's backlash against the price hikes

As ASML will likely not be able to hike prices on EUV tools that have already been pre-ordered and which are set to be delivered in the course of the next two years, existing chipmakers like TSMC will not feel the effects of the price increase at least over the next 24 months. Of course, if ASML adjusts prices of its EXE:3800-series scanners due to ship in 2028 – 2028, nobody is going to be happy. And yet, TSMC seems to be so upset that the sentiment has made it to the press. There are several reasons behind the reported backlash, but the major one seems to be strategic.

For years, TSMC has said that ASML's High-NA EUV lithography tools were too expensive, and that the company's engineers can continue innovating using Low-NA EUV systems. Also, adopting all-new High-NA EUV scanners will not be an easy undertaking in general, as the transition also requires new photoresists, photomasks, pellicles, metrology equipment, design rules, computational lithography flows, and numerous other supporting technologies and process innovations.

TSMC's mid-term expansion strategy, as well as a leading-edge roadmap through 2030, has been built around extracting more performance and resolution from conventional Low-NA EUV scanners using techniques such as improved masks, computational lithography, and multi-patterning where necessary. If ASML proceeds with its price hikes for Low-NA EUV tools, this can seriously hit one of the key economic foundations of TSMC's strategy.

TSMC's intention to avoid the usage of High-NA EUV scanners until at least 10A-class (1nm) process technology has an important economic advantage. A High-NA EUV system costs more than €350 million, whereas Low-NA systems are substantially cheaper. As a result, TSMC can choose its own trade-off between additional process steps and buying much more expensive lithography equipment. In contrast, Intel, which is set to adopt High-NA EUV lithography for its 14A fabrication process, has much less flexibility: If a particular process technology is designed around High-NA EUV layers, these extremely expensive scanners, along with other ingredients, become part of the manufacturing flow and affect wafer pricing.

One of the reasons TSMC would like to extend usage of Low-NA EUV systems is that it already has the world's largest install base of these tools, as well as mature processes, established flows, and plenty of innovations that enable it to stay ahead of the competition. However, if ASML systematically ties productivity improvements of each new Low-NA EUV generation to higher prices, the cost advantage of staying with Low-NA EUV gradually narrows, which greatly undermines TSMC's strategy.

There are several other reasons for TSMC to be particularly unhappy with ASML. Firstly, TSMC needs an enormous number of tools for its upcoming fabs in Taiwan, the U.S., and Japan. All of the company's leading-edge process technologies through 2029 rely on Low-NA EUV production tools. Even a relatively modest percentage increase applied to dozens of Low-NA EUV scanners can add billions of dollars to the company's capital expenditure (CapEx).

Secondly, ASML is essentially arguing that it deserves a share of its customers' improved economics. From TSMC's perspective, potential price adjustments are very different from charging more because a new scanner is materially more expensive to manufacture. ASML is effectively saying: 'Your fabs are more profitable, and our tools are more productive, therefore we want a piece of that.'

Thirdly, pricing negotiated today determines pricing and TSMC's economy for years to come. Now that ASML is sold out for 2027 and a significant part of 2028, it is negotiating terms for the second half of 2028 and onwards. Accepting a substantial increase now will inevitably carry through to dozens or hundreds of future Low-NA EUV systems, which directly affects TSMC's economics.

TSMC's A14 (1.4nm-class) fabrication process has made rapid progress in the last three months and is well ahead of N2 at the same stage of development, according to the company's update provided at its earnings call this week. The technology also faces strong customer interest and engagement across both smartphone and AI/HPC applications.

"A14 technology development is on track and progressing well. Internal product-like vehicle demonstrated close to 90% device performance and close to 90% 256Mb SRAM yield," said C.C. Wei, chief executive of TSMC, during the earnings call with analysts and investors.

A14 — which is expected to enter mass production in 2H 2028 — is making rapid progress in terms of performance and yield improvements. This April, the company disclosed that the production node achieved >85% target transistor performance and >80% 256Mb SRAM yield. Roughly three months later, both figures are approaching 90%, which suggests a gain of around 5% in device performance and nearly 10% in SRAM yield.

For comparison, TSMC's N2 demonstrated more than 80% of its target device performance and over 50% yield on a 256Mb SRAM test chip in April 2023. By April 2024, the process had advanced to more than 90% of its target device performance and over 80% SRAM yield. While development trajectories are not directly comparable, the figures suggest that A14 is maturing considerably faster than N2 did at a similar stage of development.

The very rapid progress of A14 compared to the relatively slow maturation of N2 at similar stages of development can probably be attributed, at least in part, to TSMC's growing experience with gate-all-around (GAA) nanosheet transistors. Back in 2023, the company barely had enough experience with the production of gate-all-around (GAA) nanosheet transistors, as N2 is its first process technology to adopt such a structure. By contrast, A14 relies on TSMC's 2nd Generation of GAA devices, so it can probably benefit from the transistor-design improvements, process refinements, and manufacturing expertise accumulated during the development and ramp of N2.

It appears TSMC has likely eliminated many of the yield limiters with A14 and N2, though keep in mind that a high 256Mb SRAM yield merely indicates low enough defect density and good process uniformity across a highly repetitive test structure, but it is not directly representative of functional or parametric yield of a commercial processor.

Nonetheless, the close to 90% device performance and close to 90% 256Mb SRAM yield about 2.5 years away from expected mass production start put TSMC's A14 progress well ahead of N2. Such progress can potentially enable TSMC to start high-volume manufacturing (HVM) using A14 ahead of schedule, provided that customer designs are ready, or initiate HVM with better-than-usual functional and parametric yields.

Speaking of customer design readiness, Wei indicated that clients strive to tape-out their A14 designs ahead of schedule, which is a good sign. It is also interesting to note that despite the fact that A14 lacks Super Power Rail backside power delivery (A12 will gain SPR in 2H 2019), it is set to be adopted not only by client processors, but also by AI/HPC applications.

"We are observing a strong level of customer interest and engagement on both smartphone and HPC/AI applications, and customer new tap-out activity is ongoing and ahead of schedule," Wei said.

A14 is TSMC's next-generation process technology that combines the company's 2nd Generation GAA nanosheet transistors with a new standard-cell architecture to improve performance, power efficiency, and transistor density. Compared with N2, TSMC expects A14 to deliver a 10% – 15% performance uplift at the same power and transistor count, or reduce power consumption by 25%–30% at the same frequency and complexity. The node is also projected to increase transistor density by around 20% for mixed designs and by 23% for logic.

As the semiconductor industry increasingly relies on ASML's EUV lithography tools both for logic and memory production, ASML is considering increasing prices of these systems as they deliver greater productivity and better value for its customers. However, with 2027 production nearly sold out and substantial 2028 orders already booked, meaningful increases may primarily affect systems delivered from late 2028 onward. Nonetheless, the idea has already angered TSMC, ASML's largest client, reports The Information.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. "Given the long order lead times that we have, that... doesn't translate into pricing effects tomorrow."

Value-based pricing set to persist… in a new way

ASML has long followed what it calls value-based pricing and gradually increased its quotes based on output, patterning costs, power consumption, and other benefits its new tools offer to clients.

Usually, this involved increasing prices once in a while. For example, if early Twinscan NXE Low-NA EUV systems cost roughly €100 million – €120 million ($115 million–$137 million), the more advanced are priced starting at €170 million ($195 million. It is still well below rumored quotes for High-NA EXE scanners that exceed €350 million ($400 million). At the same time, Low-NA productivity has risen from 160–170 wafers per hour (WPH) and ≤1.1nm matched-machine overlay to 220 WPH/260 WPH with NXE:3800E/NXE:3800F at 0.9nm. Future NXE:4200G/NXE:4200H systems are expected to exceed 300 WPH and improve overlay to ≤0.8nm–≤0.7nm.

"Clearly, the environment that we live in today, with the value that our products bring to customer — it's substantial— of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, later during the call, Dassen emphasized that ASML intends to maintain its value-based approach even in the current environment of high demand and limited supply in the semiconductor world. Yet, he stressed that from now on, ASML might want to charge for things beyond just productivity.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. "[But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out," he said, suggesting that ASML shares value with its clients.

No price hikes in the short term

ASML will be unable to hike prices of Low-NA EUV systems for another couple of years. Since orders that are in ASML's backlog already carry a sales value, subject to inflation adjustments, prices for much of the 2027 and early 2028 output may already be contractually determined. Unless existing contracts can be renegotiated, higher pricing could therefore primarily apply to 2028 shipments and beyond, or for new orders that somehow get squeezed in in 2027. The NXE:4200G, due in 2029, should naturally lift average selling prices anyway as it gets major performance improvements.

TSMC is upset

For TSMC, however, the issue is strategic. The foundry's leading-edge roadmap through 2030 relies on extending Low-NA EUV with better masks, computational lithography, and multipatterning. Until then, TSMC's strategy has always been avoiding High-NA EUV until at least its 10A-class (1 nm-class) technology. If ASML hikes prices of its future Low-NA EUV lithography systems, it will likely affect all of TSMC's plans for the next several years.

TSMC already operates the world's largest Low-NA EUV fleet and needs many more scanners for fabs in Taiwan, the U.S., and Japan as it executes its global expansion strategy. Consequently, even modest increases beyond TSMC's projections could add billions to capital spending, reduce the economic advantage of postponing High-NA, and ultimately raise its manufacturing costs. Moreover, accepting higher prices now could establish the baseline for dozens or hundreds of future systems, which will allow ASML to capture a larger share of the economic value created by increasingly productive lithography equipment.

Can this force TSMC to transition to High-NA EUV tools earlier than planned? Moving to High-NA EUV requires not only €350-million-plus scanners but also new resists, masks, pellicles, metrology, design rules, and computational lithography flows, which are likely not ready at TSMC.

Tower Semiconductor has announced a dual-track expansion of its 300mm silicon photonics, silicon germanium, and advanced packaging operations in Japan, committing up to $3 billion net of grants with backing from the country's Ministry of Economy, Trade and Industry (METI). Alongside the announcement, the Israeli specialty foundry raised its 2028 business model to approximately $3.6 billion in revenue and $1.2 billion in net profit, and it says those targets rest entirely on the first of the plan's two tracks: reviving the shuttered Arai fab it inherited from Panasonic and maximizing its running 300mm fab in Uozu, Toyama Prefecture.

Two tracks, one committed

Track One converts the former Arai facility, designated Fab 6, into a 300mm silicon photonics and advanced optical packaging plant while expanding output at Fab 7 in Uozu, with full production readiness expected during the fourth quarter of 2027. The Arai plant ceased operations in July 2022 because it exclusively served Nuvoton Technology Corporation Japan (NTCJ) rather than Tower's foundry customers, according to Tower's SEC filings, leaving an intact fab shell sitting idle for four years.

Track Two calls for constructing a new 300mm fab adjacent to Fab 7, which Tower says would deliver a multi-fold increase in silicon photonics and silicon germanium capacity and become "highly accretive beginning in 2029." The company hasn't signed definitive agreements for it, however, and none of the new 2028 targets depend on it.

A restructuring of the TPSCo joint venture, announced in March 2026, cleared the way for all this. Tower entered Japan in 2014 by buying 51% of Panasonic's three-fab semiconductor manufacturing operation, and Panasonic sold its remaining stake to Nuvoton in 2020. Under the March agreement, Tower takes full ownership of the 300mm Fab 7, while NTCJ absorbs the 200mm operations and pays Tower $25 million, with closing expected on April 1, 2027. Sole ownership of Fab 7 removed the joint-venture structure that would have complicated a $3 billion buildout.

Tower CEO Russell Ellwanger contrasted the approach with greenfield construction and fab acquisitions, which he said typically require years of process development, customer qualification, and financial stabilization while ramping from zero revenue against high fixed costs. Reusing a dormant building next to a qualified, cash-generating photonics fab is why Tower can achieve production readiness roughly 18 months ahead; Rapidus, by comparison, broke ground on its greenfield Chitose site in September 2023 and doesn't expect mass production until 2027.

29% increase in revenue

Tower reported $1.566 billion in revenue and $220 million in net profit for 2025, up from $1.436 billion and $208 million in 2024. The new 2028 model more than doubles 2025 revenue and implies a net margin of around 33%, against roughly 14% today. Measured against the prior 2028 model of $2.8 billion in revenue and $750 million in net profit, which Tower reaffirmed in its Q1 2026 report in May, the new targets add 29% to revenue and 60% to net profit.

Silicon photonics revenue is doing most of the heavy lifting, with Ellwanger telling analysts on the company's Q4 2025 earnings call in February that silicon photonics revenue reached $228 million in 2025, up from $106 million in 2024, and hit a $380 million annualized run rate in the fourth quarter, a figure he noted includes some non-wafer engineering revenue. In May, Tower disclosed $1.3 billion in contracted silicon photonics revenue for 2027 from its largest customers, backed by $290 million in prepayments already collected.

Tower's photonics customer roster includes Innolight, which builds 400G, 800G, and 1.6T optical transceivers on Tower's PH18 platform family, and Marvell, which said in June it had shipped more than five million coherent photonic ICs manufactured with Tower. The company claims more than 50 active silicon photonics customers and supplies foundry capacity for 200 Gb/s-per-lane devices used in 1.6T transceivers.

Tower's forward-looking disclosures flag construction delays, equipment lead times, permitting, and METI grant covenants that "may result in loss of a portion or all of the grant funds." The implied margin expansion also assumes sustained AI and data center optics demand from a concentrated group of very large customers through 2028, a dependency Tower acknowledges.

Tower’s position in the photonics foundry race

GlobalFoundries paid $453 million in cash for Singapore's Advanced Micro Foundry in November 2025, according to its annual report, a deal the company said made it one of the largest silicon photonics manufacturers. TSMC's COUPE co-packaged optics platform is tracking Nvidia's optical interconnect roadmap, with 1.6 Tb/s optical engines arriving in 2026 products.

Tower occupies a different lane from TSMC, as a merchant foundry serving dozens of transceiver makers and chip designers, rather than a packaging platform aligned with one customer's rack-scale plans. GlobalFoundries competes with Tower far more directly, and the two are also in court, with GlobalFoundries pursuing patent infringement claims against Tower.

MarketsandMarkets estimates the silicon photonics market at $2.65 billion in 2025, growing to $9.65 billion by 2030 at a 29.5% compound annual growth rate. Demand for optical data movement in AI clusters underpins those forecasts, as interconnects shift from copper to light at 800G and 1.6T speeds.

METI's support for Tower joins a Japanese subsidy program that has committed up to ¥1.2 trillion to TSMC's JASM fabs in Kumamoto, roughly ¥536 billion to Micron's Hiroshima operations, and around ¥2.9 trillion in planned funding for Rapidus. Tower's award appears to be the program's first at this scale for a dedicated silicon photonics foundry.

Intel agreed to buy Tower for $5.4 billion in 2022, but abandoned the deal in August 2023 after Chinese regulators declined to approve it, paying Tower a $353 million termination fee. The Japan program is the largest capital commitment in Tower's history, well beyond the up-to-$300 million arrangement it struck with Intel in September 2023 for 300mm capacity in New Mexico. Three years after nearly becoming an Intel subsidiary, Tower is building its own flagship instead.

Intel has entered high-volume manufacturing using ASML's High NA extreme ultraviolet (EUV) lithography technology for a subset of its Intel Core Ultra Series 3 "Panther Lake" processors, becoming the first company to ship high-volume logic products manufactured with the technology. ASML announced the milestone in an official press release on Wednesday, July 15, confirming that Intel Foundry is running the qualified High NA layers on its Intel 18A process node in Oregon.

According to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.

High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product.

Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography.

High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.

This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies.

"With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.

While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.

Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.

Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.

The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.

Google plans to use Intel's EMIB-T packaging for its next-generation TPU codenamed Humufish, according to SemiAnalysis. TSMC's portfolio of chip-on-wafer-on-substrate (CoWoS) technologies has become the de facto standard advanced packaging option for nearly all AI and HPC processors made in the industry. Competing offerings are usually considered as secondary solutions if CoWoS is in tight supply, but things are beginning to change.

Google is a long-standing CoWoS customer for TPUs, starting from the Third-Generation TPU, all the way to Google's latest Eighth-Generation TPUs. Assuming that SemiAnalysis's report about Google's decision to move to EMIB-T with its Ninth-Generation TPUs is accurate, it's a big decision for Google, as switching from one advanced packaging technology to another is a complicated endeavor, which involves plenty of changes and unknowns. Understanding Google's reasons for the switch could shed some light on the prospects of Intel's and TSMC's advanced packaging technologies, which will be used by leading chip designers and hyperscalers in the coming years.

Advanced packaging technologies at glance

For years, Google used TSMC's CoWoS-S, and later, CoWoS-L packaging. Initially, the company used CoWoS-S packaging, which relies on a silicon interposer up to 3.3X the reticle size, but with its 7th- and 8th-Generation TPUs, the company moved to CoWoS-L. CoWoS-L relies on a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges that enable high-performance die-to-die links, which can scale packages to 5.5X the reticle size today. TSMC promises to improve CoWoS-L's capabilities to scale over 14X the reticle size by the end of the decade.

Unlike CoWoS, Intel's embedded multi-die interconnect bridge (EMIB) technology does not use any interposers. The technology instead relies on tiny embedded silicon bridges within the substrate to enable high-density die-to-die interconnections, whereas everything else is routed through an inexpensive organic substrate.

EMIB-T adds through-silicon vias (TSVs) to the bridge, which enables power to flow vertically instead of going through the organic substrate. In addition, Intel's EMIB-T also integrates sophisticated metal-insulator-metal (MIM) capacitors and a dedicated ground plane into the bridge to improve power integrity. The latter is a particularly important feature of complex next-generation AI accelerators, which demand more, cleaner power, and for which power delivery is becoming as challenging as signal routing.

The main selling point of EMIB (and EMIB-T) is that it is not constrained by interposer reticle limits as it places small silicon bridges only where high-density die-to-die links are needed. Strictly speaking, CoWoS-L is not either, as it uses LSIs locally as well. The difference is that those bridges are embedded into a package-wide RDL interposer that connects everything and enables dense interconnections across the package.

Since both CoWoS-L and EMIB-T are designed to address the same applications and have many similarities in the way they do this, the choice between them is likely driven by a combination of factors rather than one single advantage or disadvantage. On the technology side of matters, these factors include interconnect performance and density, power delivery, scaling beyond very large package sizes, and mechanical rigidity. On the business side of things, costs, capacity availability, and supply chain diversification are also a significant factor.

Crucial differences

SemiAnalysis claims that the main advantage of EMIB/EMIB-T over CoWoS is the lack of reticle limit, but this argument does not fully hold against CoWoS-L, as it was invented specifically to escape the reticle limitation by replacing the monolithic silicon interposer with localized LSI bridges.

When it comes to dense, package-wide routing, CoWoS-L's RDL interposer is fundamentally superior to an ordinary organic substrate offered by EMIB-T. Organic substrate wiring has coarser line/space dimensions and larger vias, so it cannot provide the same routing density as CoWoS-L's fine-pitch RDL. Where an EMIB bridge connects adjacent dies, Intel can achieve very high interconnect density. But anything that needs to travel beyond those bridges must use the package substrate or cross a topology involving additional bridges.

By contrast, CoWoS-L gives the designer two levels of connectivity: LSIs provide extremely dense local die-to-die connections, while the global RDL interposer provides relatively dense and flexible routing across the entire package. This means the RDL can carry longer, lower-density connections without consuming valuable LSI resources, while still offering much finer routing than the underlying package substrate.

One scenario for Google's choice is that it potentially wanted better power delivery than what CoWoS-L could offer. EMIB-T integrates TSVs for vertical power delivery, sophisticated MIM capacitors for local decoupling, and a dedicated ground plane into its silicon bridges. The combination of these features substantially reduces power-delivery impedance and improves transient response and power integrity, which gives EMIB-T a major advantage over conventional EMIB for power-hungry AI accelerators. However, we have no idea how EMIB-T stacks up against CoWoS-L in the case of Google’s Humufish.

Of course, the larger the RDL interposer becomes, the greater its parasitics can become, potentially limiting scaling unless TSMC finds ways to mitigate them. However, EMIB does not eliminate long-distance wiring: If two distant dies must communicate, those signals still have to travel somewhere, and routing them through an organic substrate is not inherently electrically superior to routing them through a purpose-built RDL interposer. Therefore, it is difficult to claim that Google chose EMIB-T over CoWoS-L, simply because EMIB-T offers superior package-wide electrical characteristics.

After Nvidia suffered yield loss with its Blackwell data center GPUs due to an alleged mismatch in the coefficient of thermal expansion (CTE) among the GPU chiplets, LSI bridges, RDL interposer, and motherboard substrate, which led to warping and system failure, it is reasonable to question the mechanical rigidity of CoWoS-L packages. Nvidia has found a solution for its dual compute chiplet Blackwell packages, and so have other developers of AI accelerators. However, as package dimensions increase, they may behave differently, therefore causing yield losses.

By contrast, EMIB/EMIB-T eliminates the large RDL interposer and embeds small silicon bridges in the organic substrate, so most of the package consists of the substrate itself. This does not make EMIB/EMIB-T packages immune to mechanical failures, as large packages can warp and bend, causing various problems. However, as such packages lack the very source of global thermomechanical stress, they can potentially be more robust mechanically. However, EMIB-T can potentially complicate things because TSVs, additional metal structures, MIM capacitors, and their ground plane make the bridge more complex. Thus, Intel must manage both global package warpage and local stresses around each embedded bridge to ensure the mechanical rigidity of these packages.

Ironically, while CoWoS-L can offer denser package-wide routing, which is better for ultra-large processors, EMIB-T may potentially provide better mechanical rigidity required for such devices. Nonetheless, EMIB-T and its organic substrate do not eliminate package bending or cracking risks entirely.

Economics

If Google's Humufish TPU really moves to EMIB-T, the decision could well be both technical and strategic. Google has the engineering resources to opt for an all-new packaging technology in an effort to lower costs and eliminate dependence on TSMC's constrained CoWoS capacity. Nvidia tends to procure advanced packaging allocations years in advance, so it is possible that Google could simply not get enough CoWoS-L wafers for its 9th-generation TPU.

As a bonus, Google can also build relationships with Intel Foundry without using the company's fabrication technologies. In fact, keeping in mind that Intel and Google already have a strategic agreement covering Intel Xeon CPUs, it wouldn't be too surprising to learn that the cloud giant is courting Intel Foundry as well.

Both Intel's EMIB-T and TSMC's CoWoS-L have their own technological and economic advantages and disadvantages. Perhaps the biggest advantage of CoWoS-L is its predictability, as the company has experience with that tech. However, if Google has decided to drop that predictability in favor of an all-new packaging method, it may well have a combination of technological and strategic reasons to do so.

Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

Intel has unveiled Starfire, a space-grade system-on-chip designed for the U.S. government that pairs eight CPU cores and a three-tile NPU built on its Intel 18A node with an Intel 3 graphics tile, all in one Foveros package. Intel published the Starfire sell sheet, listing two versions that draw 10 W and 35 W and reach up to 45 and 75 TOPS, respectively, rated to run between -55 and 125 Celsius.

Both SKUs share the same layout of four Intel 18A P-cores, four low-power efficiency cores, a three-tile NPU also on 18A, and a four-core Xe GPU with 64 execution units built on Intel 3. The Low Power part runs its P-cores at 1.0 GHz, efficiency cores at 850 MHz, and the GPU between 800 MHz and 1.0 GHz. The Performance part clocks the P-cores to 3.1 GHz, efficiency cores to 2.1 GHz, and the GPU to 2.0 GHz. Both carry 12 PCIe Gen4 lanes, support LPDDR5 or DDR5, and are rated for a 10-plus year lifetime.

Intel builds the CPU and NPU on 18A and the GPU on the older Intel 3, the same node division it used for Clearwater Forest, the 288-core Xeon that stacks 18A compute tiles on Intel 3 base tiles. Smaller transistors hold less charge per stored bit, which makes leading-edge silicon more prone to radiation-induced bit flips, so committing 18A to orbit leans on RibbonFET and design-level hardening rather than a mature, inherently more tolerant node.

The market Starfire is targeting has run on BAE Systems' RAD750 for two decades. That radiation-hardened PowerPC part clocks 110 to 200 MHz, carries 10.4 million transistors, and is built on 150nm or 250nm lithography, per public specifications, and it flies on the Mars rovers, Kepler, and Fermi, among more than 150 spacecraft. BAE's multi-core RAD5545 and the Microchip-built processor NASA is developing to reach 100 times the throughput of current spaceflight chips are the more recent step up. Starfire's up to 75 TOPS and dedicated NPU put it in a different bracket, built for on-orbit AI inference rather than telemetry and control.

Intel lists the radiation data, covering total ionizing dose, single-event latch-up, and single-event effects, as characterization in process, so the part isn't radiation-qualified yet, and it notes the specs are subject to change. Intel Government Technologies is handling Starfire, with samples in Q3 2026 and a pitch of market-competitive pricing and domestic manufacturing. Intel Foundry is the only U.S.-based maker of leading-edge logic, holds Trusted Foundry status, and has tied its 18A and packaging roadmap to Pentagon programs including RAMP-C and SHIP, though 18A yields aren't expected to reach industry-standard levels until 2027.

Apple's planned M7 Ultra chip is being designed to support up to 1.5 TB of unified memory and to push AI performance toward the class of Nvidia's Blackwell accelerators, according to a new Bloomberg report published by Mark Gurman. But whether the lofty top memory config can ship at all will depend on the state of the memory market, and the part isn't expected until 2028. The same report says Apple has compressed its Mac silicon timeline, taping out the M7 roughly six months after the M6.

We've already heard that Apple plans to release a base M6 chip this fall for entry-level Macs, then skip the Pro, Max, and Ultra versions of that generation and move straight to the M7 line. However, Gurman now reckons that we'll see a base M7 in the first half of 2027, M7 Pro and M7 Max at the end of 2027, and the M7 Ultra in 2028. Apple reportedly began taping out the M7 about six months after it started the same process for the M6, which is what has enabled the company to pull the schedule forward.

The 1.5 TB target for the M7 Ultra is roughly twice the capacity Apple has planned for the M5 Ultra, per Gurman, who tied the configuration directly to memory availability. Apple already pulled the 128GB Mac Studio this year over supply constraints as DRAM prices climbed, and a 1.5 TB part would call for far more of the same scarce, high-cost memory.

Apple's current M3 Ultra already reaches 819 GB/s of memory bandwidth by fusing two Max dies, and it's the Ultra tier, not the base chips, that carries the heaviest local-AI workloads. Gurman describes the M7 Ultra as a large step up in AI performance rather than stated parity with Nvidia's data-center silicon. "I'm told the processor dramatically upgrades AI performance, bringing it closer to the class of dedicated AI accelerators such as Nvidia Corp.'s Blackwell," Gurman wrote in his report.

Apple is also preparing an AI server built on the M5 Ultra under the code name J246 for deployment soon, with a second server chip based on the M7 Ultra planned for 2029, according to the report. The 2028 generation, which includes an M8 chip code-named Soko and a high-end Mac part called Cardinal, moves to a 1.4nm process. That aligns with TSMC's A14 node, which the foundry has scheduled for mass production in the second half of 2028.

None of the dates or specifications have been confirmed by Apple.

SK hynix has completed the largest-ever foreign company IPO in U.S. history, raising $26.5 billion in its Nasdaq debut today, July 10. The South Korean memory giant sold 177.9 million American depositary receipts (ADRs) — a U.S.-listed stand-in for a foreign share — at $149 apiece, each representing a tenth of a Seoul-listed share. The offering was more than seven times oversubscribed and drew demand from more than 500 investment firms, according to Financial Times. Temporary Nasdaq trading is underway under the ticker SKHYV before regular-way trading begins as SKHY on Monday, July 13.

The offering was led by Bank of America, Citigroup, Goldman Sachs, and JPMorgan, with nine additional firms rounding out a 13-bank syndicate. Anchor demand came from heavyweight institutions including Baillie Gifford, Coatue Management, and Situational Awareness Partners, which together signaled interest in as much as $7 billion of stock, according to people familiar with the matter cited by Financial Times.

SK hynix is the world's leading maker of high-bandwidth memory (HBM), the vertically stacked DRAM that has become critical infrastructure for AI accelerators. The company has said it will steer the proceeds toward boosting its AI-memory manufacturing capacity. Confirmed build-outs include the first-phase fab at the massive Yongin semiconductor cluster, a new P&T7 advanced-packaging line in Cheongju, and EUV lithography equipment slated for delivery by the end of next year. Separately, SK hynix is constructing its first U.S. production site, a $4 billion advanced-packaging plant in West Lafayette, Indiana, targeted for completion around 2028. The facility is eligible for up to $458 million in CHIPS Act grants and up to $570 million in federal loans.

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SK hynix is seeing sensational growth thanks to the ongoing AI boom. The company is reportedly on track to post over 200 trillion won ($133 billion) in operating profit this year, a record-breaking figure that would see SK hynix employees earn around $400,000 each in bonuses. The company’s Seoul-listed stock is up roughly 220% year-to-date and has climbed more than sixfold over the past year.

In late June, SK hynix briefly surpassed Samsung as South Korea's most valuable company, closing at around 2,080 trillion won (about $1.35 trillion), a meteoric rise for a company that almost declared bankruptcy in 2001 and, more recently, recorded an annual operating loss of 7.73 trillion won in 2023. That rise doesn't seem like it will be slowing down any time soon. SK hynix has said its entire 2026 output of HBM, DRAM, and NAND is already sold out, with the crunch expected to extend into 2027.

Japanese chipmaker Rapidus will try to lure customers away from TSMC not only by offering a different kind of service, but also by offering its manufacturing services at lower prices, chief executive Atsuyoshi Koike announced this week. The company's plan to rival TSMC in terms of pricing appears on the surface as a risky move, as the company moves to develop leading-edge process technologies.

At present, Rapidus is looking at charging ¥3 million – ¥3.5 million ($18,550 - $21,635) per wafer processed using its 2nm-class fabrication process, which is significantly below TSMC's rumored quote of around $30,000 per N2 wafer, and is comparable to what Samsung is rumored to offer with its SF2 manufacturing technology, set at $20,000 per-wafer. Actual prices will depend on exchange rates, though Rapidus' general idea of offering significantly lower quotes than TSMC is immediately apparent.

Rapidus plans to start high-volume manufacturing (HVM) using its 2nm-class fabrication technology by the second half of 2027. The ramp of a new fab will take some time, so expect meaningful volumes from Rapidus to only be produced in 2028, when TSMC's N2 will no longer be its leading-edge node.

By the time Rapidus starts HVM at its IIM-1 in 2027, TSMC will have ramped production of chips using its performance-enhanced N2P manufacturing node, and the company will also absorb all the yield learning with gate-all-around the company will have with its N2 present at five fab modules. Furthermore, by the time Rapidus reaches meaningful volumes at IIM-1 in 2028, TSMC will have ramped up production using its advanced A16 fabrication process with Super Power Rail backside power delivery as well as a 3^rd-generation 2nm-class node named N2X.

In addition to the vast 2nm-capable capacity and process maturity that should be kept in mind when comparing Rapidus with TSMC, there is another factor to consider. One of TSMC's major advantages over its rivals is its Open Innovation Platform (OIP) ecosystem, which includes comprehensive electronic design automation tools, silicon-proven IPs, even for the latest nodes, a host of contract chip designers, and advanced packaging services not only from TSMC but also from its partners. For now, neither Rapidus nor Intel and Samsung Foundry can offer anything close to TSMC's OIP.

Given the advantages that TSMC will likely have over competitors with its 2nm-class fabrication technologies in 2028, lower pricing may be among the few ways to compete against the world's largest foundry. Rapidus' strategy of offering lower quotes while operating a single fab does not seem like the best way of earning money, but perhaps a certain way to lose it.

However, Rapidus may have another ace up its sleeve with single wafer processing across all process steps. The approach will greatly speed up the production cycle, which will be its indisputable advantage over other chipmakers, albeit at the cost of tool usage efficiency. Will lower quotes and shorter production cycles be enough for Rapidus to win customers from TSMC? Only time will tell.

Rapidus is reportedly negotiating with more than 60 potential customers, mainly overseas companies, which demonstrates the company's ambitions to become a viable rival to the global leader TSMC as well as contract chipmakers Intel Foundry and Samsung Foundry.

Researchers in Korea and Japan have presented two separate memory-integration proposals that aim to increase HBM (High-Bandwidth Memory) capacity and bandwidth without trapping more heat inside ever-taller DRAM (Dynamic Random Access Memory) stacks, one of the most pressing challenges facing future AI accelerators. Presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits held in June, the two approaches — V-Die from a Korean research collaboration and MOSAIC from a University of Tokyo-led group — both explore the same broad idea of standing DRAM memory dies on their edges instead of stacking the memory dies only upward like conventional HBM.

The Korean proposal, called Vertical-Die (V-Die), was presented by researchers at the Ulsan National Institute of Science and Technology (UNIST). The design rotates custom DRAM dies upright, drops through-silicon vias to free die area for more memory cells, gives each die its own bottom-edge I/O, and runs liquid-cooling channels between adjacent dies. In simulations against an HBM4 system at equal capacity, the V-Die system reportedly achieved 540 tokens per second on a GPT-3-sized workload, compared to 296 tokens per second for HBM4.

The Japanese project, MOSAIC, takes a similar “sideways stack” idea but focuses on the practical difficulty of connecting so many vertical dies to a GPU or package substrate. Presented by University of Tokyo researchers, the MOSAIC work uses orthogonal die stacking and a contactless die-to-die interface, in which data is transferred through tiny inductive coils rather than requiring every signal pad to land perfectly on a physical contact. The researchers say the prototype interface achieved up to 4 Gbps per channel, while the memory structure could double HBM4-class capacity in a DRAM-on-GPU configuration.

Both projects aim to solve the growing problem of AI chips being held back by memory. Modern accelerators can perform enormous amounts of computation, but large, powerful models depend on moving huge amounts of data between memory and compute. This is why HBM has become one of the defining technologies of modern AI hardware.

The technology addresses the memory wall by stacking multiple DRAM dies vertically on a base die and placing that stack very close to the processor. Nvidia's Blackwell Ultra B300, for instance, carries up to 288GB of HBM3E memory, without which much of the silicon would sit idle waiting for data. The dies are connected via through-silicon vias (TSVs) — tiny vertical channels etched through the silicon and filled with metal.

The stack then communicates with the GPU over an extremely wide interface, often routed through a silicon interposer or an advanced package. This is the core reason HBM can deliver terabytes per second of bandwidth: it uses a very wide, very short data path instead of sending memory traffic across a motherboard, as with conventional DIMMs (Dual In-line Memory Modules), physical sticks of RAM used in computers.

However, that same structure creates several problems. While taller stacks add more capacity, they also make it harder to remove heat. Heat generated in the lower dies and at the high-speed interface must pass through layers of silicon, bonding materials, underfill, and package structures before it reaches a heat spreader. Furthermore, TSVs consume die area that could otherwise be used for memory cells, and as bandwidth rises, more routing and I/O place additional pressure on both signal integrity and packaging costs.

HBM4, the latest generation of HBM, addresses a number of these challenges. Meanwhile, companies such as SK hynix, Samsung, and Micron are racing to improve speed, capacity, base-die performance, and thermal management. SK hynix has already shown iHBM, which embeds cooling elements into the HBM interface area, and Samsung has shown an HBM5 mockup with Heat Path Block cooling to more directly extract heat from the stack. However, they all retain the same upward stacking structure.

This convention is what V-Die and MOSAIC are challenging. By standing DRAM dies upright, the researchers expose far more silicon surface area to the cooling path. In theory, this turns the memory stack into something closer to a heat-sink fin array, where heat can move laterally and escape more directly instead of being trapped in the middle of a thick vertical pile. It also opens the door to new connection schemes along the bottom or side of each die, rather than forcing every die to communicate through TSVs running vertically through the stack.

For V-Die, the key shift is removing TSVs from the memory dies and replacing them with bottom-edge connections. Each DRAM die gets its own I/O along the bottom edge and connects directly to the substrate, with links reportedly spaced every 20 microns. The team says this layout gives four times as many connections as HBM4 and cuts memory read time by 37%, although some signals must travel farther across the package to reach the processor.

Cooling is the other half of the V-Die argument. The proposal places microfluidic cooling channels between adjacent upright DRAM dies, allowing coolant to dissipate heat closer to its source. According to the researchers, this could keep the stack around 45°C, far below the 80°C-plus range associated with dense HBM systems. In a simulated 16-die stack matched to H100-class hardware on a GPT-3-scale model, V-Die hit 540 tokens per second, compared to HBM4's 296, and cut first-token latency by 32%, or about 24 milliseconds.

MOSAIC, meanwhile, is focused on making the sideways stack manufacturable. Because the dies are assembled flat and then turned on edge, even a few microns of die-thickness variation across dozens of dies can add up to an alignment miss where the signal pads no longer land. The Japanese team’s answer is a contactless interface based on inductive coupling. One side of the memory die carries oblong coils, while a corresponding set of coils sits on the substrate or mating chip. Current in one coil induces a signal in the other, allowing data to cross the small gap without a direct metal-to-metal signal contact. This eliminates the need for precise overlapping, giving the package greater tolerance for assembly variation. Power, which requires fewer, larger connections than data, can still be supplied via physical contacts on the sides of the memory cube.

The VLSI MOSAIC prototype achieved up to 4 Gbps per channel and demonstrated TSV-free 3D integration for a memory-on-GPU layout. The team says the approach can enable twice the memory capacity of HBM4 without significantly increasing peak temperature. A related bump-MOSAIC hardware demonstration at ECTC used 100-micron-pitch microbumps, achieved stacking alignment within 6 microns as verified by X-ray CT, and showed a configuration with three times the thermal conductivity of conventional stacking while adding up to 30% more memory capacity.

While the results look promising, neither V-Die nor MOSAIC is close to replacing commercial HBM. Neither is close to shipping. V-Die is still a proposed architecture, with a prototype in the works to validate its thermal and electrical behavior; MOSAIC has proof-of-principle hardware, but the researchers have yet to show it scales to commercial DRAM capacity, yield, cost, and reliability.

Still, any viable solution to the multifaceted AI memory problem is a welcome development. SoftBank and Intel’s Z-Angle Memory (ZAM) and NEO Semiconductor’s 3D X-DRAM — both still in development — aim to solve the constraints of conventional memory. Meanwhile, the overall market is already feeling the squeeze on price and availability, even as memory makers divert capacity toward the more lucrative AI HBM and server products, driving consumer RAM prices even higher.

Micron has said it will invest up to $3 billion in the U.S. semiconductor supply chain, with $500 million of that going to GlobalWafers as strategic financing for its 300 mm raw silicon wafer plant in Sherman, Texas, alongside a 10-year agreement giving Micron access to that plant's wafer output. In a separate announcement, the memory maker raised its planned U.S. spending to more than $250 billion through 2035, up from $200 billion, and confirmed the first concrete pour at its Clay, New York campus more than a quarter ahead of schedule.

Sherman is the sole operating facility in the U.S. capable of producing advanced 300 mm raw silicon wafers, the substrate on which every leading-edge DRAM, NAND, and logic die is built. GlobalWafers opened the plant in May last year and holds a $406 million CHIPS Act award covering the site and a silicon-on-insulator facility in St. Peters, Missouri. The 142-acre campus is designed for up to six phases, one of which is running. Micron's other American sites draw their wafers from Japan, Taiwan, Germany, and South Korea; Shin-Etsu, SUMCO, GlobalWafers, Siltronic, and SK Siltron together control the overwhelming majority of global 300 mm supply, making raw silicon the most concentrated layer in the chip space.

Doris Hsu, chairperson and CEO of GlobalWafers, set out her terms for building phase two at Sherman during the plant's opening last year, telling Reuters the company needed profitability at the first two phases, customers willing to sign long-term contracts, reasonable pricing, prepayments, and government support. Thursday's announcement supplies most of that list in a single transaction.

Wafer suppliers spent the 2023-2024 downcycle protecting margins rather than adding capacity, and SUMCO is winding down 200mm production at Miyazaki this year while holding the line on new 300mm expansion. Customers, not suppliers, are therefore now underwriting the capacity. The last time the industry did this, during the 2017-2018 megacycle, chipmakers signed prepaid long-term agreements that turned into liabilities when pricing rolled over.

Silicon wafer shipments reached 3,275 million square inches in Q1 2026, up 13.1% year over year, with SEMI.org attributing the growth to AI data center demand across advanced logic, memory, and power devices. Micron's first new Idaho fab, ID1, is expected to begin wafer output in mid-2027, and production at Clay isn't expected until around 2030. The company began making 1-alpha DRAM at its Manassas, Virginia fab in May.

Micron told investors last December that it can serve only half to two-thirds of customer demand, and nothing announced Thursday changes the supply position of DRAM this year or next.

Rapidus is bidding Japan's entire return to leading-edge logic on one fab in Chitose, Hokkaido, and the schedule now turns on a 2027 mass-production target for a 2nm process that no high-volume customer has yet committed to.

Since opening the IIM-1 pilot line in April last year, the company has run wafers through Japan's first mass-production-grade EUV scanner, produced a 2nm gate-all-around prototype that reached its expected electrical characteristics in July, and closed a ¥267.6 billion funding round in February that made the Japanese government its largest shareholder. CEO Atsuyoshi Koike said the same month that more than 60 companies are in talks over 2nm capacity, but not one has yet signed a volume agreement. Given that its entire production base is the single IIM-1 facility, this leaves Rapidus with no diversification and no fallback site if the node doesn’t go ahead as planned.

However, the fab has the hopes of an entire nation pinned on it, and its plans are promising. Here's the breakdown.

A ticking clock on IIM-1

IIM-1, short for Innovative Integration for Manufacturing, broke ground in September 2023 at Bibi in Chitose, with the cleanroom completed in 2024. ASML delivered a TWINSCAN NXE:3800E in December 2024, the first mass-production-grade EUV system installed in Japan, and the tool completed its first exposure on April 1st last year. The pilot line also began operating that month.

Rapidus is currently targeting 2027 for mass production, but the company has given that date without any further qualification, with its business plan simply pointing to production beginning in the second half of fiscal 2027 and scaling to full volume in 2028. The same plan sets out a capacity ramp from roughly 6,000 wafer starts per month at the outset to around 25,000 within the first year, a fourfold increase that Rapidus is counting on to bring per-wafer costs down.

IIM-1’s siting in Chitose offers the abundant water that wafer cleaning demands, a cool climate that eases cooling loads, and some of Japan's strongest renewable-energy potential across wind, solar, and hydro. Local and prefectural authorities have organized around the project under a “Hokkaido Valley” initiative that aims to build a semiconductor cluster spanning Tomakomai, Chitose, and Ishikari.

The 2nm process

Rapidus’s 2nm node is a gate-all-around nanosheet design derived from the IBM 2nm process announced in 2021, the product of a partnership signed in December 2022. Rapidus engineers worked alongside IBM at the Albany NanoTech Complex in New York to learn the node before transferring it to Chitose. More than 150 Rapidus engineers were dispatched to Albany across 2023 and 2024 to learn the node, with roughly 80 later returning to Chitose to transfer and tune the process for production, according to IBM.

The differentiator the company is leaning on is manufacturing flow, with IIM-1 running single-wafer front-end processing throughout, branded as Rapid and Unified Manufacturing Service, with per-wafer data fed into AI models that Rapidus says will accelerate yield learning and shorten turnaround compared with the batch processing used by TSMC and Samsung. It’s understood that the 2nm Process Design Kit (PDK) reached early customers in Q1 this year. Still, Rapidus hasn’t yet published a yield figure, and its public claims extend only to the prototype attaining expected electrical characteristics.

The program extends beyond the wafer, with Japan’s New Energy and Industrial Technology Development Organization (NEDO) approved fiscal 2026 budget for Rapidus providing funds for chiplet and package design and manufacturing technology for 2nm-generation semiconductors, alongside front-end work. The company has also floated panel-level glass-substrate packaging as part of its longer-term roadmap. Building that back-end capability in Chitose rather than outsourcing it would mirror the integrated approach Intel and Samsung take.

Japan’s government as a shareholder

Rapidus’s February funding round closed at ¥267.6 billion, or about $1.7 billion, split between ¥100 billion from the government through the Information-technology Promotion Agency and ¥167.6 billion from 32 private companies. The state investment, the first made possible by a 2025 revision to Japan's subsidy law permitting government equity in Rapidus, made Tokyo the largest single shareholder, with a golden share giving it veto power over major decisions, including share transfers and technology partnerships.

That round sits on top of a much larger commitment from November, when Japan's Ministry of Trade and Industry added approximately ¥1 trillion in support across fiscal 2026 and 2027, lifting total planned government backing to about ¥2.9 trillion. The government added a further ¥150 billion in equity in early June, taking Rapidus’s combined capital and capital reserves to around ¥425 billion. The shares the state holds are structured as largely non-voting, keeping its formal voting position near 11.5%, but they convert to a controlling stake of roughly 60% if performance deteriorates, a clause that pairs with the golden share to give Tokyo both upside alignment and a downside lever.

Rapidus’s buildings and equipment are also currently owned by Japan's New Energy and Industrial Technology Development Organization (NEDO) and leased back, with the company previously obligated to buy them by fiscal 2027. The government now plans to construct fab buildings and tools with public money across fiscal 2027 and 2028 and transfer them to Rapidus as in-kind contributions in exchange for shares, removing that purchase obligation and converting what had been grant funding into direct ownership.

The customer conundrum

Koike said in February that Rapidus was in discussions with more than 60 companies and had issued preliminary price quotations to around 10 of them. The names attached to those talks in reporting by TrendForce are IBM and the Canadian RISC-V accelerator startup Tenstorrent, with Fujitsu, a founding investor, separately weighing whether to outsource a 1.4nm CPU for a successor to its Fugaku supercomputer around 2029.

The design partnerships Rapidus has actually signed, however, are with smaller players building energy-efficient AI silicon. Tenstorrent, the firm led by chip architect Jim Keller and currently being considered for takeover by Qualcomm, agreed back in 2023 to co-develop an edge-AI accelerator on the 2nm node under a NEDO and Leading-edge Semiconductor Technology Center (LSTC) project, with Tenstorrent handling the CPU and Rapidus' AI Chip Design Center building the accelerator. Rapidus signed a separate memorandum of cooperation with RISC-V inference designer Esperanto Technologies in May 2024.

Neither of these amounts to the committed high-volume order that Rapidus needs, and fast. Koike has described interest as growing “like a runaway steam engine,” but interest is not the same as allocation. Rapidus’s cost model depends on filling the 25,000-wafer ramp, and a fab running well below capacity carries the same fixed depreciation as a full one. The company has said its homegrown 2nm chips could cost around 10 times more than Japan’s current mainstream parts, a premium that’ll only narrow with volume.

Japan's two-track strategy

Rapidus is the leading half of a national plan that’s running on two tracks. The other is TSMC's JASM venture in Kumamoto, on the southern island of Kyushu, where a first fab backed by Sony, Denso, and Toyota began mass production in December 2024 on mature 12nm, 16nm, 22nm, and 28nm nodes aimed at automotive and industrial chips.

A second Kumamoto fab broke ground in 2025, and its planned node was upgraded twice, first to 4nm and then to 3nm, with production targeted around 2028. Tokyo is therefore funding mature and specialty capacity through a proven foreign operator in the south while betting on a domestic startup to reach the leading edge in the north. The Kumamoto plants carry far less technical risk and are already shipping; Rapidus carries nearly all of the program's execution risk and none of its proven output.

Even as the 2nm line ramps, Rapidus plans to begin 1.4nm process development in 2026, start construction on a 1.4nm fab in 2027, and reach mass production around 2029. The node leans on the company's research ties: Rapidus joined imec's core partner program in April 2023, giving it access to the Belgian institute's pilot line, and imec's position is that 1.4nm single-patterned layers require High-NA EUV, the 0.55 numerical-aperture tool that resolves the most critical metal layers in one exposure rather than several. Total lifetime investment is expected to exceed ¥7 trillion, with roughly ¥5 trillion needed just to reach stable 2nm production, according to figures cited by both TrendForce and Nikkei.

Rapidus’ financials highlight how far all this is from being self-sustainable, having posted a ¥375 million loss for fiscal 2025 with total assets of ¥749.5 billion, while still aiming to raise around ¥1 trillion from private investors. The ASEAN+3 Macroeconomic Research Office has been cited as estimating that committed funding still falls short of the roughly ¥5 trillion needed for stable production, dependent on a private investor base that has yet to materialize at scale.

Meanwhile, TSMC moved its N2 node to volume production in late 2025, and Samsung began first-generation SF2 mass production the same year, which puts Rapidus roughly two years behind both on a node that customers can already buy elsewhere with proven yields. There’s also something of an adversarial backdrop developing: TSMC employees were reportedly accused last year of taking 2nm trade secrets said to be destined for Rapidus, an allegation a Japanese government official later characterized as non-critical. The episode has no confirmed bearing on Rapidus’s process, which is built on IBM IP.

Rapidus is targeting operating profitability around fiscal 2030 and an IPO in fiscal 2031, a timeline that assumes the 2027 ramp lands on schedule and that the customers now in talks convert into committed volume. Three milestones will indicate whether those targets are possible: a named customer with a committed volume order, evidence that 2nm yields are tracking toward the levels TSMC and Samsung already run at, and confirmation that the capacity ramp is hitting its 25,000-wafer target.

An Intel patent application published on July 2, 2026, surfaced by Underfox, has revealed the company's plans for a new high-bandwidth memory (HBM) architecture that aims to ease the packaging and cost bottleneck of today's interposer-based HBM. The patent application — filed back on December 26, 2024 — describes what Intel calls cross-batch memory (XBM), an "ultra-high-bandwidth memory with backend transistors" built with the goal of matching HBM4's footprint while swapping conventional DRAM and its ultra-wide interface for back-end-of-line (BEOL) transistors and serial Universal Chiplet Interconnect Express (UCIe) links.

Intel's proposed design is a memory stack that addresses the assembly costs that make conventional HBM expensive by dropping the costly silicon interposer and shrinking the package, while building in its own defect repair.

The filing lays out a stack of memory dies, each holding one-transistor one-capacitor (1T1C) DRAM fabricated in the back-end-of-line, wired together with through-silicon via (TSV) "gutters" and both-sided high-bandwidth interconnect (HBI) connections. Intel describes dies of roughly 1.5 gigabytes (GB) apiece — 768 "datablocks" arranged in a 32-by-24 grid, grouped into eight channels of eight sub-channels each — stacked eight high and scaling to 16. Data then leaves the stack over UCIe I/O bundles running at 32 gigatransfers per second (GT/s), funneled out through a base die.

To understand what Intel is changing, it helps to recall what standard high-bandwidth memory does. HBM stacks DRAM dies vertically on a base logic die, threads them together with TSVs, and communicates with the processor across a silicon interposer using an extremely wide parallel interface — on the order of 1,024 bits per stack. This width is how HBM delivers its bandwidth, but it is also what makes it expensive to package and hard to scale, as every one of those wires has to be routed through an interposer sitting between the memory and the compute die. As AI accelerators have outrun the rate at which memory can feed them, this "memory wall" has become the dominant constraint on performance, which is why nearly every large chipmaker is now attacking the interface and the stack rather than the logic.

XBM's first major change is structural. Conventional DRAM cells are built in the front-end-of-line, the base silicon layer where transistors are normally fabricated. XBM instead moves the 1T1C cell into the back-end-of-line, the metal-and-via stack above the transistor layer, using thin-film transistors. Building memory in the BEOL is what lets Intel pack the die into many small, independently addressable memory blocks, and it is the same backend-transistor direction Intel has pursued for placing memory directly over logic.

The second change is the interface. Rather than HBM's wide parallel PHY, XBM serializes data onto UCIe bundles at 32 GT/s, with the base die handling the serialize/deserialize step and routing all I/O to the compute die. Moving to a standard chiplet interconnect is what makes the design "chiplet-native" and, Intel argues, simpler and cheaper to package than an interposer-bound HBM stack. The tradeoff is that 32 GT/s is UCIe's current top data rate, so the interface is already running at the spec ceiling rather than leaving obvious headroom.

Intel also leans heavily on repairability. The base die carries dedicated spare channels, built-in self-repair (BISR), decode and debug logic, and four sub-channels of redundant memory arrays that act as fungible spares for defects in the dies above — post-assembly repair designed to claw back yield on a very tall stack.

A large portion of the patent application focuses not on the memory cell at all but on how to mount it. Intel details memory-on-package (MoP) and "reversed overhang" structures aimed at cutting the stack's Z-height — conventional MoP can add 300 to 350 micrometers (µm) — while removing the stiffener normally needed to control warpage and feeding DRAM power directly from the voltage regulator. This is the concrete basis for the "smaller, cheaper package" claim.

XBM should not be confused with ZAM (Z-Angle Memory), the architecture Intel is co-developing with SoftBank subsidiary SAIMEMORY and set to present at the VLSI Symposium 2026. ZAM's innovation is on the bonding side — a fusion-bonded, nine-layer stack of largely conventional DRAM with roughly 3-µm-thin silicon between tiers — and it reportedly targets around twice HBM4's bandwidth density, with commercialization aimed at 2029. XBM, by contrast, is an Intel-only filing that changes the DRAM transistor itself and the interface. Read together, they suggest Intel is running at least two parallel HBM alternatives, a fitting move for a company that began in 1968 as a memory maker.

The caveats on Intel’s proposed HBM architecture are the usual ones for a patent. The patent was filed 18 months ago, and there’s currently no product or roadmap, signaling potential intent rather than a shipping part. The UCIe interface is already at its rate ceiling, backend-transistor DRAM remains unproven at manufacturing scale, and the whole thing still has to justify itself against HBM4E and Intel's own ZAM timeline.

Huawei is planning to enter South Korea's AI accelerator market in the fourth quarter of 2026 with its Ascend 950 series processors and Atlas 950 SuperPod AI computing platform, according to a report by Korean publication ETNews last week. The move would mark Huawei's first major push into one of Nvidia's strongest overseas AI markets, with the Chinese company reportedly planning to undercut Nvidia on price while pitching its hardware as an alternative for customers seeking to reduce dependence on the US chipmaker.

The chips spearheading the move are the Ascend 950PR and the Ascend 950DT, the latest models in Huawei's Ascend line of neural network processing units (NPUs) for AI computing. The Ascend 950PR, an inference-focused chip, entered mass production in April, while the Ascend 950DT, designed for AI training workloads, is scheduled for release in the fourth quarter. Both processors are expected to debut in Korea together with the Atlas 950 SuperPod, an integrated AI computing platform that Huawei says can scale to as many as 8,192 Ascend processors in a single deployment.

According to the report, Huawei Korea has completed master distributor agreements with two local partners, Hansol PNS and longtime Huawei collaborator SK Shieldus, and has already begun preparations for commercialization, including technical training, pricing policies, marketing strategies, and localized branding for the Korean market. Huawei is reportedly building its Korean campaign around aggressive pricing and processing power.

The company claims its Ascend 950PR delivers approximately 2.87 times the inference performance of Nvidia's H20 AI accelerator while costing around one-quarter as much. The H20 is Nvidia's export-compliant AI processor developed specifically for the Chinese market after US export restrictions prevented sales of more powerful GPUs. Huawei concedes its chip falls short on raw performance compared to Nvidia's flagship H200, but argues the gap can be closed by clustering thousands of Ascend processors together via the Atlas 950 platform.

The Ascend 950 series uses Huawei's "self-developed" high-bandwidth memory (HBM), which the firm constructs from dies obtained from foreign sources. The 950PR uses Huawei's HiBL 1.0 memory and the 950DT its HiZQ 2.0 standard.

Huawei's strategy for the South Korea move, which comes as the country's demand for AI infrastructure surges, appears aimed at competing on both cost and ecosystem maturity, positioning its hardware as a viable Nvidia alternative. Nvidia's flagship accelerators reportedly command tens of thousands of dollars each, with supply remaining tight. A chip at one-quarter the price of the H20 gives Korean buyers a real incentive to seek a second source. Huawei also says it is improving compatibility between its Compute Architecture for Neural Networks (CANN) software stack and Nvidia's CUDA programming ecosystem to ease migration for developers.

Huawei is not new to penetrating South Korea's market, having successfully entered the country’s highly competitive LTE equipment market in 2013. However, past experience is not a guarantee of future success. ETNews notes that industry observers expect Huawei to face resistance in Korea, citing local sensitivity toward Chinese technology, security concerns, the power and heat overhead of high-density Chinese silicon, and the vendor lock-in risk of adopting a proprietary stack. There is also a domestic dimension, as the Korean AI-chip scene is made up largely of accelerator startups, making Huawei's arrival — backed by its supply scale and software depth — read as a competitive threat.

Atomic Semi, the semiconductor tooling startup founded by chip architect Jim Keller and DIY fabrication pioneer Sam Zeloof, has rebranded as Fab2 and moved its operations to Texas, according to the company's new site at fab2.com. The rebrand recasts the company around the idea they're calling a "fab fab," a factory that mass-produces small semiconductor fabs and the tools inside them.

Fab2 designs and builds every tool in its fabs in-house, from pumps, valves, and gas lines to lithography and the vacuum chambers that house it. The company assembles those components into machines, the machines into complete fabs, and then aims to mass-produce the fabs themselves. It pairs the hardware with Studio, an in-browser, collaborative EDA tool for layout, schematic, and simulation work, previously branded as Atomic Studio.

Rather than moving 300mm wafers through ginormous production lines, Fab2 targets small, software-defined fabs that pattern chips far smaller than a wafer and turn prototypes around in hours. Zeloof built the concept's proof point as a teenager, fabricating lithographic chips in his parents' garage down to roughly 300nm features before co-founding this company with Keller in 2022.

The method's main constraint, however, is throughput. Electron-beam lithography writes patterns directly rather than projecting them through a mask, which makes it slow: a single patterning step on a small chip can take far longer than an EUV scanner needs to expose an entire 300mm wafer. That's a big tradeoff that only really suits prototyping and low-volume runs rather than high-volume production at commercial foundries.

Fab2 now operates three sites: a 120,000 square foot facility in Austin serves as the new headquarters for research and production, a 30,000 square foot site in Lockhart houses the "fab fab" itself, and the original 25,000 square foot "garage fab" remains in San Francisco.

Fab2 said it shifted its hiring focus to Texas after four years in California, and Tracxn lists the company at around 84 employees as of May 2026. The startup raised a reported $15 million seed round in 2023, led by the OpenAI Startup Fund, at a valuation of about $100 million, with angel backing from Naval Ravikant, Nat Friedman, and Fred Ehrsam.

In moving to Texas, Fab2's model of many small, printable fabs now sits beside the likes of Tesla and SpaceX, which announced Terafab back in March, a single Austin megafab targeting a terawatt of annual compute at a cost of up to $119 billion. The contrasting businesses are clearly not competitors; Fab2 sells small fabs and prototyping speed, while Terafab is built for high-volume AI. But they represent competing answers to the same question of how the U.S. should expand its chipmaking capacity — consolidate everything in massive manufacturing campuses, or distribute production across many small, replicable fabs?

Intel has resolved wafer-to-wafer yield variability issues with its 18A process technology, according to a report from BlueFin Research Partners. If the report coming from an unofficial source is accurate, then Intel can expect consistent and predictable yield improvements for its products made using the latest 1.8nm-class node from now on.

"Intel 18A wafer-to-wafer yield issue resolved; ramp to 12-15K wpm at both sites ongoing," BlueFin Research Partners wrote in a note to clients.

If the information is accurate, then products made using Intel's 18A process technology will no longer be plagued by wafer-to-wafer variability, an issue where good wafers and poor wafers are produced in the same production flow. However, wafer-to-wafer variability is only one contributor to yield loss, so fixing it means that Intel can now consistently improve product yields, but it does not necessarily mean overall yield is where Intel wants it to be.

Generally, a die yield defined by multiple factors, including defect density (which in turn is defined by random defects and systematic defects), within-wafer variability (differences between the center and edge of the same wafer when it comes to things like critical dimensions uniformity, line edge roughness, or stochastics; something that Intel has been improving recently), wafer-to-wafer variability (die yield and/or parametric yield differ from wafer to wafer), and packaging yield. When it comes to actual products, we should mention parametric yields (dies may be defect-free, but they do not meet performance and/or power specifications) as well as reliability screening (dies are functional and meet required specifications but fail burn-in tests).

That said, saying that Intel has 'fixed wafer-to-wafer yield issues' most likely means the process is now much more consistent from wafer to wafer, which clearly reduces lot-to-lot variation and makes production more predictable. However, it does not mean that defect density has reached target levels, parametric yield is optimal, and overall economic yield is where Intel wants it to be. What it does mean is that at a consistent yield improvement level (Intel once mentioned 7% per month for 18A), Intel is set to reach its target goals within a predictable timeframe.

In addition, the report claims that Intel now has capacity of around 30,000 wafer starts per month across its D1X development fab (presumably module 3) in Oregon and Fab 52 high-volume fab in Arizona (confirmed by @Alex_Intel_), which is a solid result at this point of the ramp cycle. However, without information about overall die yields and parametric yields of Intel's 18A products, it is hard to assess whether Intel can now produce enough Core Ultra 3 'Panther Lake' and Xeon 6+ 'Clearwater Forest' processors. Meanwhile, it should be noted that using a development facility for high-volume manufacturing (HVM) is costlier than using a fab that was designed to be an HVM fab from the start.

Meanwhile, it looks like Intel is set to continue such a practice with its next-generation 14A (1.4nm) fabrication process, according to BlueFin. The company plans to make 'D1X the initial HVM fab for 14A,' whereas the first phase of Intel's Ohio One semiconductor manufacturing site in Ohio will serve as the second HVM facility to make 14A chips, BlueFin claims. Intel recently confirmed that it intends to initiate high-volume production of chips using 14A in 2029. Ohio One first phase (Mod 1) is set to be completed in 2030, which means that it will come online 'between 2030 and 2031,' according to Intel.

Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.

Earlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.

Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial.

Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.

"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."

Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.

Tesla has hired Gary Jiang, an Intel veteran who most recently was responsible for installing equipment and transferring Intel's leading-edge 18A technology process from development fab in Oregon to the company's high-volume fab in Arizona, as spotted by Electrek.co. The appointment marks the first publicly identified senior leadership hire for Elon Musk's semiconductor production project, Terafab, which demonstrates Tesla's effort to build an experienced semiconductor manufacturing organization from the ground up by hiring veterans from other companies.

Tesla poaches an Intel veteran

Gary Jiang joined Tesla in June 2026 after spending over 17 years at Intel, according to his LinkedIn profile. Interestingly, there is little to glean about his current role from his LinkedIn profile, aside from noting that he is a director at Tesla. His final position at Intel was as Factory Manager, where he oversaw the construction of the production facility, the installation of fabrication equipment, factory startup, product certification, preparation for high-volume manufacturing, and, ultimately, the transfer of Intel 18A technology from the development fab in Oregon to high-volume Fab 52 in Arizona.

Earlier in his Intel career, Jiang held multiple management positions at the company's Ocotillo campus in Chandler, Arizona, where he managed technician teams accountable for startup, ramp, yield, and output for 22nm, 14nm, and 10nm-class process technologies (which include Intel 10nm SuperFin and 10nm Enhanced SuperFin/ Intel 7) at Fab 32 and Fab 42.

Tesla has been looking for a Technical Program Manager (TPM) for semiconductor infrastructure, focused on end-to-end fab program delivery, since March, but without any success, as the job listing is still listed on the company's website. Therefore, Terafab — the joint initiative between Tesla, SpaceX, and xAI — still does not have a formal leader who is going to lead the whole project.

In his most recent role at Intel, Gary Jiang worked closely with supply chain, finance, and materials logistics for new factory planning for output, wafer cost, yield, and profit & loss, according to his LinkedIn profile. He also managed the billion-dollar capital equipment and startup of the fab. Hence, without any doubt, Jiang appears to have been one of the senior manufacturing leaders responsible for building and equipping Intel's new 18A-capable manufacturing facilities in Arizona (primarily Fab 52, and potentially Fab 62 as the campus expands). However, it would still be inaccurate to say he was the person responsible for building Fab 52 alone.

Jiang's skills roughly match what one would expect from a senior manufacturing executive helping commission a new leading-edge fab, so he will be instrumental in turning a newly constructed fab shell (or even cleanroom) into a production-ready semiconductor manufacturing facility.

However, he did not oversee the entire Fab 52/Fab 62 program and was not responsible for every stage of the project — from permitting and groundbreaking to construction, tool installation, and the ramp to high-volume manufacturing. Likewise, he is unlikely to lead the Terafab project as a whole. Nonetheless, given that Terafab is set to license Intel's 14A process technology, Gary Jiang is probably among the best candidates to equip a fab for an Intel manufacturing node.

One major caveat

In fact, one of the most confusing parts about Tesla's hiring people to work at Terafab is that Tesla itself will not own any high-volume semiconductor production facilities; SpaceX will, according to Elon Musk.

In the near term, Tesla plans to build a $3 billion semiconductor R&D center at its Texas campus. The facility will house a small pilot line capable of processing a few thousand wafers per month to develop and validate new manufacturing technologies before they are scaled for commercial production.

Once the pilot line shows signs of success, SpaceX is expected to construct a full-scale high-volume manufacturing fab. However, coordinating a joint project between Tesla and SpaceX will add complexity, as major decisions require approval from both companies' boards and must undergo conflict-of-interest reviews, which will likely slow execution.

That said, given that Gary Jiang was hired by Tesla, not SpaceX, his responsibilities could be to equip and ramp a development facility at its Gigafactory Texas campus rather than build, equip, and ramp a high-volume fab for SpaceX. In any case, we are speculating here, and nothing can really stop SpaceX from hiring Jiang at some point down the line.

South Korean President Lee Jae Myung on Monday, June 29, announced an 800 trillion won ($520 billion) public-private investment plan alongside Samsung Electronics and SK Hynix to expand the country's chipmaking capacity, a move the government framed as essential to keeping South Korea competitive in the global artificial intelligence race. Lee unveiled the plan in a televised state address at his office in Seoul, flanked by Samsung Electronics Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won, the leaders of the world's two largest memory chipmakers.

"Right now is truly a decisive moment, as the landscape of the global economy is being reshaped," Lee said in televised remarks. "Major countries, including the U.S. and China, are engaged in all-out competition with massive stakes." He added that only through cooperation between the private and public sectors could South Korea hope to triumph. Industry Minister Kim Jung-kwan said the plan would let the country rapidly expand production by sharply shortening the timeline from licensing to construction.

The centerpiece of the partnership is the construction of four production facilities, with Samsung and SK Hynix each building two. According to the government, the new plants will be built in the southwestern part of the country, near the city of Gwangju, a mostly rural area far from the existing semiconductor base south of Seoul, where both companies operate major clusters. Samsung will also build packaging facilities for high-bandwidth memory (HBM) chips in Chungcheong as demand for the advanced components soars.

"HBM, which is indispensable for the training and inference of AI models, requires cutting-edge technology for stacking semiconductor chips," the Samsung chairman said. "We will focus our investment on HBM fabs, which require main-fab-level processes, alongside existing semiconductor back-end fabs in the Chungcheong region, including Cheonan and Onyang."

One detail the government did not provide was the split between public and private money, as the project is a combined public-private commitment rather than a government spending program. While it is not immediately clear how much of the 800 trillion won would come from the state versus the two chipmakers, the disclosed line items are comparatively modest.

Industry Minister Kim Jung-kwan said the government and industry would jointly invest more than 30 trillion won over 15 years across the semiconductor value chain, while President Lee said Gwangju and South Jeolla province would contribute a further 5 trillion to 20 trillion won. Kim put another 81 trillion won toward the Chungcheong packaging hub, though he did not say how much of that is public.

The balance of the headline number is widely expected to be company capital expenditure, with the state's role concentrated in subsidies, faster permitting, and infrastructure. Kim said the government would streamline approvals and bring fab construction forward by up to 12 years, from the mid-2040s to the mid-2030s.

The plan also absorbs and accelerates projects already underway. The government said it would help Samsung and SK Hynix speed up construction of their existing capital-region clusters, with SK Group pulling forward the ramp of its Yongin memory site from 2045 to 2033, part of a stated goal to double the country's memory output within five years. SK Hynix supplies the bulk of the HBM that Nvidia depends on for its AI accelerators, the very strain this expansion is meant to relieve. While semiconductors are the focus of the investment, with the priority being a decisive lead in memory chips, the companies will also work on AI robots, physical AI, and AI data centers.

The investment partnership appears to be the latest piece of a broader strategy. SK Hynix had already committed $15 billion to new semiconductor facilities in February, a figure that now reads as an early piece of the larger national framework. Earlier iterations of the country's cluster plan had pegged long-term investment at around $471 billion, stretching to 2047, so the new figure represents a substantial expansion as AI demand projections have climbed. The fabs are targeted for completion in the mid-2030s.

The announcement caps an extraordinary stretch for both firms. SK Hynix overtook Samsung in June to become South Korea's most valuable listed company for the first time in more than 25 years, lifted by its commanding lead in HBM, while Samsung's chip division alone booked 53.7 trillion won in first-quarter operating profit as AI-driven memory shortages are expected to strain the companies' capacity past 2027.

The scale of the investments also invites inevitable comparison. At roughly $520 billion, South Korea’s plan dwarfs the United States' CHIPS Act, which provided about $52 billion in direct subsidies, by a factor of ten. Although the comparison is imperfect, since the U.S. figure is a government subsidy while the Korean number appears to be mostly private investment that the state is coordinating.

The strategic logic is the same on both sides of the Pacific: secure domestic capacity for the chips that underpin AI, at a moment when the U.S., China, Japan and the EU are all pursuing their own semiconductor industrial strategies. For Seoul, the specific prize is memory, the segment where its two companies already hold a commanding global position, with the goal being to extend that lead rather than merely defend it.

Imec's semiconductor process technology roadmap sets the general direction of industry development and showcases the challenges the sector is set to face over the next few decades. The roadmap gives us an idea of the timelines for the next major process nodes and transistor architectures the company will research and develop in cooperation with industry giants, such as TSMC, Intel, Nvidia, AMD, Samsung, and ASML, among many others.

Imec's latest production node roadmap shows that the international research and development organization envisions 3 angstrom-class (0.3nm) fabrication technologies by 2038, but expects contact poly pitch (CPP) to stop scaling at A10 in 2030. While things might not be looking great for Moore's Law for imec, to continue scaling the chipmaker will need to adopt new technologies, such as CFET transistors and likely Hyper-NA EUV Lithography systems.

GAA transistors have seven years left

As the production of semiconductors becomes substantially more complicated, chipmakers no longer introduce all-new process technologies every couple of years. Instead, they typically roll out a new node generation every three years, with annual incremental enhancements in between. TSMC ramped N3B production in 2023, then followed it up with N3E in 2024, and N3P in 2025. Intel planned to follow the same pattern with 20A in 2024 (which was canceled), 18A in 2025, and 18A-P in 2027.

Next-generation process technologies will continue to emerge at similar cadences, according to imec's roadmap.

Interuniversity Microelectronics Centre considers that we now live in the 2nm-class era (N2) with contact poly pitch (CPP) of around 48nm, as well as cell height of around 132nm and 6 metal tracks. The reality may be a bit different as Intel's 18A has a CPP of 50nm as well as a cell height of 160nm (high density) or 190nm (high performance), whereas TSMC's N3 can boast with a CPP of 45nm. N2 (or 18A, if you wish) will be followed by its performance and efficiency-enhanced version in the next couple of years, which is in line with how the industry has been operating in recent years.

"Of course, we are going to extend our logic roadmap to the next generation beyond N2," said Julien Ryckaert, vice president of R&D at imec. "As you know, in two nanometers we have already jumped into a new technology device paradigm in the nanosheet era, and that is going to bring us deep into the Angstrom node."

Imec expects the A14-class to emerge in 2028. TSMC expects to start high-volume manufacturing using A14 in late 2028, so the actual ramp will happen in 2029. Intel's 14A follows the same pattern. With A14, imec projects CPP to shrink to 45nm and cell height to drop to 115nm and 5.5 metal tracks. Around 2030–2031, imec expects an A10-class technology — or a 1nm-class — with a 42 nm CPP and 98 nm cell height, which will still rely on a 5.5-track architecture.

It is noteworthy that gate-all-around (GAA) transistor-based nodes can be implemented either with conventional frontside power delivery networks or with backside power delivery, which reflects both imec's and TSMC's belief that BSPDN will not immediately become mandatory across all applications, as many of them do not benefit from it.

It is also worth mentioning that imec expects High-NA EUV tools insertion at A14, which is in line with Intel's plans, but not with TSMC's plans.

CFET insertion in the early 2030s

The roadmap becomes particularly interesting at the A7 generation, which imec expects to come in 2033. While CPP remains at 42 nm, cell height drops to roughly 80nm, and the standard-cell architecture moves to 4.5 tracks. More importantly, A7 is the point where CFET emerges as a serious candidate for production insertion. Instead of placing n-type and p-type transistors side by side, CFET stacks them vertically, which adds a third dimension to transistor scaling.

Imec’s roadmap explicitly positions CFET as the leading contender for A7, which means that the organization sees conventional nanosheet architectures approaching practical scaling limits in the early 2030s. Yet, since A7's CPP does not change from A10, chipmakers may or may not adopt the all-new transistor architecture at A7. Also note that imec seems to consider BSPDN as mandatory for CFETs.

"Moving into A7, the seventh-angstrom generation, which is the fourth generation of nanosheet, we see more and more challenges in scaling the conventional nanosheet device technology," Ryckaert said. "There is a contender that we have already mentioned as well in previous presentations, where CFET could start emerging as the solution for the next era of transistors."

Beyond A7, the roadmap seems to depend on CFET evolution. The A5 generation, expected in 2035–2036, retains a 42nm CPP but reduces cell height to about 64nm using a 4-track library. By 2038, the roadmap reaches A3 with a 39nm CPP and 50nm cell height. At this point, imec envisions sequential CFET implementations and eventually bonded CFET structures that further exploit vertical integration. In fact, vertical integration seems to be the new way we should look at Moore's Law's evolution. Meanwhile, to get to a 39nm CPP and 50nm cell height, chipmakers might need to use Hyper-NA EUV lithography scanners, according to imec.

Redefining Moore's Law

The most interesting thing about imec's roadmap is that it essentially redefines what Moore's Law means. Traditionally, we consider Moore's Law as the observation that the number of transistors on a chip of a certain size doubles every 18 – 24 months, as they are getting smaller.

The fact that imec shows CPP stuck at 42 nm from A10 through A5 is almost an admission that classical transistor scaling is running out of steam, and future density gains must come from vertical integration. In the imec roadmap, transistors are still getting denser, but not exactly because individual transistors are shrinking at the same pace they used to decades ago, but because chip designers can fit more logic gates into a given area because of different transistor architectures, 3D integration, or backside power delivery.

As a result, in the coming years, we may no longer care how many nanometers a gate pitch is, or individual transistors, but rather the size of a standard cell. After all, when companies like AMD, Intel, or Nvidia design a chip, they do not place individual transistors, but actual blocks built from standard cells. Yet, calculating the size of a standard cell is complicated because while cell height is fixed, its width is not, and depends on the actual function.

Library height × CPP is not the size of a specific standard cell. It is the fundamental footprint unit of a standard-cell library and a widely used proxy for logic density. Actual standard cells have that height, but their width varies depending on function. Instead, the industry uses such metrics as logic cell area (standard-cell footprint) — Cell Height × CPP — that measures the actual footprint of the logic building blocks that designers use, not just the dimensions of individual transistors.

The transition from 6-track cells at N2 to 3-track cells at A3 illustrates how future density gains will rely as much on shrinking standard-cell height as on reducing transistor pitch. As a result, despite the fact that CPP shrinkage is expected to stall for years, logic cell area is set to decrease; designers will be able to extract transistor density gain from future nodes, proving that Moore's Law is still here.

Hetrogenous Large-Scale Integration × Cross-Technology Co-Optimization

Given all the changes that the semiconductor industry is already experiencing and what is set to come, imec believes the sector is entering a new era that it calls Heterogeneous Large-Scale Integration (HLSI). The concept reflects a shift away from traditional VLSI scaling, where progress largely depended on the evolution of transistors and increasing transistor density, toward a model that combines multiple technologies within a single compute platform.

Future systems will rely on heterogeneous integration of logic, memory, power-delivery circuitry, and optical I/O using advanced 3D and 3D + 2.5D packaging technologies, according to imec's predictions. Of course, the organization expects AI workloads to become the main driver of semiconductor demand, so expect both compute architectures and the semiconductor industry to evolve in a direction that satisfies the needs of AI applications.

"As we will move deeper into AI-driven architecture, we will need to double down on the heterogeneity that technology offers, and this will probably move the VLSI paradigm to the HLSI paradigm, the Heterogeneous Large Scale Integration," Ryckaert said.

To optimize future platforms on the system level rather than develop individual components in isolation, imec has established its Cross-Technology Co-Optimization (XTCO) framework, which could be seen as an integral part of the HLSI vision. XTCO is designed to wed development logic, memory, interconnects, power delivery, cooling, and packaging, and assesses their impact on key system metrics such as compute density, energy efficiency, thermal performance, and memory.

It remains to be seen how this is going to work out, if at all, given the fact that logic process technologies are developed at foundries, memory technologies are designed at DRAM makers, whereas cooling is developed at third parties like CoolIt or Frore Systems.

Power and cooling

As individual chips get denser and more power-hungry, power delivery is set to become a critical bottleneck, which is why all leading chipmakers — Intel, Samsung, and TSMC — are implementing or set to implement backside power delivery technologies and integrated voltage regulators.

Imec expects future AI accelerators and CPUs to rely on a combination of BSPDN, IVRs, embedded capacitors, and advanced power semiconductors to reduce losses and improve efficiency. Over time, more power-conversion stages are expected to migrate from racks and motherboards into packages themselves to deliver cleaner power directly to transistors.

Since we are talking about multi-chiplet packages consuming kilowatts of power, the importance of cooling is hard to overestimate. For sure, 3D stacking and CFETs will not make cooling any easier because thermal power density is set to increase linearly with the number of transistors, thermal resistance is set to increase, and local hotspots will become an even bigger problem than they are today. As a result, imec expects future compute platforms to rely on a combination of more advanced cooling technologies, improved heat spreading, fine-grained thermal sensors, and system-level thermal optimization techniques.

"At the end of the day, what we need to achieve is a reduced energy cost of data movement. We need to improve the TDP for better thermal management," Ryckaert said. "We need to improve the efficiency of the power delivery, and we need to obviously increase the compute density to improve the functionality."

In short, useful future scaling will depend not only on the ability to build transistors and increase their density, but on delivering power efficiently and removing heat effectively.

Paving the path forward

Imec's latest semiconductor roadmap projects logic process technologies all the way to A3 generation around 2038 and argues that Moore's Law can continue despite the slowing pace of traditional transistor scaling. While the Dennard scaling for semiconductors is over, there are plenty of interesting things incoming.

According to the roadmap, conventional gate-all-around nanosheet transistors should remain viable through A10, while CFET architectures become a candidate for production insertion at the A7 generation around 2033. Meanwhile, future transistor density gains are expected to come from vertical integration, reduced standard-cell footprints, and eventually sequential and bonded CFET structures rather than from aggressive shrinking of transistor dimensions.

IBM on Thursday said it has produced the first test chip using its 0.7nm-class (7 angstroms) fabrication technology, the industry's first sub-1nm manufacturing process. The concept process technology relies on the so-called nanostack transistors and promises rather dramatic power, performance, and area (PPA) gains compared to IBM's 2nm-class node. To produce nanostack transistors, IBM uses two wafers instead of one, along with ultra-thin dielectric bonding, an arrangement that has never been used before.

IBM's 7A-class (or 0.7nm-class) fabrication process based on nanostack transistors is said to offer up to 50% higher performance and 70% higher energy efficiency compared to IBM's 2nm-class node based on nanosheet gate-all-around transistors the company introduced in 2021. Perhaps more importantly, IBM's nanosheet architecture provides a 40% higher SRAM density and even higher density improvements for logic transistors, gains that are extremely hard to achieve these days.

Such massive gains have been enabled by numerous innovations, but the key enabler is IBM's nanostack transistor architecture, which conceptually resembles CFETs and stems from GAA nanosheet transistors.

Two wafers instead of one

In modern process technologies, all logic transistors live in one active device tier, and NFETs and PFETs sit side by side laterally in the standard-cell layout. Nanosheet GAA transistors feature a more advanced internal geometry, but they still reside in this single-transistor tier, which gets harder to shrink with every generation.

IBM's nanostack concept seems to separate complementary n-type and p-type transistors into vertically bonded tiers instead of placing them side by side in a single transistor layer. The payoff is a major reduction in the lateral footprint of a CMOS pair, as the architecture effectively turns one NFET+PFET structure from a 2D layout into a 3D stacked layout, which is why IBM can claim roughly double transistor density versus its 2nm research node without relying on conventional planar shrink.

While conceptually IBM's nanostack transistors resemble CFETs, the way IBM builds its nanostacks is fundamentally different compared to monolithic CFETs proposed by various chipmakers and organizations. N-type and p-type transistors are fundamentally the same kind of transistor used as complementary partners in CMOS logic, but they differ in carrier type (electrons for n-type and electron holes for p-type), switching polarity, and electrical behavior, which is why advanced process technologies tend to optimize them separately. However, these n-type and p-type transistors are made on the same wafer using essentially the same materials, so the level of their optimization is limited today.

Instead of building n-type and p-type transistors on the same wafer using the same materials, IBM builds them separately on different wafers and integrates them together using ultra-thin dielectric bonding in CMOS integration. This enables the company to optimize n and p-type channels independently, as each tier now can use different process conditions, different channel materials, different strain engineering, or even different geometries (though images from IBM indicate that the geometry of different transistors is the same).

As we see with all new process nodes, the nanometer-scale measurement doesn't coorelate to the physical dimensions of the device, but this remains a tremendous achievement.

Numerous caveats

Using two wafers for active transistor tiers instead of one could let IBM stack NFETs and PFETs vertically and optimize them independently, but such a method comes with a number of caveats that do not exist today with single-tier logic nodes.

The biggest issues are alignment and bonding yield, because two advanced logic wafers must line up with extreme precision, and any defect at the bond interface can kill the stack. Secondly, routing and power delivery could get more complex with two active device tiers. Thirdly, cooling gets harder now that one active tier sits farther from the heat sink. Last but not least are the costs. IBM has to pay for two advanced FEOL wafers, additional bonding and thinning steps, and manage higher process complexity and likely lower yields. As a result, the whole concept only makes sense if the density, SRAM, and performance-per-watt gains are large enough to offset manufacturing difficulties and cost penalty. IBM says nothing about costs and manufacturability, and the test chip it has completed is the size of a fingernail,' so not hard to make by today's standards. Meanwhile, it is highly likely that the approach only makes sense for heavy-duty data center AI solutions (which are near reticle size) and not for mainstream processors for client applications. For others, monolithic CFETs can do the job.

On the bright side, IBM's 7A-class fabrication process does not rely on High-NA EUV lithography, as there are simply no such tools at the semiconductor research facility in Albany, New York, where IBM develops its technologies. Usage of proven Low-NA EUV systems makes it easier to get high yields now. Meanwhile, it remains to be seen how IBM's dual wafer approach works with High-NA EUV scanners that have half the exposure field compared to Low-NA EUV machines and therefore require field stitching, which does not really help yields. IBM implies that its next-generation nodes will use High-NA EUV lithography, so the company probably has ideas how to wed these new tools with its approaches to transistor designs.

In production in the next five years

When dealing with IBM's manufacturing technologies, one has to keep in mind that these are not fabrication processes that can be licensed and rapidly deployed at a high-volume fab, but are essentially a set of pre-competitive IPs, patents, and some R&D know-how that can be used to design an actual production node. For example, Rapidus licensed IBM's 2nm-class process, though it has yet to prove that it can create a competitive high-volume node.

IBM believes nanostack could make sense for sub-1nm generations and potentially enter mass production within the next five years.

TSMC has reportedly told customers to prepare for price increases across its advanced chipmaking portfolio, extending the hikes beyond the newer 3nm process to include 7nm and even legacy products. According to a June 23rd Culpium report, the increases would affect the bulk of TSMC’s wafer revenue and could raise costs for major chip designers, including Apple, Nvidia, AMD, Qualcomm, Broadcom, and MediaTek.

The exact size of the increases remains unclear, as figures would reportedly vary by customer, node, and product category, but generally appear to fall in the 5% to 10% range. TSMC price increases have reportedly already started rolling out in some cases, while other customers have been told to build the higher cost structure into future purchase orders.

The company declined to discuss specific pricing with Culpium. “TSMC does not comment on pricing. Our pricing strategy is strategic, not opportunistic,” the company said in a statement to the publication. “We will continue to work closely with customers and sell our value to them.” Although the company had earlier said it would refrain from raising prices.

Earlier reports from Taiwanese media had mainly pointed to increases at TSMC’s 3nm node, one of its most advanced processes currently used for premium smartphones, PC, and AI chips, with price pressure also expected at the newest 2nm-class production. However, Culpium reports that TSMC has informed clients that “all advanced nodes” will become more expensive, meaning the hikes would extend beyond 3nm and 2nm to include older but still advanced processes such as 5nm and 7nm.

3nm alone accounted for 25% of TSMC’s wafer revenue in the first quarter of 2026, while the company’s full advanced-node portfolio — defined by TSMC as 7nm and more advanced technologies — accounted for 74% of wafer revenue. Therefore, the hikes would span nearly three-quarters of the company’s wafer business.

The inclusion of 7nm is especially notable because the node is no longer TSMC’s flagship technology. However, it's not exactly surprising as 7nm remains heavily used across processors, accelerators, networking silicon, and other high-performance chips. Many products remain on older, more advanced nodes because they offer better cost, yield, and maturity than the newest processes, especially when a design does not require the density or efficiency gains of 3nm or 2nm.

The client notices follow weeks of public comments from TSMC executives suggesting that higher prices were at least under consideration. At the company’s annual shareholders’ meeting in Hsinchu on June 4, CEO C.C. Wei said customers remained positive on the AI demand outlook, while also acknowledging cost pressures and the widening gap between chip demand and available manufacturing capacity. CFO Wendell Huang also said earlier that TSMC did not rule out price increases as inflation, overseas expansion, and advanced manufacturing costs continue to rise.

The timing of the price increases reflects TSMC’s strong negotiating position. The company remains the dominant manufacturer of leading-edge logic chips, and its most advanced capacity is in high demand among AI accelerator vendors, smartphone chip designers, and custom ASIC developers. With customers competing for access to the same manufacturing lines, TSMC has more room to pass on rising costs than it would in a weaker cycle.

The move also comes as TSMC benefits from a surge in AI-related demand. In its first-quarter results, the company reported $35.9 billion in revenue and a 66.2% gross margin, both supported by strong demand for high-performance computing and advanced-node production. TSMC has also raised its 2026 revenue growth target to more than 30%, with capital spending expected to remain elevated as the company expands capacity in Taiwan, the U.S., Japan, and Germany. The company’s Arizona manufacturing capacity has been sold out through 2027 since early 2025.

The reported increases are still far smaller than the recent price spikes seen in the memory market, where AI-driven demand for HBM and other high-end memory products has allowed suppliers to push through much steeper increases. Conversely, TSMC does not need memory-style pricing to meaningfully improve its margins. Because advanced nodes account for most of its wafer revenue, even a mid-single-digit increase across that base could add billions of dollars in annual revenue if demand remains strong.

For chip designers, the immediate impact is a higher manufacturing bill. For consumers, the effect is less direct but still important. A 5% to 10% wafer price increase does not automatically translate into a 5% to 10% increase in the price of a GPU, CPU, smartphone, or laptop, since the wafer is only one part of the final product cost. However, when combined with higher memory prices, packaging constraints, AI demand, and rising manufacturing costs, it creates another reason for device makers and component vendors to raise prices or protect margins by cutting costs elsewhere.

An interesting conversation on X has unearthed the existence of a rare ASML-focused Special Edition Monopoly board. Two chipmaking and engineering enthusiasts appear to have clinched a deal where one hands over an ASML Lego kit, a scale model of the world’s first High-NA EUV machine. In the no-cash deal, the other party will receive an ASML Special Edition Monopoly board. It appears that the deal is done, barring any regulatory hurdles and no one changing their minds, but it did pique our interest in the history of the board.

While we’ve seen and reported on the ASML chip tool Lego sets previously, this is the first time the firm’s special edition Monopoly set has blipped on our radar. It is possible this obscurity is due to this board game edition coming out way back in 2007, when the pioneering Dutch semiconductor company’s profile wasn’t quite as high as it is now. With the semiconductor segment becoming all the more important in recent years, driving the current AI boom, cutting-edge chip tool firms like ASML have risen to great prominence.

ASML’s special edition merchandise is also in high demand in the 2020s. Thankfully, we can learn a little more about the provenance of the headlining Monopoly board as it is featured in the board game’s Wiki. As previously mentioned, it was produced in 2007. Specifically, it was prepared for the Christmas period at the end of that year “as a gift to ASML employees and their families this holiday season.” From that ‘publisher’s description, it sounds like quite a few employees will have received one of these games, but it is still obviously an attractive collector’s item.

Sadly, the Wiki imagery doesn’t clearly show what the playing ‘tokens’ are (that’s Hasbro’s official term for the little metal playing pieces). The normal game has tokens like a boot, a dog, and a car, but we can’t quite make out the detail on this. Instead of streets and avenues, the ASML Monopoly board appears to have technologies and machines. Furthermore, the traditional stations are replaced by ASML campuses. Elsewhere on the board, special spaces include Corporate Tax and Press Release, where you must pick up a card. Regular Monopoly features such as Go, Water Works, Go To Jail, and the Electric Company remain.

Other non-consumer-facing semiconductor brands like TSMC and SK hynix have released successful sellout merchandise and memorabilia in recent years. Some items are easier for non-employees to get a hold of than others. For example, it is easy for anyone to find resellers of TSMC-related merchandise on Taiwan’s Shopee marketplace.

ASML has told Tom's Hardware that claims one of its extreme ultraviolet (EUV) lithography systems has ended up in China despite export restrictions is both inaccurate and damaging to its reputation. It follows a report that Commerce Secretary Howard Lutnick questions senior leadership, concerned that one of the machines had ended up in China in breach of export restrictions.

The company is refuting a recent report claiming the U.S. government believes that one of ASML's extreme ultraviolet (EUV) lithography systems may have somehow reached China despite export restrictions, according to Bloomberg, citing sources familiar with negotiations between the U.S. officials and ASML executives. ASML denies any wrongdoing and claims that it knows the location of every EUV tool it has ever built.

The issue reportedly emerged during meetings between U.S. Commerce Secretary Howard Lutnick and ASML executives. According to people familiar with the discussions cited by Bloomberg, Lutnick questioned whether an EUV system may have found its way into China. Such a development would represent a major breach of export controls because, under the Wassenaar Arrangement, ASML can not ship EUV lithography equipment to Chinese customers. In fact, the only EUV tool that China-based Semiconductor Manufacturing International Corp. (SMIC) has bought remains in the Netherlands. As a result, ASML calls the accusations 'unfounded' and 'damaging.'

"In recent years, ASML has refuted several unfounded rumors regarding non-compliance with export controls concerning China which were inaccurate and damaging to our reputation," a spokesperson for ASML told Tom's Hardware.

The U.S. government has not publicly produced evidence that a complete EUV scanner is operating in China. Yet, several senior administration officials told Bloomberg that they possess information indicating that ASML exported equipment associated with EUV systems, including specialized systems used to 'transport EUV machines.' Those officials declined to disclose any evidence, citing sensitivity concerns.

"ASML has never shipped an EUV machine to China, nor have we shipped to China any component, module or equipment specially designed to be used in an EUV machine," the spokesperson told us.

An ASML EUV scanner is made of 100,000 components and weighs 180 tons. It is transported only by air on multiple planes, and it would be impossible to intercept such a shipment without causing an international scandal. Meanwhile, given the complexity of the machine, it is impossible to build one using spare or scrap parts or reverse engineer it using its components, as we reported back in December.

Bloomberg claims that ASML has circulated an internal presentation titled 'No indication of any ASML EUV System in China,' which reportedly states there are 314 EUV systems currently operating worldwide and another 26 that have been retired. According to the document, none are located in China. The presentation further notes that EUV scanners continuously communicate with ASML, so the company can detect interruptions, abnormal activity, or connectivity issues. In addition, customers cannot simply dismantle, transport, and reinstall an EUV scanner without direct assistance from ASML due to specialized logistics and handling requirements.

ASML certainly understands concerns of the West regarding China, so claims it has never shipped an EUV tool to the People's Republic initially due to the Wassenaar Arrangement and then due to more recently imposed export controls.

"ASML regularly engages in transparent and open dialogue with government leaders globally," ASML told us. "We recognize the national security considerations behind export control regulations in the U.S. and the Netherlands. As a company, we are fully committed to abiding by all laws and regulations applicable to our business activities, including all applicable relevant export control regulations, and we have consistently adjusted our business to any development in export controls to comply to any new rules."

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer at a 50nm contacted poly pitch, the tightest pitch demonstrated to date for complementary 2D devices and one that lands within range of leading-edge silicon.

The trio presented the work this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, using a single EUV exposure to print channel lengths as short as 28nm. Imec reported that 94% of the integrated transistors switched correctly, with an on/off current ratio above 100,000. The n-channel devices use molybdenum disulfide (MoS₂), while the p-channel devices use tungsten diselenide (WSe₂) or tungsten disulfide (WS₂).

2D transition metal dichalcogenides have been studied for more than a decade — imec has been fabricating MoS₂ test transistors since the late 2010s — so while it’s not a new material breakthrough, the result is a solid milestone in terms of integration and scaling. What’s changed with this work is that both transistor polarities were built together on a standard 300mm process flow, rather than as isolated single devices patterned with coarser lithography.

The demonstrated transistors reached active widths down to 75nm and an equivalent oxide thickness near 2nm. Both polarities turned fully off at zero gate voltage, and imec said the WSe₂ p-channel devices performed close to the best lab-scale results reported so far, narrowing the gap on the historically weaker p-type side of 2D CMOS. For perspective on the pitch, 50nm is tighter than the 54nm contacted gate pitch of Intel's 10nm-class node.

Building the transistor upside down

Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, partly because the metal pins the semiconductor's Fermi level and raises the Schottky barrier that carriers must cross. Lab devices have compensated by keeping large contact areas, which in turn blocks the pitch scaling that makes the transistors worth pursuing in the first place.

To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.

"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.

EUV resolution, not High-NA

The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.

Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS₂. University groups have pushed monolayer MoS₂ transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.

2D channels

2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.

Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node, N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.

And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.

This roadmap provides an in-depth analysis of Intel's current plans for its chip production capacity. In the space of 12 months, Intel has gone from canceling fabs to running short of them. In July last year, the company scrapped a planned €30 billion megafab in Magdeburg, Germany, and a $4.6 billion assembly and test plant near Wroclaw, Poland, citing a lack of committed demand. Then, in April this year, it paid Apollo $14.2 billion to repurchase the 49% stake in its Ireland fab that it had sold for $11.2 billion in 2024. Three weeks later, CFO David Zinsner described "unprecedented demand for silicon" alongside Q1 results that sent the stock up 24% in a single session, its best day since October 1987.

The next round of capacity development now hinges on two key deadlines: CEO Lip-Bu Tan told investors in January that prospective 14A customers will begin to make firm supplier decisions "starting in the second half of this year and extending into the first half of 2027." Separately, the enhanced 35% advanced manufacturing investment credit signed into law last July applies only to fab construction that begins before December 31st, 2026; projects that break ground in 2027 get nothing.

Both clocks run out within months of each other, and both bear on the same construction projects.

Arizona

Fab 52 at the Ocotillo campus in Chandler is the production foundation for everything on Intel's 2026 to 2028 product roadmap. The facility became fully operational in October last year as the first high-volume home of Intel 18A, building Panther Lake compute tiles and, later this year, Clearwater Forest. Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is "capable of more than 10,000 18A wafer starts per week," which works out to roughly 40,000 wafer starts per month at full ramp and makes it larger than TSMC's Fab 21 phase 1 and phase 2 combined.

That’s named capacity, however, not current output; Intel has indicated that 18A yields will reach industry-standard levels in early 2027, and until then, the company is capping CPU output on the node, leaving part of Fab 52's capacity idle. Tan said in May that 18A yields are improving by 7% to 8% per month.

Fab 62, the second from Intel's $20 billion 2021 Arizona expansion, is expected to be ready around 2028. Intel hasn’t officially assigned it a node, leaving it open as a stopgap for 14A if Ohio isn't ready, or as additional 18A capacity if external demand comes sooner. Brookfield Infrastructure put up to $15 billion into the two Chandler fabs in 2022 for a 49% share of the joint venture, and unlike the Apollo arrangement, Intel has made no move to buy that stake back, so every wafer out of Fab 52 and Fab 62 will have revenue share commitments attached to it.

Oregon

As the home of 14A, D1X complex at Gordon Moore Park in Hillsboro — a low-volume fab and development site — is currently the only place Intel develops leading-edge process technology, with Chandrasekaran telling CNBC the node will be developed first in Oregon, with a goal of risk production in 2028 and high-volume manufacturing in 2029.

Hillsboro houses Intel's High-NA EUV machines, including the first ASML Twinscan EXE:5200B system delivered anywhere, and 14A is the first Intel node designed around it. Oregon also carried early 18A production while Arizona ramped up. Intel began permitting work in February 2024 for a multibillion-dollar expansion of the campus following the approval of an air quality permit, though no construction start has been announced to date.

Ohio One

Ohio is Intel’s most problematic fab project on paper. It broke ground in New Albany way back in 2022 on a $28 billion first phase, originally targeting 2025 production. In February 2025, however, Chandrasekaran reset its schedule, targeting 2030 for the completion of Mod 1 with operations between 2030 and 2031, and Mod 2 in 2031 with operations in 2032. In a memo setting out this new schedule, Chandrasekaran said Intel preserves “the flexibility to accelerate work and the start of operations if customer demand warrants.”

Spanning nearly 1,000 acres, the site is designated for 14A and future nodes, and has room for up to eight fabs. Intel has spent roughly $5 billion there to date as of March 2025, including $1.4 billion in total for that year. Bechtel, the lead contractor, posted a wave of new construction job listings in January, the same month Tan declared Intel is “going big time into 14A.”

Still, customers (or a lack thereof) remain the gating factor for 14A production. Intel told investors in January that it’s got two prospective customers evaluating 14A test chips, and its SEC filings still warn that without a significant external customer, it “may pause or discontinue” 14A, successor nodes, and various manufacturing expansion projects.

Elon Musk said in April that his planned TeraFab project — the first named taker for the node — will use 14A process technology to make AI chips, though test production is expected to be years out. This also isn’t such a big win in terms of the volume commitment Intel’s filings say it needs for 14A to be viable. At the time of writing, 14A’s next and arguably most critical milestone is the 14A v0.9 PDK, which Tan says will reach external customers in October.

"The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Ireland and canceled projects

Launched in 2023, Fab 34 in Leixlip is Intel's only EUV-class site in Europe, producing Intel 4 and Intel 3 silicon for Core Ultra and Xeon 6 parts. In 2024, Apollo-managed funds paid $11.2 billion for a 49% interest in the joint venture entitled to the fab's output, a deal that gave Intel a much-needed cash injection at the time.

In April this year, Intel bought that stake back for $14.2 billion — at a premium of roughly 27% — funded from cash and about $6.5 billion in new debt issuance. Apollo walked away with around $3 billion in return for two years of exposure, and Intel paid a nine-figure annual cost of capital to reclaim needed wafer revenue.

“Flexibility and alignment are core to how we approach relationships as a long-term, solutions-oriented capital partner, and we are pleased to facilitate this transaction in support of Intel's evolving strategic and operational priorities,” said Apollo Partner Jamshid Ehsani at the time.

Magdeburg, once pitched as a €30 billion home for 14A-era production with roughly €10 billion in German subsidies attached, was postponed to 2029-2030 in November 2024. This prompted the German government to reallocate those subsidies to the federal budget and, following a $3.2 billion operating loss with Q2 2025 financial results, Intel killed the project, the subsidies dying with it.

Wroclaw's $4.6 billion assembly and test plant was canceled the same day, and Costa Rica's assembly and test operations were consolidated into Vietnam and Malaysia. Fab 38 in Kiryat Gat, Israel, the planned $25 billion expansion announced in 2023 with $3.5 billion in Israeli government backing, has been paused for the last two years, with no restart announced. Every leading-edge wafer Intel produces for the foreseeable future will come therefore come from three U.S. states and one campus in Ireland.

Packaging and test

Fab 9 in Rio Rancho, New Mexico, a $3.5 billion conversion that opened in January 2024, is the only high-volume Foveros 3D stacking site in the United States. Foveros is the packaging behind every tiled Intel design since Meteor Lake, bonding compute, graphics, and I/O dies vertically rather than laying them side by side, and it is integral to the stacked Clearwater Forest parts now ramping on 18A.

Intel runs it alongside the neighboring Fab 11x as a single co-located operation, which EVP Keyvan Esfarjani called “the only U.S. factory producing the world's most advanced packaging solutions at scale.” The buildout created hundreds of Intel jobs and more than 3,000 construction roles, and the campus later drew a further $500 million in CHIPS funding for modernization.

The $7 billion Penang complex in Malaysia, placed on indefinite hold in early 2025, has been revived: the buildout is now 99% complete, and first-phase assembly and test operations are due to begin later this year, according to Malaysian Prime Minister Anwar Ibrahim, following an earlier briefing with Tan. Intel has also outsourced EMIB production to Amkor's Songdo facility in South Korea, and its next-generation EMIB-T packaging rolls out across production fabs this year.

With Magdeburg and the Penang delay having stripped packaging options elsewhere, Rio Rancho is now the load-bearing U.S. node for the back-end work that makes Intel's entire chip roadmap possible.

Two deadlines and three things to watch

Intel’s 14A commitment window and the cutoff for tax credits both converge in the second half of this year. Tan’s stated expectation is that customers make firm supplier decisions between the second half of 2026 and the first half of 2027, with results from the upcoming October PDK potentially being the trigger for those decisions.

On June 8th, Cadence announced a multi-year agreement with Intel Foundry to co-optimize designs for 14A and deliver production-ready process design kits. This is exactly the EDA groundwork that needs to be in place before any fabless customer can commit volume, and a committed volume customer will be what unlocks acceleration at Ohio and gives Fab 62 a job. The alternative, per Intel, is to cancel 14A altogether.

Unlike the customer deadline set by Intel, the tax deadline can’t slip. The so-called One Big Beautiful Bill Act raised the Section 48D advanced manufacturing investment credit from 25% to 35% in July last year, but the law's termination clause is unchanged: the credit doesn't apply to “property the construction of which begins after December 31, 2026.”

Treasury rules let a physical-work test or a 5% spend safe harbor establish a construction start, so Intel has roughly six months to break ground on any new shells, in Ohio, Arizona, or Oregon, that it wants the U.S. government to part-fund. The government, of course, has been a shareholder since August, when $5.7 billion in unpaid CHIPS grants from Intel's $7.86 billion award and $3.2 billion in Secure Enclave funds were converted into a 9.9% equity stake.

Ultimately, we’re going to be watching for three things before January: a named 14A customer with a volume commitment; a construction-start announcement timed to beat the credit deadline; and 18A yield milestones that free up the Arizona capacity Intel’s currently sitting on.

Following a paper published earlier this year, Intel has provided more details on its optimized 18A-P process at VLSI 2026. The performance-optimized node is an enhancement of 18A that Intel is using in products like Panther Lake and Xeon 6+, promising a 9% improvement in performance at the same power, or an 18% reduction in power consumption at the same performance level. In addition to greater technical detail, Intel has revealed that 18A-P has entered risk production.

If you’re unfamiliar with that term, it’s the stage of semiconductor manufacturing just before high-volume mass production. It’s a low-volume manufacturing stage where Intel will produce full wafers of 18A-P on a standard production line, just with a limited scope to gather data on defect rate, performance, and variability before full production begins. Risk production usually leads mass production on advanced logic by 12 to 24 months, though we’re not dealing with an entirely new node here, so expect a tighter timeline.

18A-P is a revision of 18A, and although it carries new transistor designs (more on those soon), they live in the same libraries at cell heights of 180mm (High Performance) and 160mm (High Density). The new process is backward compatible with 18A designs, meaning designers can port to 18A-P without making any changes. Some of the new transistor options could spur a design change, but it’s not required; anything built on 18A can be built on 18A-P with more minor performance benefits, but no design changes.

For performance, Intel arrived at its numbers by testing on a standard Arm core subblock, noting the 9% frequency increase or 18% reduction in power specifically at 0.75 volts. The chart you can see in the gallery below is a beautified version of a chart published in Intel’s original research; in other words, it’s not just random lines without any correlation. You can see that even as voltage moves outside that 0.75V mark, 18A-P retains a frequency/power improvement.

With 18A-P, Intel is adding three transistor designs to its library. The W1 design is available in the 180mm cell height library (it was previously available in the 160mm library), while W1.5 is available in the 160mm library. The enhanced W3P design is available in both libraries. W1 and W1.5 are both narrow designs optimized for low-power usage, helping fill gaps in power-optimized designs in Intel’s library, while W3P is a new dual-contact transistor with “Power Boost,” as Intel calls it. As you can see in the gallery below, the original W2 and W3 designs still see a boost in ring oscillator frequency (moving an electrical signal through a ring of inverters) with 18A-P.

W3P is the most interesting design due to Power Boost. 18A already uses backside power delivery with PowerVia, which uses the back of the wafer to route power, freeing up space for front side signal wiring and reducing thermal resistance. The W3P design has contacts on the front side and backside, reducing parasitic resistance and enabling higher drive current to speed up switching.

Although the standard W2 and W3 transistors will see a benefit moving from 18A to 18A-P, it’s minor. The biggest frequency improvement comes from W3P, while W1 pushes 18A-P down to lower capacitance levels for energy-optimized designs.

Intel is also adding a new VT (threshold voltage) pair to its lineup. Typically, we see four flavors of VT pairs: HVT, SVT, LVT, and ULVT, noting high, standard, low, and ultra-low threshold voltage, respectively. The lower the threshold voltage, the less power a transistor needs to activate, and therefore the more power it leaks. So, ULVT transistors are the most performant, but they leak the most power, while HVT transistors are the least performant but leak the least amount of power. Chip designers need to balance these different flavors of threshold voltage for their application.

The new VT pair adds another option: ULVTLL, or Ultra-Low Voltage Threshold Low Leakage. It lives between ULVT and LVT, offering better performance than LVT but lower leakage than ULVT. Like the new transistor design, it gives designers more flexibility when designing a chip for 18A-P.

In addition to the expanding 18A-P’s capabilities, Intel says the revision comes with a 20% to 40% improvement in thermal resistance, as well as a 10% to 30% improvement in via resistance at “perf critical layers.” The reduction in thermal resistance comes from grinding the wafer down with advanced EDA tools for better thermal conductivity.

Intel 18A is currently ramping in two U.S. fabs, and although the company has taken some heat for poor 18A yields, Intel says that defect rates continue to drop along with its expectations. 18A is being used already in Panther Lake and Xeon 6+, and Intel is reportedly in talks with Apple and Nvidia to build on 18A, as well.

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