Intel has resolved wafer-to-wafer yield variability issues with its 18A process technology, according to a report from BlueFin Research Partners. If the report coming from an unofficial source is accurate, then Intel can expect consistent and predictable yield improvements for its products made using the latest 1.8nm-class node from now on.

"Intel 18A wafer-to-wafer yield issue resolved; ramp to 12-15K wpm at both sites ongoing," BlueFin Research Partners wrote in a note to clients.

If the information is accurate, then products made using Intel's 18A process technology will no longer be plagued by wafer-to-wafer variability, an issue where good wafers and poor wafers are produced in the same production flow. However, wafer-to-wafer variability is only one contributor to yield loss, so fixing it means that Intel can now consistently improve product yields, but it does not necessarily mean overall yield is where Intel wants it to be.

Generally, a die yield defined by multiple factors, including defect density (which in turn is defined by random defects and systematic defects), within-wafer variability (differences between the center and edge of the same wafer when it comes to things like critical dimensions uniformity, line edge roughness, or stochastics; something that Intel has been improving recently), wafer-to-wafer variability (die yield and/or parametric yield differ from wafer to wafer), and packaging yield. When it comes to actual products, we should mention parametric yields (dies may be defect-free, but they do not meet performance and/or power specifications) as well as reliability screening (dies are functional and meet required specifications but fail burn-in tests).

That said, saying that Intel has 'fixed wafer-to-wafer yield issues' most likely means the process is now much more consistent from wafer to wafer, which clearly reduces lot-to-lot variation and makes production more predictable. However, it does not mean that defect density has reached target levels, parametric yield is optimal, and overall economic yield is where Intel wants it to be. What it does mean is that at a consistent yield improvement level (Intel once mentioned 7% per month for 18A), Intel is set to reach its target goals within a predictable timeframe.

In addition, the report claims that Intel now has capacity of around 30,000 wafer starts per month across its D1X development fab (presumably module 3) in Oregon and Fab 52 high-volume fab in Arizona (confirmed by @Alex_Intel_), which is a solid result at this point of the ramp cycle. However, without information about overall die yields and parametric yields of Intel's 18A products, it is hard to assess whether Intel can now produce enough Core Ultra 3 'Panther Lake' and Xeon 6+ 'Clearwater Forest' processors. Meanwhile, it should be noted that using a development facility for high-volume manufacturing (HVM) is costlier than using a fab that was designed to be an HVM fab from the start.

Meanwhile, it looks like Intel is set to continue such a practice with its next-generation 14A (1.4nm) fabrication process, according to BlueFin. The company plans to make 'D1X the initial HVM fab for 14A,' whereas the first phase of Intel's Ohio One semiconductor manufacturing site in Ohio will serve as the second HVM facility to make 14A chips, BlueFin claims. Intel recently confirmed that it intends to initiate high-volume production of chips using 14A in 2029. Ohio One first phase (Mod 1) is set to be completed in 2030, which means that it will come online 'between 2030 and 2031,' according to Intel.

Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.

Earlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.

Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial.

Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.

"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."

Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.

Tesla has hired Gary Jiang, an Intel veteran who most recently was responsible for installing equipment and transferring Intel's leading-edge 18A technology process from development fab in Oregon to the company's high-volume fab in Arizona, as spotted by Electrek.co. The appointment marks the first publicly identified senior leadership hire for Elon Musk's semiconductor production project, Terafab, which demonstrates Tesla's effort to build an experienced semiconductor manufacturing organization from the ground up by hiring veterans from other companies.

Tesla poaches an Intel veteran

Gary Jiang joined Tesla in June 2026 after spending over 17 years at Intel, according to his LinkedIn profile. Interestingly, there is little to glean about his current role from his LinkedIn profile, aside from noting that he is a director at Tesla. His final position at Intel was as Factory Manager, where he oversaw the construction of the production facility, the installation of fabrication equipment, factory startup, product certification, preparation for high-volume manufacturing, and, ultimately, the transfer of Intel 18A technology from the development fab in Oregon to high-volume Fab 52 in Arizona.

Earlier in his Intel career, Jiang held multiple management positions at the company's Ocotillo campus in Chandler, Arizona, where he managed technician teams accountable for startup, ramp, yield, and output for 22nm, 14nm, and 10nm-class process technologies (which include Intel 10nm SuperFin and 10nm Enhanced SuperFin/ Intel 7) at Fab 32 and Fab 42.

Tesla has been looking for a Technical Program Manager (TPM) for semiconductor infrastructure, focused on end-to-end fab program delivery, since March, but without any success, as the job listing is still listed on the company's website. Therefore, Terafab — the joint initiative between Tesla, SpaceX, and xAI — still does not have a formal leader who is going to lead the whole project.

In his most recent role at Intel, Gary Jiang worked closely with supply chain, finance, and materials logistics for new factory planning for output, wafer cost, yield, and profit & loss, according to his LinkedIn profile. He also managed the billion-dollar capital equipment and startup of the fab. Hence, without any doubt, Jiang appears to have been one of the senior manufacturing leaders responsible for building and equipping Intel's new 18A-capable manufacturing facilities in Arizona (primarily Fab 52, and potentially Fab 62 as the campus expands). However, it would still be inaccurate to say he was the person responsible for building Fab 52 alone.

Jiang's skills roughly match what one would expect from a senior manufacturing executive helping commission a new leading-edge fab, so he will be instrumental in turning a newly constructed fab shell (or even cleanroom) into a production-ready semiconductor manufacturing facility.

However, he did not oversee the entire Fab 52/Fab 62 program and was not responsible for every stage of the project — from permitting and groundbreaking to construction, tool installation, and the ramp to high-volume manufacturing. Likewise, he is unlikely to lead the Terafab project as a whole. Nonetheless, given that Terafab is set to license Intel's 14A process technology, Gary Jiang is probably among the best candidates to equip a fab for an Intel manufacturing node.

One major caveat

In fact, one of the most confusing parts about Tesla's hiring people to work at Terafab is that Tesla itself will not own any high-volume semiconductor production facilities; SpaceX will, according to Elon Musk.

In the near term, Tesla plans to build a $3 billion semiconductor R&D center at its Texas campus. The facility will house a small pilot line capable of processing a few thousand wafers per month to develop and validate new manufacturing technologies before they are scaled for commercial production.

Once the pilot line shows signs of success, SpaceX is expected to construct a full-scale high-volume manufacturing fab. However, coordinating a joint project between Tesla and SpaceX will add complexity, as major decisions require approval from both companies' boards and must undergo conflict-of-interest reviews, which will likely slow execution.

That said, given that Gary Jiang was hired by Tesla, not SpaceX, his responsibilities could be to equip and ramp a development facility at its Gigafactory Texas campus rather than build, equip, and ramp a high-volume fab for SpaceX. In any case, we are speculating here, and nothing can really stop SpaceX from hiring Jiang at some point down the line.

South Korean President Lee Jae Myung on Monday, June 29, announced an 800 trillion won ($520 billion) public-private investment plan alongside Samsung Electronics and SK Hynix to expand the country's chipmaking capacity, a move the government framed as essential to keeping South Korea competitive in the global artificial intelligence race. Lee unveiled the plan in a televised state address at his office in Seoul, flanked by Samsung Electronics Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won, the leaders of the world's two largest memory chipmakers.

"Right now is truly a decisive moment, as the landscape of the global economy is being reshaped," Lee said in televised remarks. "Major countries, including the U.S. and China, are engaged in all-out competition with massive stakes." He added that only through cooperation between the private and public sectors could South Korea hope to triumph. Industry Minister Kim Jung-kwan said the plan would let the country rapidly expand production by sharply shortening the timeline from licensing to construction.

The centerpiece of the partnership is the construction of four production facilities, with Samsung and SK Hynix each building two. According to the government, the new plants will be built in the southwestern part of the country, near the city of Gwangju, a mostly rural area far from the existing semiconductor base south of Seoul, where both companies operate major clusters. Samsung will also build packaging facilities for high-bandwidth memory (HBM) chips in Chungcheong as demand for the advanced components soars.

"HBM, which is indispensable for the training and inference of AI models, requires cutting-edge technology for stacking semiconductor chips," the Samsung chairman said. "We will focus our investment on HBM fabs, which require main-fab-level processes, alongside existing semiconductor back-end fabs in the Chungcheong region, including Cheonan and Onyang."

One detail the government did not provide was the split between public and private money, as the project is a combined public-private commitment rather than a government spending program. While it is not immediately clear how much of the 800 trillion won would come from the state versus the two chipmakers, the disclosed line items are comparatively modest.

Industry Minister Kim Jung-kwan said the government and industry would jointly invest more than 30 trillion won over 15 years across the semiconductor value chain, while President Lee said Gwangju and South Jeolla province would contribute a further 5 trillion to 20 trillion won. Kim put another 81 trillion won toward the Chungcheong packaging hub, though he did not say how much of that is public.

The balance of the headline number is widely expected to be company capital expenditure, with the state's role concentrated in subsidies, faster permitting, and infrastructure. Kim said the government would streamline approvals and bring fab construction forward by up to 12 years, from the mid-2040s to the mid-2030s.

The plan also absorbs and accelerates projects already underway. The government said it would help Samsung and SK Hynix speed up construction of their existing capital-region clusters, with SK Group pulling forward the ramp of its Yongin memory site from 2045 to 2033, part of a stated goal to double the country's memory output within five years. SK Hynix supplies the bulk of the HBM that Nvidia depends on for its AI accelerators, the very strain this expansion is meant to relieve. While semiconductors are the focus of the investment, with the priority being a decisive lead in memory chips, the companies will also work on AI robots, physical AI, and AI data centers.

The investment partnership appears to be the latest piece of a broader strategy. SK Hynix had already committed $15 billion to new semiconductor facilities in February, a figure that now reads as an early piece of the larger national framework. Earlier iterations of the country's cluster plan had pegged long-term investment at around $471 billion, stretching to 2047, so the new figure represents a substantial expansion as AI demand projections have climbed. The fabs are targeted for completion in the mid-2030s.

The announcement caps an extraordinary stretch for both firms. SK Hynix overtook Samsung in June to become South Korea's most valuable listed company for the first time in more than 25 years, lifted by its commanding lead in HBM, while Samsung's chip division alone booked 53.7 trillion won in first-quarter operating profit as AI-driven memory shortages are expected to strain the companies' capacity past 2027.

The scale of the investments also invites inevitable comparison. At roughly $520 billion, South Korea’s plan dwarfs the United States' CHIPS Act, which provided about $52 billion in direct subsidies, by a factor of ten. Although the comparison is imperfect, since the U.S. figure is a government subsidy while the Korean number appears to be mostly private investment that the state is coordinating.

The strategic logic is the same on both sides of the Pacific: secure domestic capacity for the chips that underpin AI, at a moment when the U.S., China, Japan and the EU are all pursuing their own semiconductor industrial strategies. For Seoul, the specific prize is memory, the segment where its two companies already hold a commanding global position, with the goal being to extend that lead rather than merely defend it.

Imec's semiconductor process technology roadmap sets the general direction of industry development and showcases the challenges the sector is set to face over the next few decades. The roadmap gives us an idea of the timelines for the next major process nodes and transistor architectures the company will research and develop in cooperation with industry giants, such as TSMC, Intel, Nvidia, AMD, Samsung, and ASML, among many others.

Imec's latest production node roadmap shows that the international research and development organization envisions 3 angstrom-class (0.3nm) fabrication technologies by 2038, but expects contact poly pitch (CPP) to stop scaling at A10 in 2030. While things might not be looking great for Moore's Law for imec, to continue scaling the chipmaker will need to adopt new technologies, such as CFET transistors and likely Hyper-NA EUV Lithography systems.

GAA transistors have seven years left

As the production of semiconductors becomes substantially more complicated, chipmakers no longer introduce all-new process technologies every couple of years. Instead, they typically roll out a new node generation every three years, with annual incremental enhancements in between. TSMC ramped N3B production in 2023, then followed it up with N3E in 2024, and N3P in 2025. Intel planned to follow the same pattern with 20A in 2024 (which was canceled), 18A in 2025, and 18A-P in 2027.

Next-generation process technologies will continue to emerge at similar cadences, according to imec's roadmap.

Interuniversity Microelectronics Centre considers that we now live in the 2nm-class era (N2) with contact poly pitch (CPP) of around 48nm, as well as cell height of around 132nm and 6 metal tracks. The reality may be a bit different as Intel's 18A has a CPP of 50nm as well as a cell height of 160nm (high density) or 190nm (high performance), whereas TSMC's N3 can boast with a CPP of 45nm. N2 (or 18A, if you wish) will be followed by its performance and efficiency-enhanced version in the next couple of years, which is in line with how the industry has been operating in recent years.

"Of course, we are going to extend our logic roadmap to the next generation beyond N2," said Julien Ryckaert, vice president of R&D at imec. "As you know, in two nanometers we have already jumped into a new technology device paradigm in the nanosheet era, and that is going to bring us deep into the Angstrom node."

Imec expects the A14-class to emerge in 2028. TSMC expects to start high-volume manufacturing using A14 in late 2028, so the actual ramp will happen in 2029. Intel's 14A follows the same pattern. With A14, imec projects CPP to shrink to 45nm and cell height to drop to 115nm and 5.5 metal tracks. Around 2030–2031, imec expects an A10-class technology — or a 1nm-class — with a 42 nm CPP and 98 nm cell height, which will still rely on a 5.5-track architecture.

It is noteworthy that gate-all-around (GAA) transistor-based nodes can be implemented either with conventional frontside power delivery networks or with backside power delivery, which reflects both imec's and TSMC's belief that BSPDN will not immediately become mandatory across all applications, as many of them do not benefit from it.

It is also worth mentioning that imec expects High-NA EUV tools insertion at A14, which is in line with Intel's plans, but not with TSMC's plans.

CFET insertion in the early 2030s

The roadmap becomes particularly interesting at the A7 generation, which imec expects to come in 2033. While CPP remains at 42 nm, cell height drops to roughly 80nm, and the standard-cell architecture moves to 4.5 tracks. More importantly, A7 is the point where CFET emerges as a serious candidate for production insertion. Instead of placing n-type and p-type transistors side by side, CFET stacks them vertically, which adds a third dimension to transistor scaling.

Imec’s roadmap explicitly positions CFET as the leading contender for A7, which means that the organization sees conventional nanosheet architectures approaching practical scaling limits in the early 2030s. Yet, since A7's CPP does not change from A10, chipmakers may or may not adopt the all-new transistor architecture at A7. Also note that imec seems to consider BSPDN as mandatory for CFETs.

"Moving into A7, the seventh-angstrom generation, which is the fourth generation of nanosheet, we see more and more challenges in scaling the conventional nanosheet device technology," Ryckaert said. "There is a contender that we have already mentioned as well in previous presentations, where CFET could start emerging as the solution for the next era of transistors."

Beyond A7, the roadmap seems to depend on CFET evolution. The A5 generation, expected in 2035–2036, retains a 42nm CPP but reduces cell height to about 64nm using a 4-track library. By 2038, the roadmap reaches A3 with a 39nm CPP and 50nm cell height. At this point, imec envisions sequential CFET implementations and eventually bonded CFET structures that further exploit vertical integration. In fact, vertical integration seems to be the new way we should look at Moore's Law's evolution. Meanwhile, to get to a 39nm CPP and 50nm cell height, chipmakers might need to use Hyper-NA EUV lithography scanners, according to imec.

Redefining Moore's Law

The most interesting thing about imec's roadmap is that it essentially redefines what Moore's Law means. Traditionally, we consider Moore's Law as the observation that the number of transistors on a chip of a certain size doubles every 18 – 24 months, as they are getting smaller.

The fact that imec shows CPP stuck at 42 nm from A10 through A5 is almost an admission that classical transistor scaling is running out of steam, and future density gains must come from vertical integration. In the imec roadmap, transistors are still getting denser, but not exactly because individual transistors are shrinking at the same pace they used to decades ago, but because chip designers can fit more logic gates into a given area because of different transistor architectures, 3D integration, or backside power delivery.

As a result, in the coming years, we may no longer care how many nanometers a gate pitch is, or individual transistors, but rather the size of a standard cell. After all, when companies like AMD, Intel, or Nvidia design a chip, they do not place individual transistors, but actual blocks built from standard cells. Yet, calculating the size of a standard cell is complicated because while cell height is fixed, its width is not, and depends on the actual function.

Library height × CPP is not the size of a specific standard cell. It is the fundamental footprint unit of a standard-cell library and a widely used proxy for logic density. Actual standard cells have that height, but their width varies depending on function. Instead, the industry uses such metrics as logic cell area (standard-cell footprint) — Cell Height × CPP — that measures the actual footprint of the logic building blocks that designers use, not just the dimensions of individual transistors.

The transition from 6-track cells at N2 to 3-track cells at A3 illustrates how future density gains will rely as much on shrinking standard-cell height as on reducing transistor pitch. As a result, despite the fact that CPP shrinkage is expected to stall for years, logic cell area is set to decrease; designers will be able to extract transistor density gain from future nodes, proving that Moore's Law is still here.

Hetrogenous Large-Scale Integration × Cross-Technology Co-Optimization

Given all the changes that the semiconductor industry is already experiencing and what is set to come, imec believes the sector is entering a new era that it calls Heterogeneous Large-Scale Integration (HLSI). The concept reflects a shift away from traditional VLSI scaling, where progress largely depended on the evolution of transistors and increasing transistor density, toward a model that combines multiple technologies within a single compute platform.

Future systems will rely on heterogeneous integration of logic, memory, power-delivery circuitry, and optical I/O using advanced 3D and 3D + 2.5D packaging technologies, according to imec's predictions. Of course, the organization expects AI workloads to become the main driver of semiconductor demand, so expect both compute architectures and the semiconductor industry to evolve in a direction that satisfies the needs of AI applications.

"As we will move deeper into AI-driven architecture, we will need to double down on the heterogeneity that technology offers, and this will probably move the VLSI paradigm to the HLSI paradigm, the Heterogeneous Large Scale Integration," Ryckaert said.

To optimize future platforms on the system level rather than develop individual components in isolation, imec has established its Cross-Technology Co-Optimization (XTCO) framework, which could be seen as an integral part of the HLSI vision. XTCO is designed to wed development logic, memory, interconnects, power delivery, cooling, and packaging, and assesses their impact on key system metrics such as compute density, energy efficiency, thermal performance, and memory.

It remains to be seen how this is going to work out, if at all, given the fact that logic process technologies are developed at foundries, memory technologies are designed at DRAM makers, whereas cooling is developed at third parties like CoolIt or Frore Systems.

Power and cooling

As individual chips get denser and more power-hungry, power delivery is set to become a critical bottleneck, which is why all leading chipmakers — Intel, Samsung, and TSMC — are implementing or set to implement backside power delivery technologies and integrated voltage regulators.

Imec expects future AI accelerators and CPUs to rely on a combination of BSPDN, IVRs, embedded capacitors, and advanced power semiconductors to reduce losses and improve efficiency. Over time, more power-conversion stages are expected to migrate from racks and motherboards into packages themselves to deliver cleaner power directly to transistors.

Since we are talking about multi-chiplet packages consuming kilowatts of power, the importance of cooling is hard to overestimate. For sure, 3D stacking and CFETs will not make cooling any easier because thermal power density is set to increase linearly with the number of transistors, thermal resistance is set to increase, and local hotspots will become an even bigger problem than they are today. As a result, imec expects future compute platforms to rely on a combination of more advanced cooling technologies, improved heat spreading, fine-grained thermal sensors, and system-level thermal optimization techniques.

"At the end of the day, what we need to achieve is a reduced energy cost of data movement. We need to improve the TDP for better thermal management," Ryckaert said. "We need to improve the efficiency of the power delivery, and we need to obviously increase the compute density to improve the functionality."

In short, useful future scaling will depend not only on the ability to build transistors and increase their density, but on delivering power efficiently and removing heat effectively.

Paving the path forward

Imec's latest semiconductor roadmap projects logic process technologies all the way to A3 generation around 2038 and argues that Moore's Law can continue despite the slowing pace of traditional transistor scaling. While the Dennard scaling for semiconductors is over, there are plenty of interesting things incoming.

According to the roadmap, conventional gate-all-around nanosheet transistors should remain viable through A10, while CFET architectures become a candidate for production insertion at the A7 generation around 2033. Meanwhile, future transistor density gains are expected to come from vertical integration, reduced standard-cell footprints, and eventually sequential and bonded CFET structures rather than from aggressive shrinking of transistor dimensions.

IBM on Thursday said it has produced the first test chip using its 0.7nm-class (7 angstroms) fabrication technology, the industry's first sub-1nm manufacturing process. The concept process technology relies on the so-called nanostack transistors and promises rather dramatic power, performance, and area (PPA) gains compared to IBM's 2nm-class node. To produce nanostack transistors, IBM uses two wafers instead of one, along with ultra-thin dielectric bonding, an arrangement that has never been used before.

IBM's 7A-class (or 0.7nm-class) fabrication process based on nanostack transistors is said to offer up to 50% higher performance and 70% higher energy efficiency compared to IBM's 2nm-class node based on nanosheet gate-all-around transistors the company introduced in 2021. Perhaps more importantly, IBM's nanosheet architecture provides a 40% higher SRAM density and even higher density improvements for logic transistors, gains that are extremely hard to achieve these days.

Such massive gains have been enabled by numerous innovations, but the key enabler is IBM's nanostack transistor architecture, which conceptually resembles CFETs and stems from GAA nanosheet transistors.

Two wafers instead of one

In modern process technologies, all logic transistors live in one active device tier, and NFETs and PFETs sit side by side laterally in the standard-cell layout. Nanosheet GAA transistors feature a more advanced internal geometry, but they still reside in this single-transistor tier, which gets harder to shrink with every generation.

IBM's nanostack concept seems to separate complementary n-type and p-type transistors into vertically bonded tiers instead of placing them side by side in a single transistor layer. The payoff is a major reduction in the lateral footprint of a CMOS pair, as the architecture effectively turns one NFET+PFET structure from a 2D layout into a 3D stacked layout, which is why IBM can claim roughly double transistor density versus its 2nm research node without relying on conventional planar shrink.

While conceptually IBM's nanostack transistors resemble CFETs, the way IBM builds its nanostacks is fundamentally different compared to monolithic CFETs proposed by various chipmakers and organizations. N-type and p-type transistors are fundamentally the same kind of transistor used as complementary partners in CMOS logic, but they differ in carrier type (electrons for n-type and electron holes for p-type), switching polarity, and electrical behavior, which is why advanced process technologies tend to optimize them separately. However, these n-type and p-type transistors are made on the same wafer using essentially the same materials, so the level of their optimization is limited today.

Instead of building n-type and p-type transistors on the same wafer using the same materials, IBM builds them separately on different wafers and integrates them together using ultra-thin dielectric bonding in CMOS integration. This enables the company to optimize n and p-type channels independently, as each tier now can use different process conditions, different channel materials, different strain engineering, or even different geometries (though images from IBM indicate that the geometry of different transistors is the same).

As we see with all new process nodes, the nanometer-scale measurement doesn't coorelate to the physical dimensions of the device, but this remains a tremendous achievement.

Numerous caveats

Using two wafers for active transistor tiers instead of one could let IBM stack NFETs and PFETs vertically and optimize them independently, but such a method comes with a number of caveats that do not exist today with single-tier logic nodes.

The biggest issues are alignment and bonding yield, because two advanced logic wafers must line up with extreme precision, and any defect at the bond interface can kill the stack. Secondly, routing and power delivery could get more complex with two active device tiers. Thirdly, cooling gets harder now that one active tier sits farther from the heat sink. Last but not least are the costs. IBM has to pay for two advanced FEOL wafers, additional bonding and thinning steps, and manage higher process complexity and likely lower yields. As a result, the whole concept only makes sense if the density, SRAM, and performance-per-watt gains are large enough to offset manufacturing difficulties and cost penalty. IBM says nothing about costs and manufacturability, and the test chip it has completed is the size of a fingernail,' so not hard to make by today's standards. Meanwhile, it is highly likely that the approach only makes sense for heavy-duty data center AI solutions (which are near reticle size) and not for mainstream processors for client applications. For others, monolithic CFETs can do the job.

On the bright side, IBM's 7A-class fabrication process does not rely on High-NA EUV lithography, as there are simply no such tools at the semiconductor research facility in Albany, New York, where IBM develops its technologies. Usage of proven Low-NA EUV systems makes it easier to get high yields now. Meanwhile, it remains to be seen how IBM's dual wafer approach works with High-NA EUV scanners that have half the exposure field compared to Low-NA EUV machines and therefore require field stitching, which does not really help yields. IBM implies that its next-generation nodes will use High-NA EUV lithography, so the company probably has ideas how to wed these new tools with its approaches to transistor designs.

In production in the next five years

When dealing with IBM's manufacturing technologies, one has to keep in mind that these are not fabrication processes that can be licensed and rapidly deployed at a high-volume fab, but are essentially a set of pre-competitive IPs, patents, and some R&D know-how that can be used to design an actual production node. For example, Rapidus licensed IBM's 2nm-class process, though it has yet to prove that it can create a competitive high-volume node.

IBM believes nanostack could make sense for sub-1nm generations and potentially enter mass production within the next five years.

TSMC has reportedly told customers to prepare for price increases across its advanced chipmaking portfolio, extending the hikes beyond the newer 3nm process to include 7nm and even legacy products. According to a June 23rd Culpium report, the increases would affect the bulk of TSMC’s wafer revenue and could raise costs for major chip designers, including Apple, Nvidia, AMD, Qualcomm, Broadcom, and MediaTek.

The exact size of the increases remains unclear, as figures would reportedly vary by customer, node, and product category, but generally appear to fall in the 5% to 10% range. TSMC price increases have reportedly already started rolling out in some cases, while other customers have been told to build the higher cost structure into future purchase orders.

The company declined to discuss specific pricing with Culpium. “TSMC does not comment on pricing. Our pricing strategy is strategic, not opportunistic,” the company said in a statement to the publication. “We will continue to work closely with customers and sell our value to them.” Although the company had earlier said it would refrain from raising prices.

Earlier reports from Taiwanese media had mainly pointed to increases at TSMC’s 3nm node, one of its most advanced processes currently used for premium smartphones, PC, and AI chips, with price pressure also expected at the newest 2nm-class production. However, Culpium reports that TSMC has informed clients that “all advanced nodes” will become more expensive, meaning the hikes would extend beyond 3nm and 2nm to include older but still advanced processes such as 5nm and 7nm.

3nm alone accounted for 25% of TSMC’s wafer revenue in the first quarter of 2026, while the company’s full advanced-node portfolio — defined by TSMC as 7nm and more advanced technologies — accounted for 74% of wafer revenue. Therefore, the hikes would span nearly three-quarters of the company’s wafer business.

The inclusion of 7nm is especially notable because the node is no longer TSMC’s flagship technology. However, it's not exactly surprising as 7nm remains heavily used across processors, accelerators, networking silicon, and other high-performance chips. Many products remain on older, more advanced nodes because they offer better cost, yield, and maturity than the newest processes, especially when a design does not require the density or efficiency gains of 3nm or 2nm.

The client notices follow weeks of public comments from TSMC executives suggesting that higher prices were at least under consideration. At the company’s annual shareholders’ meeting in Hsinchu on June 4, CEO C.C. Wei said customers remained positive on the AI demand outlook, while also acknowledging cost pressures and the widening gap between chip demand and available manufacturing capacity. CFO Wendell Huang also said earlier that TSMC did not rule out price increases as inflation, overseas expansion, and advanced manufacturing costs continue to rise.

The timing of the price increases reflects TSMC’s strong negotiating position. The company remains the dominant manufacturer of leading-edge logic chips, and its most advanced capacity is in high demand among AI accelerator vendors, smartphone chip designers, and custom ASIC developers. With customers competing for access to the same manufacturing lines, TSMC has more room to pass on rising costs than it would in a weaker cycle.

The move also comes as TSMC benefits from a surge in AI-related demand. In its first-quarter results, the company reported $35.9 billion in revenue and a 66.2% gross margin, both supported by strong demand for high-performance computing and advanced-node production. TSMC has also raised its 2026 revenue growth target to more than 30%, with capital spending expected to remain elevated as the company expands capacity in Taiwan, the U.S., Japan, and Germany. The company’s Arizona manufacturing capacity has been sold out through 2027 since early 2025.

The reported increases are still far smaller than the recent price spikes seen in the memory market, where AI-driven demand for HBM and other high-end memory products has allowed suppliers to push through much steeper increases. Conversely, TSMC does not need memory-style pricing to meaningfully improve its margins. Because advanced nodes account for most of its wafer revenue, even a mid-single-digit increase across that base could add billions of dollars in annual revenue if demand remains strong.

For chip designers, the immediate impact is a higher manufacturing bill. For consumers, the effect is less direct but still important. A 5% to 10% wafer price increase does not automatically translate into a 5% to 10% increase in the price of a GPU, CPU, smartphone, or laptop, since the wafer is only one part of the final product cost. However, when combined with higher memory prices, packaging constraints, AI demand, and rising manufacturing costs, it creates another reason for device makers and component vendors to raise prices or protect margins by cutting costs elsewhere.

An interesting conversation on X has unearthed the existence of a rare ASML-focused Special Edition Monopoly board. Two chipmaking and engineering enthusiasts appear to have clinched a deal where one hands over an ASML Lego kit, a scale model of the world’s first High-NA EUV machine. In the no-cash deal, the other party will receive an ASML Special Edition Monopoly board. It appears that the deal is done, barring any regulatory hurdles and no one changing their minds, but it did pique our interest in the history of the board.

While we’ve seen and reported on the ASML chip tool Lego sets previously, this is the first time the firm’s special edition Monopoly set has blipped on our radar. It is possible this obscurity is due to this board game edition coming out way back in 2007, when the pioneering Dutch semiconductor company’s profile wasn’t quite as high as it is now. With the semiconductor segment becoming all the more important in recent years, driving the current AI boom, cutting-edge chip tool firms like ASML have risen to great prominence.

ASML’s special edition merchandise is also in high demand in the 2020s. Thankfully, we can learn a little more about the provenance of the headlining Monopoly board as it is featured in the board game’s Wiki. As previously mentioned, it was produced in 2007. Specifically, it was prepared for the Christmas period at the end of that year “as a gift to ASML employees and their families this holiday season.” From that ‘publisher’s description, it sounds like quite a few employees will have received one of these games, but it is still obviously an attractive collector’s item.

Sadly, the Wiki imagery doesn’t clearly show what the playing ‘tokens’ are (that’s Hasbro’s official term for the little metal playing pieces). The normal game has tokens like a boot, a dog, and a car, but we can’t quite make out the detail on this. Instead of streets and avenues, the ASML Monopoly board appears to have technologies and machines. Furthermore, the traditional stations are replaced by ASML campuses. Elsewhere on the board, special spaces include Corporate Tax and Press Release, where you must pick up a card. Regular Monopoly features such as Go, Water Works, Go To Jail, and the Electric Company remain.

Other non-consumer-facing semiconductor brands like TSMC and SK hynix have released successful sellout merchandise and memorabilia in recent years. Some items are easier for non-employees to get a hold of than others. For example, it is easy for anyone to find resellers of TSMC-related merchandise on Taiwan’s Shopee marketplace.

ASML has told Tom's Hardware that claims one of its extreme ultraviolet (EUV) lithography systems has ended up in China despite export restrictions is both inaccurate and damaging to its reputation. It follows a report that Commerce Secretary Howard Lutnick questions senior leadership, concerned that one of the machines had ended up in China in breach of export restrictions.

The company is refuting a recent report claiming the U.S. government believes that one of ASML's extreme ultraviolet (EUV) lithography systems may have somehow reached China despite export restrictions, according to Bloomberg, citing sources familiar with negotiations between the U.S. officials and ASML executives. ASML denies any wrongdoing and claims that it knows the location of every EUV tool it has ever built.

The issue reportedly emerged during meetings between U.S. Commerce Secretary Howard Lutnick and ASML executives. According to people familiar with the discussions cited by Bloomberg, Lutnick questioned whether an EUV system may have found its way into China. Such a development would represent a major breach of export controls because, under the Wassenaar Arrangement, ASML can not ship EUV lithography equipment to Chinese customers. In fact, the only EUV tool that China-based Semiconductor Manufacturing International Corp. (SMIC) has bought remains in the Netherlands. As a result, ASML calls the accusations 'unfounded' and 'damaging.'

"In recent years, ASML has refuted several unfounded rumors regarding non-compliance with export controls concerning China which were inaccurate and damaging to our reputation," a spokesperson for ASML told Tom's Hardware.

The U.S. government has not publicly produced evidence that a complete EUV scanner is operating in China. Yet, several senior administration officials told Bloomberg that they possess information indicating that ASML exported equipment associated with EUV systems, including specialized systems used to 'transport EUV machines.' Those officials declined to disclose any evidence, citing sensitivity concerns.

"ASML has never shipped an EUV machine to China, nor have we shipped to China any component, module or equipment specially designed to be used in an EUV machine," the spokesperson told us.

An ASML EUV scanner is made of 100,000 components and weighs 180 tons. It is transported only by air on multiple planes, and it would be impossible to intercept such a shipment without causing an international scandal. Meanwhile, given the complexity of the machine, it is impossible to build one using spare or scrap parts or reverse engineer it using its components, as we reported back in December.

Bloomberg claims that ASML has circulated an internal presentation titled 'No indication of any ASML EUV System in China,' which reportedly states there are 314 EUV systems currently operating worldwide and another 26 that have been retired. According to the document, none are located in China. The presentation further notes that EUV scanners continuously communicate with ASML, so the company can detect interruptions, abnormal activity, or connectivity issues. In addition, customers cannot simply dismantle, transport, and reinstall an EUV scanner without direct assistance from ASML due to specialized logistics and handling requirements.

ASML certainly understands concerns of the West regarding China, so claims it has never shipped an EUV tool to the People's Republic initially due to the Wassenaar Arrangement and then due to more recently imposed export controls.

"ASML regularly engages in transparent and open dialogue with government leaders globally," ASML told us. "We recognize the national security considerations behind export control regulations in the U.S. and the Netherlands. As a company, we are fully committed to abiding by all laws and regulations applicable to our business activities, including all applicable relevant export control regulations, and we have consistently adjusted our business to any development in export controls to comply to any new rules."

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer at a 50nm contacted poly pitch, the tightest pitch demonstrated to date for complementary 2D devices and one that lands within range of leading-edge silicon.

The trio presented the work this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, using a single EUV exposure to print channel lengths as short as 28nm. Imec reported that 94% of the integrated transistors switched correctly, with an on/off current ratio above 100,000. The n-channel devices use molybdenum disulfide (MoS₂), while the p-channel devices use tungsten diselenide (WSe₂) or tungsten disulfide (WS₂).

2D transition metal dichalcogenides have been studied for more than a decade — imec has been fabricating MoS₂ test transistors since the late 2010s — so while it’s not a new material breakthrough, the result is a solid milestone in terms of integration and scaling. What’s changed with this work is that both transistor polarities were built together on a standard 300mm process flow, rather than as isolated single devices patterned with coarser lithography.

The demonstrated transistors reached active widths down to 75nm and an equivalent oxide thickness near 2nm. Both polarities turned fully off at zero gate voltage, and imec said the WSe₂ p-channel devices performed close to the best lab-scale results reported so far, narrowing the gap on the historically weaker p-type side of 2D CMOS. For perspective on the pitch, 50nm is tighter than the 54nm contacted gate pitch of Intel's 10nm-class node.

Building the transistor upside down

Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, partly because the metal pins the semiconductor's Fermi level and raises the Schottky barrier that carriers must cross. Lab devices have compensated by keeping large contact areas, which in turn blocks the pitch scaling that makes the transistors worth pursuing in the first place.

To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.

"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.

EUV resolution, not High-NA

The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.

Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS₂. University groups have pushed monolayer MoS₂ transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.

2D channels

2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.

Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node, N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.

And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.

This roadmap provides an in-depth analysis of Intel's current plans for its chip production capacity. In the space of 12 months, Intel has gone from canceling fabs to running short of them. In July last year, the company scrapped a planned €30 billion megafab in Magdeburg, Germany, and a $4.6 billion assembly and test plant near Wroclaw, Poland, citing a lack of committed demand. Then, in April this year, it paid Apollo $14.2 billion to repurchase the 49% stake in its Ireland fab that it had sold for $11.2 billion in 2024. Three weeks later, CFO David Zinsner described "unprecedented demand for silicon" alongside Q1 results that sent the stock up 24% in a single session, its best day since October 1987.

The next round of capacity development now hinges on two key deadlines: CEO Lip-Bu Tan told investors in January that prospective 14A customers will begin to make firm supplier decisions "starting in the second half of this year and extending into the first half of 2027." Separately, the enhanced 35% advanced manufacturing investment credit signed into law last July applies only to fab construction that begins before December 31st, 2026; projects that break ground in 2027 get nothing.

Both clocks run out within months of each other, and both bear on the same construction projects.

Arizona

Fab 52 at the Ocotillo campus in Chandler is the production foundation for everything on Intel's 2026 to 2028 product roadmap. The facility became fully operational in October last year as the first high-volume home of Intel 18A, building Panther Lake compute tiles and, later this year, Clearwater Forest. Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is "capable of more than 10,000 18A wafer starts per week," which works out to roughly 40,000 wafer starts per month at full ramp and makes it larger than TSMC's Fab 21 phase 1 and phase 2 combined.

That’s named capacity, however, not current output; Intel has indicated that 18A yields will reach industry-standard levels in early 2027, and until then, the company is capping CPU output on the node, leaving part of Fab 52's capacity idle. Tan said in May that 18A yields are improving by 7% to 8% per month.

Fab 62, the second from Intel's $20 billion 2021 Arizona expansion, is expected to be ready around 2028. Intel hasn’t officially assigned it a node, leaving it open as a stopgap for 14A if Ohio isn't ready, or as additional 18A capacity if external demand comes sooner. Brookfield Infrastructure put up to $15 billion into the two Chandler fabs in 2022 for a 49% share of the joint venture, and unlike the Apollo arrangement, Intel has made no move to buy that stake back, so every wafer out of Fab 52 and Fab 62 will have revenue share commitments attached to it.

Oregon

As the home of 14A, D1X complex at Gordon Moore Park in Hillsboro — a low-volume fab and development site — is currently the only place Intel develops leading-edge process technology, with Chandrasekaran telling CNBC the node will be developed first in Oregon, with a goal of risk production in 2028 and high-volume manufacturing in 2029.

Hillsboro houses Intel's High-NA EUV machines, including the first ASML Twinscan EXE:5200B system delivered anywhere, and 14A is the first Intel node designed around it. Oregon also carried early 18A production while Arizona ramped up. Intel began permitting work in February 2024 for a multibillion-dollar expansion of the campus following the approval of an air quality permit, though no construction start has been announced to date.

Ohio One

Ohio is Intel’s most problematic fab project on paper. It broke ground in New Albany way back in 2022 on a $28 billion first phase, originally targeting 2025 production. In February 2025, however, Chandrasekaran reset its schedule, targeting 2030 for the completion of Mod 1 with operations between 2030 and 2031, and Mod 2 in 2031 with operations in 2032. In a memo setting out this new schedule, Chandrasekaran said Intel preserves “the flexibility to accelerate work and the start of operations if customer demand warrants.”

Spanning nearly 1,000 acres, the site is designated for 14A and future nodes, and has room for up to eight fabs. Intel has spent roughly $5 billion there to date as of March 2025, including $1.4 billion in total for that year. Bechtel, the lead contractor, posted a wave of new construction job listings in January, the same month Tan declared Intel is “going big time into 14A.”

Still, customers (or a lack thereof) remain the gating factor for 14A production. Intel told investors in January that it’s got two prospective customers evaluating 14A test chips, and its SEC filings still warn that without a significant external customer, it “may pause or discontinue” 14A, successor nodes, and various manufacturing expansion projects.

Elon Musk said in April that his planned TeraFab project — the first named taker for the node — will use 14A process technology to make AI chips, though test production is expected to be years out. This also isn’t such a big win in terms of the volume commitment Intel’s filings say it needs for 14A to be viable. At the time of writing, 14A’s next and arguably most critical milestone is the 14A v0.9 PDK, which Tan says will reach external customers in October.

"The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Ireland and canceled projects

Launched in 2023, Fab 34 in Leixlip is Intel's only EUV-class site in Europe, producing Intel 4 and Intel 3 silicon for Core Ultra and Xeon 6 parts. In 2024, Apollo-managed funds paid $11.2 billion for a 49% interest in the joint venture entitled to the fab's output, a deal that gave Intel a much-needed cash injection at the time.

In April this year, Intel bought that stake back for $14.2 billion — at a premium of roughly 27% — funded from cash and about $6.5 billion in new debt issuance. Apollo walked away with around $3 billion in return for two years of exposure, and Intel paid a nine-figure annual cost of capital to reclaim needed wafer revenue.

“Flexibility and alignment are core to how we approach relationships as a long-term, solutions-oriented capital partner, and we are pleased to facilitate this transaction in support of Intel's evolving strategic and operational priorities,” said Apollo Partner Jamshid Ehsani at the time.

Magdeburg, once pitched as a €30 billion home for 14A-era production with roughly €10 billion in German subsidies attached, was postponed to 2029-2030 in November 2024. This prompted the German government to reallocate those subsidies to the federal budget and, following a $3.2 billion operating loss with Q2 2025 financial results, Intel killed the project, the subsidies dying with it.

Wroclaw's $4.6 billion assembly and test plant was canceled the same day, and Costa Rica's assembly and test operations were consolidated into Vietnam and Malaysia. Fab 38 in Kiryat Gat, Israel, the planned $25 billion expansion announced in 2023 with $3.5 billion in Israeli government backing, has been paused for the last two years, with no restart announced. Every leading-edge wafer Intel produces for the foreseeable future will come therefore come from three U.S. states and one campus in Ireland.

Packaging and test

Fab 9 in Rio Rancho, New Mexico, a $3.5 billion conversion that opened in January 2024, is the only high-volume Foveros 3D stacking site in the United States. Foveros is the packaging behind every tiled Intel design since Meteor Lake, bonding compute, graphics, and I/O dies vertically rather than laying them side by side, and it is integral to the stacked Clearwater Forest parts now ramping on 18A.

Intel runs it alongside the neighboring Fab 11x as a single co-located operation, which EVP Keyvan Esfarjani called “the only U.S. factory producing the world's most advanced packaging solutions at scale.” The buildout created hundreds of Intel jobs and more than 3,000 construction roles, and the campus later drew a further $500 million in CHIPS funding for modernization.

The $7 billion Penang complex in Malaysia, placed on indefinite hold in early 2025, has been revived: the buildout is now 99% complete, and first-phase assembly and test operations are due to begin later this year, according to Malaysian Prime Minister Anwar Ibrahim, following an earlier briefing with Tan. Intel has also outsourced EMIB production to Amkor's Songdo facility in South Korea, and its next-generation EMIB-T packaging rolls out across production fabs this year.

With Magdeburg and the Penang delay having stripped packaging options elsewhere, Rio Rancho is now the load-bearing U.S. node for the back-end work that makes Intel's entire chip roadmap possible.

Two deadlines and three things to watch

Intel’s 14A commitment window and the cutoff for tax credits both converge in the second half of this year. Tan’s stated expectation is that customers make firm supplier decisions between the second half of 2026 and the first half of 2027, with results from the upcoming October PDK potentially being the trigger for those decisions.

On June 8th, Cadence announced a multi-year agreement with Intel Foundry to co-optimize designs for 14A and deliver production-ready process design kits. This is exactly the EDA groundwork that needs to be in place before any fabless customer can commit volume, and a committed volume customer will be what unlocks acceleration at Ohio and gives Fab 62 a job. The alternative, per Intel, is to cancel 14A altogether.

Unlike the customer deadline set by Intel, the tax deadline can’t slip. The so-called One Big Beautiful Bill Act raised the Section 48D advanced manufacturing investment credit from 25% to 35% in July last year, but the law's termination clause is unchanged: the credit doesn't apply to “property the construction of which begins after December 31, 2026.”

Treasury rules let a physical-work test or a 5% spend safe harbor establish a construction start, so Intel has roughly six months to break ground on any new shells, in Ohio, Arizona, or Oregon, that it wants the U.S. government to part-fund. The government, of course, has been a shareholder since August, when $5.7 billion in unpaid CHIPS grants from Intel's $7.86 billion award and $3.2 billion in Secure Enclave funds were converted into a 9.9% equity stake.

Ultimately, we’re going to be watching for three things before January: a named 14A customer with a volume commitment; a construction-start announcement timed to beat the credit deadline; and 18A yield milestones that free up the Arizona capacity Intel’s currently sitting on.

Following a paper published earlier this year, Intel has provided more details on its optimized 18A-P process at VLSI 2026. The performance-optimized node is an enhancement of 18A that Intel is using in products like Panther Lake and Xeon 6+, promising a 9% improvement in performance at the same power, or an 18% reduction in power consumption at the same performance level. In addition to greater technical detail, Intel has revealed that 18A-P has entered risk production.

If you’re unfamiliar with that term, it’s the stage of semiconductor manufacturing just before high-volume mass production. It’s a low-volume manufacturing stage where Intel will produce full wafers of 18A-P on a standard production line, just with a limited scope to gather data on defect rate, performance, and variability before full production begins. Risk production usually leads mass production on advanced logic by 12 to 24 months, though we’re not dealing with an entirely new node here, so expect a tighter timeline.

18A-P is a revision of 18A, and although it carries new transistor designs (more on those soon), they live in the same libraries at cell heights of 180mm (High Performance) and 160mm (High Density). The new process is backward compatible with 18A designs, meaning designers can port to 18A-P without making any changes. Some of the new transistor options could spur a design change, but it’s not required; anything built on 18A can be built on 18A-P with more minor performance benefits, but no design changes.

For performance, Intel arrived at its numbers by testing on a standard Arm core subblock, noting the 9% frequency increase or 18% reduction in power specifically at 0.75 volts. The chart you can see in the gallery below is a beautified version of a chart published in Intel’s original research; in other words, it’s not just random lines without any correlation. You can see that even as voltage moves outside that 0.75V mark, 18A-P retains a frequency/power improvement.

With 18A-P, Intel is adding three transistor designs to its library. The W1 design is available in the 180mm cell height library (it was previously available in the 160mm library), while W1.5 is available in the 160mm library. The enhanced W3P design is available in both libraries. W1 and W1.5 are both narrow designs optimized for low-power usage, helping fill gaps in power-optimized designs in Intel’s library, while W3P is a new dual-contact transistor with “Power Boost,” as Intel calls it. As you can see in the gallery below, the original W2 and W3 designs still see a boost in ring oscillator frequency (moving an electrical signal through a ring of inverters) with 18A-P.

W3P is the most interesting design due to Power Boost. 18A already uses backside power delivery with PowerVia, which uses the back of the wafer to route power, freeing up space for front side signal wiring and reducing thermal resistance. The W3P design has contacts on the front side and backside, reducing parasitic resistance and enabling higher drive current to speed up switching.

Although the standard W2 and W3 transistors will see a benefit moving from 18A to 18A-P, it’s minor. The biggest frequency improvement comes from W3P, while W1 pushes 18A-P down to lower capacitance levels for energy-optimized designs.

Intel is also adding a new VT (threshold voltage) pair to its lineup. Typically, we see four flavors of VT pairs: HVT, SVT, LVT, and ULVT, noting high, standard, low, and ultra-low threshold voltage, respectively. The lower the threshold voltage, the less power a transistor needs to activate, and therefore the more power it leaks. So, ULVT transistors are the most performant, but they leak the most power, while HVT transistors are the least performant but leak the least amount of power. Chip designers need to balance these different flavors of threshold voltage for their application.

The new VT pair adds another option: ULVTLL, or Ultra-Low Voltage Threshold Low Leakage. It lives between ULVT and LVT, offering better performance than LVT but lower leakage than ULVT. Like the new transistor design, it gives designers more flexibility when designing a chip for 18A-P.

In addition to the expanding 18A-P’s capabilities, Intel says the revision comes with a 20% to 40% improvement in thermal resistance, as well as a 10% to 30% improvement in via resistance at “perf critical layers.” The reduction in thermal resistance comes from grinding the wafer down with advanced EDA tools for better thermal conductivity.

Intel 18A is currently ramping in two U.S. fabs, and although the company has taken some heat for poor 18A yields, Intel says that defect rates continue to drop along with its expectations. 18A is being used already in Panther Lake and Xeon 6+, and Intel is reportedly in talks with Apple and Nvidia to build on 18A, as well.

Full presentation

SemiAnalysis has published the first teardown from its new in-house lab, focusing on the minimum local metal pitch on SMIC’s third-gen 7nm at 32.5nm, tighter than the 36nm pitch shipping in Intel’s Panther Lake chips on 18A. The analysis was conducted on a HiSilicon Kirin 9030, the processor found inside Huawei’s Mate 80 phones and built on the N+3 process, which SemiAnalysis says trails Intel’s 18A high-density library by 38%. The SemiAnalysis Teardown Engineering & Evaluation Lab (STEEL) has been opened in Hillsboro, Oregon, and built to take on TechInsights in advanced-node reverse engineering.

A 36nm pitch is what Panther Lake ships with, but the 18A process on the whole supports a 32nm minimum metal pitch. With Panter Lake, Intel opted to relax the pitch because routing power through the back of the wafer — via PowerVia — clears the front-side metal stack for signal wiring.

Intel has said doing this buys roughly 10% higher density and looser front-side pitches, which is how a node built on GAA RibbonFET transistors and backside power can ship a wider local pitch than a DUV Chinese process and maintain a wide overall lead. SMIC reached 32.5nm without EUV lithography, leaning on DUV tools and quadruple-patterning that needs extra masking and etch passes.

Counting transistors per area, SemiAnalysis put N+3 at 113.4 million per square millimeter, just ahead of TSMC's mature N6 at 107.7 million and well behind 18A. SMIC got there by spending every density trick available without EUV: two fins per transistor, contacts landed directly over the active gate, and single diffusion breaks between cells.

Each of those workarounds obviously adds complexity and cost, with N+3’s ceiling ultimately showing a huge trade-off. The Kirin 9030 Pro's prime core runs at 2.75 GHz and lands near Arm's 2021-era Cortex-X2 per clock, leaving the chip roughly level with Android flagships from three years ago and behind current parts from Apple, Qualcomm, MediaTek, and Samsung. Huawei’s roadmap does say that it’s targeting 5 GHz by 2031, but, as SemiAnalysis notes, that’s “far beyond what planar scaling alone could deliver.”

SemiAnalysis said it spent the past 18 months building the lab and has already earned revenue analyzing datacenter silicon. “We have already generated revenue on advanced datacenter chip teardowns, including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack.”

The company is taking aim at the Ottawa-based TechInsights, which is backed by private equity and held by the likes of Oakley Capital and CVC Growth. SemiAnalysis claims its rival is up for sale and has underinvested in equipment as a result, though that hasn’t been officially confirmed. The teardown also found the Kirin 9030 Pro carrying Samsung LPDDR5X memory, with 16 GB variants turning up DRAM from Chinese maker CXMT as well.

The race is on to build the massive chip packages that power the future of AI, with some technologies being developed to produce a single chip that houses a monstrous 58 chips in one unit. But the future pathway to those sorts of massive chips isn't entirely agreed upon yet, as learned at TSMC's recent European Technology Symposium that we attended.

Although panel-level packaging technologies are set to enable much larger chip packages, they will not provide, at least initially, the same interconnection densities as today's wafer-level packaging technologies like CoWoS, according to Kevin Zhang, TSMC’s senior vice president of business development and global sales and deputy co-COO.

"The geometry complexity panel-based process has to deal with is nowhere near the wafer level technology capability," Zhang said. "CoPoS, I would say it is one way to basically using panel-based process to continue driving the interposer scaling."

One of the common misconceptions in the semiconductor industry is that panel-based chip packaging technologies will replace existing wafer-based technologies like CoWoS as they promise to enable considerably larger package sizes — think 310mm×310mm, up from existing 120mm×150mm — at lower costs. This is not the case, though, according to TSMC.

"That is an option on the table," Zhang said. "But remember, if you look at our CoWoS roadmap, we still have a lot of runway left with wafer-level technologies. We can scale CoWoS all the way to 14X using wafer-level processes, and we also have wafer-level integration. […] You can integrate 58 large reticle-sized dies together. So, there is still plenty of room for us to continue advancing wafer-level integration. At the same time, our team always wants to make sure we evaluate all future options. Obviously, one of those options is panel-based packaging."

But panel-level packaging cannot leverage the tools currently used for wafer-level packaging, as essentially technologies like CoWoS use the same lithography, etching, deposition, and other tools that were previously used to make logic chips. By contrast, panel-level integration tools are considerably less advanced.

 "From technology point of view, wafer-level-based process is far more advanced than panel," Zhang said. "I am not talking about just TSMC, I am talking about the industry as a whole. Wafer-level processing is where the most advanced manufacturing technology exists today. To move to panel-based manufacturing, the industry needs to improve panel processes rapidly so they can eventually offer a better next-generation solution relative to wafer-level technology."

In fact, the main advantage that panels have over wafers is indeed larger package size: currently, TSMC can use 120mm×150mm substrates, next-generation CoWoS technologies will enable 150mm×250mm substrates, but even substrates the size of a hardcover book look pale compared to the initial 310mm×310mm panels. Furthermore, future packages can get to 515mm×510mm or even 750mm×620mm, which is larger than a wafer. When asked specifically whether CoPoS will complement CoWoS rather than replace it, Zhang essentially answered positively.

 "I think that may be a way to look at it because it depends on the specific product configuration," Zhang said. "At some of the product will continue to get optimum benefit by leveraging wafer-level processing capability. Our goal is to offer our customer all the options they would need in order to find the optimum solution for their next-generation product. CoWoS today [has a lot of] scaling room for us to continue to drive this technology forward. But at the same time, we are looking at a fan-out-based process, some use the word CoPoS, as another alternative path going forward."

TSMC is currently expected to complete its first CoPoS pilot line this June. The gap between pilot and meaningful production is often around two or three years, so a reasonable expectation for high-volume manufacturing (HVM) using CoPoS would be 2028 – 2029. However, keeping in mind that CoPoS uses new tools and since the peculiarities of these tools are unknown, it is more reasonable to expect the first CoPoS-based products in 2029 or 2030, with more meaningful volumes sometime in the first half of the next decade. At the end of the day, CoWoS existed for years before explosive adoption, so CoPoS will likely repeat this pattern.

When we referred to TSMC just several years ago, we called it 'the world's largest foundry,' implying that Intel was still the world's largest producer of advanced logic chips. However, having spent nearly $240 billion on capacity expansion over the last 10 years, TSMC now has nine sites with dozens of 300-mm fabs, many of which can process orders of magnitude more wafers using EUV-based process technologies than Intel*, which makes TSMC the world's largest maker of advanced logic chips.

Being the world's largest maker of advanced AI processors requires TSMC to stay ahead of its rivals, Intel and Samsung Foundry, both in terms of process technologies and, perhaps, even more importantly, in terms of production capacity.

Therefore, TSMC has kicked off the most aggressive manufacturing expansion in its history as the company races to meet explosive demand for AI processors, logic chips made on leading-edge nodes, and advanced packaging.

During TSMC's Tech Symposium 2026 manufacturing presentations, the company revealed that in 2025 – 2026, it effectively doubled its historical construction pace, building or converting nine fab phases annually, up from an average of four phases per year. The company is simultaneously building or ramping new fabs in Taiwan, the U.S., Japan, and Germany. In addition, it introduces new ways to improve the productivity of existing facilities.

N2 ramp: Six-figure amounts of wafers per-month by 2029

The central part of TSMC's expansion plan is its N2 process technology. At present, the company is ramping up production of chips using N2 at two sites: Fab 20 phase 1 and phase 2 in Hsinchu near TSMC's global R&D center, and Fab 22 phase 1 in Kaohsiung. Ramping a leading-edge node at three facilities simultaneously is highly uncommon for foundries. The company also plans to ramp up production at Fab 22 phase 2 shortly and Fab 22 phase 3 by the end of the year. Eventually, Fab 22 phase 4 will come online as well. As a result, TSMC aims to start mass production on its N2 process technology at five facilities in the first year, which is at an unprecedented scale.

As a result of such an aggressive ramp, TSMC expects its N2 wafer-out capacity to be 45% higher than that of N3B in the first year. Reports from 2023 – 2024 indicate that TSMC ramped its N3B production at two or three phases of Fab 18 in 2023 and reached a capacity of around 60,000 wafer starts per month by the end of that year. If the reports are accurate, then TSMC expects its N2 capacity to reach around 90,000 wafer starts per month (WSPM) by the end of the year. This exceeds the fully ramped capacity of Intel's 18A-capable Fab 52, which is believed to be at around 40,000 WSPM.

What is even more impressive is that TSMC intends to increase its N2/A16-capable capacity by 70% every year through 2028, which means hundreds of thousands of WSPM in 2029.

In addition to reaching vast capacity, ramping up five fab phases simultaneously enables TSMC to mitigate risks. If one fab phase experiences a contamination issue, tool failure, or yield issues, the entire N2 supply chain will not collapse. The same applies to ramping up production at two sites located in different parts of the country: an earthquake or utility failure can interrupt production or even cause yield loss at one of them, but it will not affect another. Such risk mitigation is critically important when customers like Apple, AMD, Nvidia, or Qualcomm, which demand a continuous supply. There is potentially another bonus with ramping up these fab phases in parallel rather than in serial, so read on.

N2 ramp: One Team and the Super Manufacturing Platform

Such an unusual ramp strategy seems to be enabled by two programs at TSMC: the "One Team" collaboration between R&D and fab operations, and the Super Manufacturing Platform (SMP) that enables multiple fabs (or rather fab phases) to work as one, which likely has similarities to Intel's "Copy Exactly." TSMC hasn't shared many details about the One Team and SMP, though we can make some educated guesses.

The One Team is a global manufacturing knowledge-transfer system that links R&D, process integration, equipment management, and high-volume manufacturing expertise during technology development and ramp-up. To speed up feedback loops, TSMC likely inserts manufacturing teams relatively early in node development so that R&D teams adjust their work to what is possible at fabs. As a result, yield learning, process optimization, and tool productivity improvements can be done quickly at one fab and then transferred to others. TSMC says that One Team enabled a 20% faster technology transfer compared to N3, without disclosing the time it typically takes to transfer technology from one fab to another.

In addition, all of TSMC's GigaFab sites now rely on its Super Manufacturing Platform (SMP), which is essentially a centralized manufacturing-control system that makes multiple fabs operate as one giant synchronized fab with standard process recipes, tool configurations, metrology, and yield management flows. This should enable TSMC to transfer production between fabs more easily, ramp new nodes faster, introduce yield fixes globally instead of locally, and reduce customer requalification work when production of chips is moved from one fab to another.

Moreover, since every fab phase generates its own tool behavior data, defect density data, process window statistics, and yield learning information, multiple simultaneous ramps may actually accelerate yield/defects learning when SMP and One Team are in place. In turn, it may speed up ramping of fab phases.

A 70% CAGR in N2/A16 capacity in the coming years is an extraordinarily aggressive ramp for leading-edge manufacturing. Without something like TSMC's' One Team structure and SMP, coordinating that scale of expansion across multiple Fab 22 phases, Fab 20, and eventually Fab 21 phase 3 in Arizona would be barely possible both from organizational (operational control) and from economic (yield learning, process window, etc.) points of view.

TSMC also noted that despite the significantly higher complexity associated with gate-all-around (GAA) nanosheet transistors, N2 is achieving a better yield learning curve than N3, which again can be attributed to the innovative approaches that the company uses.

Beyond N2: A14, A13, and A12

TSMC's N2/N2P/N2X/N2U/A16 production will largely be concentrated at Fab 20 phase 1 and 2, Fab 22 phases 1, 2, 3, 4, and, to some degree, Fab 21 phase 3. However, for nodes beyond 2nm-class (A16 is essentially N2P with a backside power delivery network), such as A14, A13, and A12, TSMC will build Fab 21 phase 3 and then the all-new Fab 25 site in central Taiwan with at least four phases.

A14 is set to start high-volume production in late 2028, so there is a good chance that TSMC will ramp it at both Fab 20 phase 3 and Fab 25 phase 1. However, given the company's aggressive approach to capacity expansion, TSMC might well surprise us once again. Also, we do not yet know how TSMC plans to upgrade N2/A16-capable fabs to subsequent nodes, if at all.

Expansion beyond N2

The expansion is not limited to the N2 production node and subsequent technologies. TSMC is continuing to grow combined N3 and N5 capacity at a 25% compound annual growth rate (CAGR) from 2022 through 2027. To address immediate demand, the company is converting some N5 capacity into N3 production, which is not particularly expensive, since N3 reuses 85% - 90% of the tools used for N5. Furthermore, as much of TSMC's N3 and N5 capacities are concentrated at Fab 18 (four phases N5, four phases N3), converting some of the N5 capacity to N3 is relatively easy from a logistical perspective.

AI is here to help (to build more AI processors)

Alongside the conversion of N5 to N3 capacity, TSMC also heavily uses AI to improve the performance of each tool, and the whole fab in particular. Essentially, TSMC uses AI to build more AI processors, which seems to be a paradox, but it is becoming popularized as AI becomes embedded within workflows.

One of the things that greatly slows down cycle times of modern fabs is batch processing of wafers in various chambers, something that is an inevitable part of some 5,000 steps. Essentially, 25 wafers ‘wait’ in a (perhaps in a CVD chamber) for a lithography tool to process them individually.

Atsuyoshi Koike of Rapidus thinks differently and believes that a single-wafer processing across all steps can significantly speed up cycle time, but at the cost of tool efficiency. TSMC does not seem to plan to use single-wafer processing (despite its purchasing power, it can likely persuade fab tool makers to produce appropriate tools), but it can certainly optimize the ways in which it uses existing tools to boost the productivity of its existing fabs.

TSMC revealed at its recent Technology Summit that it uses intelligent scheduling systems that incorporate 'state-of-the-art linear programming and heuristic algorithms' to optimize equipment efficiency, though it did not reveal what exactly is done and what is achieved. TSMC further revealed that it uses generative AI algorithms to identify optimal parameters that 'challenge the physical limits of equipment' while maintaining wafer quality. In parallel, the company analyzes tool logs using big-data analytics and text-mining systems to dynamically adjust key parameters, minimize tool idle time, and maximize output.

AI systems are also used for real-time chamber condition analysis to determine optimal chamber-cleaning timing and avoid unnecessary maintenance that could reduce machine uptime and available capacity. In addition, TSMC disclosed that AI-assisted comparison and fine-tuning of large volumes of machine verification parameters reduced the time required to validate new tools and reach high-volume manufacturing by more than 20%, which helps to ramp up new fab modules faster.

TSMC also said it achieved more flexible allocation and higher combined N3 and N5 capacity at Fab 18 in Tainan by increasing equipment commonality and integrating 'cross-technologies planning,' which essentially means that the company re-uses as many tools as possible.

Expansion beyond Taiwan

Outside of Taiwan, TSMC continues to broaden its geographic footprint. In Arizona, Fab 21 phase 1 is already producing chips using N4 technology (with capacity increasing by 1.8X this year alone), while Fab 21 phase 2 is on track to start N3 production in Q3 2027. Fab 21 phase 3 targets N2 sometime later this decade, as the company continues to construct shells both for phase 3 and phase 4. The company also reaffirmed plans for an advanced packaging facility, an R&D center, and additional land acquisitions to support future expansion.

In Japan, the company’s Kumamoto Fab 23 phase 1 is already producing 28nm and 22nm chips, while Fab 23 phase 2 underwent a major strategic shift. Originally planned for 7nm-class production, the facility will instead manufacture using technologies down to N3 3nm to address stronger-than-expected local demand and onshoring intentions of local chip designers.

Meanwhile, Fab 23 in Dresden, Germany, which is under construction, is aimed at automotive and industrial applications with legacy planar transistors and FinFET-based 28nm, 22nm, N16, and N12 production nodes.

Advanced Packaging

AI itself is now one of the main drivers behind the company's unprecedented capacity growth. TSMC disclosed that wafer shipments for AI accelerators are expected to rise 11X between 2022 and 2026. The company also highlighted the rapid growth of extremely large dies exceeding 500 mm^2, as shipments of those devices are projected to increase 6X over the same period. Such products typically require lots of wafer capacity (wafer starts) and advanced packaging technologies, since many of these designs use HBM3E memory.

Advanced packaging has therefore become just as important as wafer fabrication itself. TSMC said its CoWoS capacity will grow at an 80% CAGR between 2022 and 2027, while SoIC capacity will expand at a 90% CAGR during the same timeframe. TSMC also said it has improved development-to-HVM transition times by 30% for CoWoS and by 75% for SoIC compared to earlier generations.

TSMC currently operates 11 advanced packaging facilities in Taiwan (AP1 in Hsinchu, AP2A/AP2B/AP2C and AP8 in Tainan, AP3 in Longtan, AP5 in Taichung, AP6A/AP6B/AP6C in Zhunan, and AP7 in Chiayi). According to a recent DigiTimes report, the company is simultaneously expanding multiple advanced packaging campuses, including AP5, AP6, AP7, and AP8.

The AP7 site in Chiayi will reportedly become TSMC's largest advanced packaging campus using SoIC to support major customers like Nvidia, which plans to use 3D packaging technologies for its next-generation Feynman GPUs. AP8 — converted from a former Innolux LCD fab — is expected to exceed 40,000 wafers per month of CoWoS capacity by late 2026.

While CoWoS is the de facto standard for AI processors, SoIC is set to become much more widely used in the coming years. As a result, the company is also rapidly expanding its SoIC production capacity. DigiTimes claims that AP6 in Zhunan could approach 10,000 SoIC wafers per month, whereas AP7B may add approximately 12,000 wafers per month. Future AP7 phases are expected to support both SoIC and CoPoS technologies, though CoPoS is a part of TSMC's roadmap in the 2030s.

Advanced packaging now requires tight ecosystem integration that includes HBM suppliers, substrate vendors, OSAT partners, testing companies, materials providers, and toolmakers, with which TSMC works to standardize those tools. The very emergence of such an ecosystem emphasizes the increasing role of TSMC in the burgeoning AI industry.

An all-encompassing roadmap

After investing nearly $240 billion into capacity expansion over the last decade, TSMC has evolved from the world’s largest foundry into the world's largest producer of advanced logic chips, producing the lion's share of AI processors today.

To support the explosive AI demand and to stay ahead of Intel and Samsung Electronics, TSMC has doubled its historical fab construction pace to nine fab phases annually in 2025 – 2026 while simultaneously expanding in Taiwan, Arizona, Japan, and Germany. The company's N2 ramp is unprecedented as the company preps to ramp five fab phases within the node's first year, and N2/A16 capacity is projected to grow at a 70% CAGR through 2028.

TSMC said this aggressive expansion is enabled by its One Team organizational structure and Super Manufacturing Platform (SMP), which synchronizes manufacturing, yield learning, and process control across multiple fabs. The company is also implementing various AI-driven manufacturing optimizations, including intelligent scheduling systems, generative AI process tuning, and real-time tool analytics to improve throughput, reduce cycle times, and accelerate tool qualification.

At the same time, TSMC is rapidly expanding advanced packaging capacities. The company intends to increase CoWoS and SoIC capacities at 80% and 90% CAGR, respectively, through 2027, as demand for both technologies is expected to grow as chiplet-based designs and HBM memory are technologies of choice for AI accelerators.

*TSMC's wafer processing revenue for 2025 was $103,708.5 billion, thus representing around 84% of consolidated revenue of $122.4 billion. EUV-based N3 and N5 process technologies accounted for 60% of TSMC's wafer revenue in 2025, thus earning around $62,225 billion. Intel Foundry earned $17.826 billion in 2025, $307 million came from external customers that mainly ordered advanced packaging. It is estimated that process technologies that use EUV account for more than 10% but less than 20% of Intel's wafer revenue.

Intel does not disclose a revenue split similar to TSMC's (wafer fabrication vs. packaging/testing vs. other) in its official filings, so its wafer processing revenue is hard to estimate, especially given the fact that some of its silicon is made at TSMC and is packaged internally. Nonetheless, even 20% of Intel Foundry's 2025 revenue is $3.565 billion, which is over 17 times less than TSMC earns on its EUV-based nodes.

Chinese semiconductor start-up Prinano announced that it has successfully validated the mass production of photonic chips without using the industry-standard lithography equipment. According to an SCMP report, the company said in a WeChat post on Friday, June 5th, that it had made 8-inch optical chip wafers in collaboration with Shenzhen Litra Technology. The company said it achieved this while “completely avoiding” the need for deep-ultraviolet lithography (DUV), a significant breakthrough in China’s push to reduce its dependence on ASML lithography tools, which remain subject to export restrictions.

Instead of conventional optical lithography, Prinano said it used its PL-AS vacuum air-cushion nanoimprint lithography (NIL) system, which, according to the company, can reduce manufacturing costs to roughly one-tenth that of traditional DUV-based processes, while supporting wafer-level production of photonic chips.

Modern chips are typically produced using highly sophisticated DUV or more advanced EUV (extreme ultraviolet) systems that project circuit patterns onto silicon wafers using light. These machines contain some of the most complex optics ever built and can cost hundreds of millions of dollars. Nanoimprint lithography takes a very different approach. Rather than projecting patterns using light, it physically presses nanoscale structures into a specially prepared resist layer, basically stamping microscopic patterns directly onto the wafer surface. This process eliminates the need for many of the expensive optical systems required by conventional lithography equipment.

Nanoimprint lithography has long been viewed as a potential alternative to conventional optical lithography because of its potential for lower costs and extremely high pattern resolution. However, despite its promise, the technology has struggled to achieve widespread adoption in semiconductor manufacturing due to concerns about defect rates, template wear, throughput, and production yields, all of which become increasingly important in high-volume manufacturing environments.

Founded in 2017, Prinano has spent the past several years working to overcome those limitations by developing its own nanoimprint lithography ecosystem. The company took a significant step in 2025 when it announced the delivery of what it described as China's first semiconductor nanoimprint lithography system to a domestic customer, marking an early effort to commercialize the technology.

The company's latest announcement suggests it may have progressed beyond equipment development and pilot deployments. According to Prinano, its PL-AS vacuum air-cushion nanoimprint lithography platform incorporates wafer-level pressure control, customized double-layer imprinting materials, and proprietary process technologies capable of producing sub-10-nanometer features. The company now claims those developments have enabled the successful validation of wafer-scale photonic chip production on 8-inch wafers.

Importantly, Prinano is not attempting to replace the production of cutting-edge processors or AI accelerators. Instead, the company's announcement focuses on photonic chips, a category of semiconductors that manipulate light rather than electrical signals. These devices are widely used in fiber-optic communications, data center interconnects, sensing systems, and LiDAR technologies.

Photonic chips are considered particularly well suited to nanoimprint lithography because many of their critical structures, including waveguides, gratings, and ring resonators, consist of repeating nanoscale patterns that can be replicated efficiently through imprinting techniques. This characteristic makes them a more practical near-term application for NIL than advanced logic chips, where defect rates and alignment requirements are far more demanding.

Another noteworthy detail is the use of 8-inch wafers. While leading-edge processors are increasingly manufactured on larger 12-inch wafers, 8-inch wafers remain widely used across specialized sectors such as compound semiconductors and power electronics. Demonstrating production on full 8-inch wafers suggests the process has moved beyond laboratory-scale demonstrations and into a format more compatible with commercial manufacturing.

The development also highlights China's broader search for alternative semiconductor manufacturing pathways amid ongoing export restrictions. Access to advanced lithography equipment from ASML — required for EUV and DUV — has been increasingly constrained under US-led controls, prompting Chinese companies to explore alternative approaches ranging from advanced packaging technologies to new chip architectures and novel manufacturing methods. Huawei recently announced a new LogicFolding chip architecture that allows the company to develop high-performance processors without relying on restricted EUV lithography machines.

Significant questions remain about Prinano’s announcement. While the claims have been validated in mass production, the company did not disclose production volumes, yield rates, defect densities, customer shipment data, or independent third-party validation. These metrics are critical for determining whether a semiconductor manufacturing technology is commercially viable rather than merely technically feasible.

ASML closed Wednesday, June 3rd, as the most valuable company in European history, reaching a market cap of $668 billion and passing the $650 billion record Novo Nordisk set in June 2024. The Dutch firm, which is the sole supplier of the extreme ultraviolet (EUV) lithography machines that TSMC, Samsung, and Intel use to print leading-edge logic, rose after JPMorgan and Morgan Stanley published near-identical notes arguing it can manufacture far more machines than the market had assumed.

The two banks raised their price targets on the same day, JPMorgan to €1,900 from €1,515 and Morgan Stanley to €1,660 from €1,400, both keeping Overweight ratings. JPMorgan analyst Sandeep Deshpande argued that ASML can deliver more than 110 low-NA EUV systems without adding new building capacity, well above the roughly 90 units investors had previously cited as the maximum and above the company's own near-term output.

That output is mission-critical for the chip industry because EUV remains a severe chokepoint on advanced chip supply. Every wafer of leading-edge silicon used to train and run AI models passes through an ASML scanner at some stage, so more machines shipping translates directly into more capacity for the fabs downstream.

Morgan Stanley said its greater confidence in near-term shipments stemmed from comments at ASML's April annual general meeting, where the company outlined an expansion at the Brainport Industries Campus in Eindhoven, with construction set to begin in the third quarter of 2026. The bank cautioned that the campus "needs to be the start of a multi-phase build-out" to fully alleviate capacity concerns.

ASML’s record ironically sits below the bar set by the companies ASML supplies. Its market cap remains short of the trillion-dollar mark that several U.S. chip firms have cleared, and the stock's roughly 50% gain this year has trailed the broader semiconductor sector, which has run far hotter on AI demand. ASML had already passed SAP as Europe's largest listed company and is now worth more than the next two European firms, HSBC and Roche, combined.

And while the company holds a monopoly, its long-term dominance isn’t guaranteed; several efforts are currently taking aim at it. Substrate, a San Francisco startup backed by Peter Thiel's Founders Fund and the CIA-linked In-Q-Tel, has raised $100 million for a particle-accelerator X-ray lithography system that it claims can pattern 2nm-class features at roughly $10,000 per wafer against the $100,000 it models for leading-edge EUV. Canon is also shipping commercial nanoimprint tools, while Nikon has entered with a lower-end product, and China has touted a workaround to ASML's equipment.

None of these is likely to replace an EUV scanner in high-volume logic anytime soon, where ASML's tools run from roughly $235 million for a low-NA system to about $380 million for the High-NA EXE:5200B that Intel installed late last year for its 14A node.

Asked about rivals by TechCrunch last month, ASML CEO Christophe Fouquet said the gap between wanting the technology and having it remains vast, adding that "when you start from scratch, the challenge is enormous."

TSMC CEO C.C. Wei has told company shareholders that it still won’t be able to completely address the production demands for AI chips in the years to come. Even though the company has opened multiple fabs across the world, including the one in Arizona, the insatiable demand for the most advanced processors means that there still isn’t enough production capacity to go around for all customers. Bloomberg reports that the additional capacity that is expected to go online in the U.S. is still not enough to feed the increasing demand from hyperscalers.

“It will be a long time before we can meet customer demand,” C.C. Wei said. Despite that, TSMC is still forecasting a 30% increase in sales this year. It’s also not taking advantage of the supply bottleneck, with Wei adding that the company will avoid sudden price hikes similar to the memory and storage chip market industry’s experience to ensure business stability.

Hyperscaler buildouts are expected to hit $725 billion just this year. And unless the AI bubble bursts, demand is only expected to go up every year. TSMC has been building many new fabs in Taiwan, the U.S., and other parts of the world. But building these manufacturing plants would take years, and it seems that semiconductor manufacturing demand would outpace supply if the current AI infrastructure build-out continues.

TSMC Arizona’s manufacturing capacity has been sold out through 2027 since early 2025, showing the massive demand for the company’s output. The company is continually expanding this site, too, with its Taiwan headquarters authorizing a $20 billion capital injection last month to continue the development of Fab 21 phase 2. It’s expected that this would allow the company to start mass producing 3nm chips in Arizona in 2027, which is about a year earlier than the original 2028 launch date. There have also been reports of additional fabs and other units, bringing the total Arizona site to 12 fabs, 4 packaging facilities, and an R&D center.

These production shortages mean that TSMC can expect that their expansion plans will have customers once they’re completed. However, this is also an opportunity for Intel, which is trying to win customers for its 18A and 14A processes. Both Apple and Nvidia are reportedly considering Intel for some of their 2028 chip production, and sources say that the former has already reached a preliminary agreement with Team Blue.

The lack of availability has also led Elon Musk into semiconductor manufacturing. Even though building chips is a totally different beast when compared to building electric cars and even rocket ships, it seems that the billionaire founder is ready to take on the challenge with Terafab. It seems that he’s pretty serious, too, with his team already in talks with various suppliers and that they’re willing to pay a premium to ensure priority.

Samsung displayed its first physical mockup of HBM5 memory at Computex 2026 in Taipei. Tom's Hardware dropped by to see its pairing of the eighth-generation AI memory with a new in-package cooling structure it calls Heat Path Block, or HPB. Just last week, rival SK hynix unveiled its own iHBM thermal design, meaning both companies are now focusing on the same heat bottleneck in the die-to-die interface that connects memory to the processor. Samsung also confirmed that it’ll fab HBM5’s base die on its in-house 2nm process, down from the 4nm node used for HBM4 and HBM4E.

Rather than letting heat escape outward through the core dies, HPB builds a separate set of thermal pillars that pull heat from inside the stack and carry it to a spreader sitting above or beside the package, according to Samsung at Computex.

The design concentrates on the D2D PHY layer, the high-speed link between the HBM base die and the GPU, where power density and temperatures increase exponentially as stacks grow taller and run quicker. Samsung said it has already implemented and verified HPB on HBM4E, the generation whose first 12-layer samples it began shipping last month at 14 Gbps, scaling to 16 Gbps, with 3.6 TB/s of bandwidth per stack.

Samsung runs both a memory business and a logic foundry, letting it build the HBM5 stack and the 2nm die beneath it in-house. "AI systems are becoming more powerful and densely integrated, making heat management, data-processing efficiency, and packaging stability just as important as memory performance itself," Song Jai-hyuk, president and CTO of Samsung's Device Solutions division, told reporters at Computex, according to the Korea Herald. Song said the company would keep building its competitiveness in next-generation memory through cooperation with partners, including Nvidia.

Last year, a roadmap from KAIST projected HBM5 reaching a 4,096-bit interface, roughly 4 TB/s per stack, and about 100 watts of per-stack power, a thermal load that goes a long way in explaining why both Korean memory giants are reworking their packaging now rather than at launch.

SK hynix faced the same problem via a different route. Its iHBM design embeds cooling elements made of electrically non-conductive, thermally conductive silicon into the D2D PHY layer, which the company said cuts thermal resistance by more than 30% against current products.

SK hynix has opted to place a cooling element directly at the hotspot, while Samsung has built a route to evacuate heat away from it. Both methods are slated to debut with HBM5, but it’ll be a little while before we see either in action, as neither company expects it to reach mass production before 2028.

Thousands of SK hynix employees fled their factory stations earlier today as a fire broke out in a room where fluorine gas was used. Yonhap News reports that seven of the workers have been hospitalized, five are being treated for eye irritation, and two are under observation (machine translation). At the time of writing, a cleanup operation appears to be continuing at SK hynix’s Cheongju 4th campus, with all 3,600 employees evacuated. A company official told Yonhap, “There are no issues with equipment operation, so there will be no production disruption.”

Reports indicate that the fire began at around 10.23 am Korean time today. An unintentional fire is probably not a great thing anywhere in an advanced semiconductor fab, even in the burgers and cigars wing. However, in “the gas room on the 6th floor connecting the M15 and M15X factories at SK Hynix's Cheongju 4th campus,” it could have been a particularly nasty incident. This room includes equipment/canisters/pipelines holding highly toxic fluorine gas.

According to the Korean news source, the fire in the gas room was extinguished immediately by sprinklers, but fluorine escaped into the room at a concentration estimated to be 5 ppm. This is where the seven hospitalized workers had been situated.

Fluorine gas is used in various industrial processes, but it is a highly reactive gas that can cause spontaneous combustion or explosions if it comes into contact with common materials. It is also quite deadly to humans. Wikipedia states that “significant irritation of the eyes and respiratory system as well as liver and kidney damage occur above 25 ppm… The eyes and nose are seriously damaged at 100 ppm… and inhalation of 1,000 ppm fluorine will cause death in minutes.”

Official insists there will be “no production disruption”

With the immense demand and pressure on memory-making titans like SK hynix, some may be concerned that a facility like Cheongju closing even for a few hours could impact supplies, schedules, pricing, and more. However, an official insisted, “There are no issues with equipment operation, so there will be no production disruption.” It was also suggested that the fire/leak occurred in the gas pipeline, but that fact had yet to be determined.

At the time of writing, there may still be environmental purification and repair work to do. If and when that’s completed, operatives will begin safety inspections, including air quality measurements. After the all-clear, “we plan to return the employees,” the official told Yonhap. We’ve linked to the latest report on this incident available at the source.

TikTok owner ByteDance is reportedly developing its own custom AI CPUs in a bid to reduce its reliance on US chipmakers. Per a Reuters report, ByteDance's new chip is inspired by Groq's "language processing units," a fancy term for a chip optimized for inference tasks — running AI models instead of training them. The move comes in a context where inference-heavy agentic AI is quickly becoming the new normal. The project is seemingly in the concept and design stage, with Reuters' sources claiming that ByteDance is evaluating both Arm and RISC-V designs.

Additionally, The Information claims ByteDance is partnering with Chinese startup InnoStar Semiconductor for memory technology related to the project, potentially obviating the need to acquire rare and expensive HBM chips from Samsung and the like. The Chinese startup got investments from ByteDance and Alibaba, China's cloud and e-commerce giant.

However, ByteDance doesn't appear to have its own chip design teams, and will purportedly rely on "several external partners", who are expected to also take care of the actual silicon manufacturing. The firm's CPU project takes place against a geopolitical tussle that got China's government banning the purchase of Nvidia H200 Blackwell chips, after the Trump administration backtracked on its technological export controls.

This is hardly ByteDance's first rodeo with investing in its own technology, too, as it started designing its own SeedChip AI accelerator with TSMC back in 2024, a silicon slab expected to tape out and be mass-produced this year still. For now, the expectation is that ByteDance will use hybrid architectures for its servers as dependence on Nvidia is still an unfortunate necessity, but over time, it wouldn't be surprising to see the firm waving goodbye to the back of Jensen Huang's leather jacket.

Furthermore, much like any other advanced chip vendor these days, Intel and AMD reportedly keep increasing prices every quarter as they hold the lion's share of the CPU market. Nvidia's recently unveiled Vera chips show great promise, but once again, we're talking about a U.S. firm. Although Bytedance is best known for TikTok, the world's leading short-form video app, the company runs China's AI chatbot app Doubao and has a handful of AI models under its belt.

The global foundry market is dominated by TSMC, which captured 69.9% of global foundry revenue in 2025, but beyond the glitz and glamor of the leading edge sit a tier of foundries that collectively manufacture the chips found in cars, power supplies for AI servers, RF front-end modules, display drivers, industrial controllers, and defense systems. GlobalFoundries, UMC, and SMIC posted a combined 2025 revenue of roughly $24 billion and hold approximately 13.5% of the global foundry market between them.

Each is pursuing a fundamentally different strategy shaped by geography, regulation, and technology choices. GlobalFoundries is becoming a U.S. and European specialty foundry, backed by $1.575 billion in CHIPS Act funding and a $3.1 billion Department of Defense contract.

Meanwhile, UMC is bridging from pure mature-node services into 12nm FinFET territory through a manufacturing partnership with Intel, and SMIC is China's de facto national champion, expanding mature-node capacity at enormous scale while pushing the limits of what DUV lithography can achieve under tightening export controls. We break down each of these trailing-edge foundries to see what might be coming up next.

GlobalFoundries

GlobalFoundries (‘GF’) exited leading-edge development in 2018 when it canceled its 7nm program and has since repositioned as a specialty foundry focused on differentiated process platforms. That strategy produced FY2025 revenue of $6.79 billion (up 1% year-over-year), with Q4 gross margin of 27.8% and full-year operating cash flow of $1.73 billion. The company's automotive segment hit a record $1.4 billion, up 17% year-over-year, according to its SEC filing.

Its current node portfolio runs from 12LP FinFET down to 180nm and spans several specialty platforms. The company's flagship is 22FDX, a 22nm fully depleted silicon-on-insulator (FD-SOI) process targeting ultra-low-power IoT, automotive radar, millimeter-wave 5G, and microcontrollers with embedded MRAM support. Meanwhile, 45RFSOI is the dominant global platform for 5G RF front-end modules. Below those sit 28nm, 40nm, and 55nm logic nodes, alongside BCD for power management, SiGe BiCMOS for high-frequency analog, and a ramping GaN-on-silicon platform at its Vermont facility.

Two recent acquisitions, however, have expanded GF beyond pure-play manufacturing. It bought Singapore-based Advanced Micro Foundry last year, making it one of the world's largest silicon photonics foundries, and acquired MIPS (for RISC-V CPU and AI inference IP) along with Synopsys' ARC and RISC-V processor IP portfolio. The company now offers customers pre-built compute IP alongside fabrication, a model no other trailing-edge foundry currently can.

GF operates five manufacturing sites. Fab 8 in Malta, New York, is its most advanced 300mm facility and holds Trusted Foundry Category 1A accreditation from the U.S. Department of Defense. A new fab at the Malta site, funded partly by a $1.587 billion CHIPS Act award, will triple the site's capacity over the next decade as part of a $16 billion, 10-year U.S. investment plan.

Fab 1 in Dresden is Europe's largest semiconductor fab, with a €1.1 billion expansion underway to push output toward 1.5 million wafers per year by the end of 2028. Fab 7 in Singapore opened in September 2023 after a $4 billion build-out, adding 450,000 wafers per year. The two remaining sites are both 200mm facilities in the U.S.: Fab 9 in Burlington, Vermont, which is targeted for the company's first high-volume GaN production line.

The company's 2026 capital expenditure guidance of 15% to 20% of revenue represents a sharp jump from 8% in 2025, driven by what management described as oversubscribed demand in silicon photonics, 22FDX, and SiGe. That investment will compress free cash flow margins in the near term, but GF has said customer prepayments and long-term agreements underpin spending.

Reports surfaced in 2025 of an internal assessment dubbed "Project Ultron" exploring a potential takeover of UMC that would create a mature-node foundry with roughly 28% combined market share. UMC denied active merger talks, and, in any case, the regulatory barriers across Taiwan, China, and the U.S. are more than likely insurmountable.

UMC

UMC reported Q1 2026 revenue of NT$61.04 billion (approximately $1.93 billion), with net income surging 107.9% year-over-year to NT$16.17 billion. Gross margin was 29.2% and capacity utilization stood at 79%, with Q2 guided to the low-80% range and wafer shipments expected to rise by high single-digit percentages.

The 22nm node is UMC's primary growth driver. Revenue from 22nm grew 93% year-over-year in 2025 and now accounts for 14% of total revenue, up from single digits the prior year. Combined, 22nm and 28nm represent 34% to 36% of quarterly wafer revenue.

UMC dominates small-panel display driver IC (DDIC) production at 28nm, holding over 90% market share in that segment, and launched an advanced 22nm embedded high-voltage (eHV) platform in 2024, targeting next-generation smartphone OLED displays. Specialty processes extend across embedded non-volatile memory (eFlash from 350nm to 28nm), RFSOI, RF CMOS, and BCD for analog and power applications down to 55nm.

UMC operates 12 fabs with combined capacity exceeding 400,000 12-inch-equivalent wafers per month. The newest, Fab 12i Phase 3 in Singapore, opened in April last year after a $5 billion investment and will start 22/28nm volume production this year, with an initial capacity of 30,000 wafer starts per month and with space reserved for a second phase.

The most significant item on UMC's roadmap is its 12nm FinFET node, co-developed with Intel and targeted for mass production in 2027 at Intel's fabs in Chandler, Arizona. The process offers 10% higher performance, 20% lower power, and roughly 10% area reduction compared with UMC's existing 14FFC, with three fewer mask layers.

UMC's CFO Chi-Tung Liu confirmed last May that the majority of UMC's R&D spending is now directed at this node. The partnership gives UMC its first U.S. manufacturing footprint and a FinFET node at scale, while Intel gains mature-node foundry volume through what are largely depreciated fabs.

SMIC

SMIC posted record full-year 2025 revenue of $9.33 billion, up 16.2% year-over-year, according to the company's annual results. Full-year utilization averaged 93.5%, a jump of eight percentage points from 2024, and wafer shipments rose 20.9% to roughly 9.7 million 8-inch-equivalent wafers.

Annual capex, meanwhile, ran at over $7 billion, reflecting an aggressive capacity build-out that is compressing margins: full-year gross margin was 21%, and the company guided Q4 2025 gross margin to 18% to 20% as depreciation from new fabs weighed on profitability even at near-full loading.

SMIC's production stack officially spans 350nm to 7nm, but the vast majority of output sits at 28nm and above. 28nm HKMG and PolySiON variants serve smartphones, networking, and DDICs. Nodes from 40nm through 180nm cover analog, power management, RF, image sensors, and microcontrollers.

At the advanced end, SMIC's N+2 process (7nm-class) is in production for Huawei's Kirin 9000S, 9020, and Ascend 910C, with an estimated 20,000 WSPM of capacity. N+3, confirmed on the Huawei Kirin 9030 in December, extends 7nm-class scaling using DUV multi-patterning, though TechInsights characterized it as firmly 7nm/6nm-equivalent in absolute terms rather than a true 5nm node.

Four major new 12-inch fabs are under construction or recently completed, in Shanghai (Lin-Gang), Shenzhen, Beijing, and Tianjin, including an $8.87 billion facility, collectively targeting approximately 340,000 wafer starts per month of new 28nm-and-above capacity.

Export controls from the U.S., the Netherlands, Japan, and Taiwan constrain SMIC's ability to scale its advanced nodes. The company has been on the U.S. Entity List since December 2020, blocking access to ASML EUV scanners and progressively tightening DUV and etch equipment supply.

Taiwan added SMIC and Huawei to its own export-control blacklist in June 2025, requiring permits for high-tech equipment shipments. Although it was reported back in August that SMIC planned to double its 7nm capacity in 2026, the company remains constrained by tooling access: analysts estimate SMIC's advanced-node capacity will remain in the low tens of thousands of wafer starts per month rather than the hundreds of thousands that an unconstrained buildout would target.

SMIC's pricing reflects the competitive pressures in the mature-node segment, with the company having reportedly cut 28nm wafer prices by roughly 40% in early 2025, dropping from approximately $2,500 to $1,500 per wafer, before reversing course with a roughly 10% increase later in the year as utilization exceeded 95%.

Pricing and demand

After two years of price declines driven by Chinese capacity additions, the mature-node segment is reaching a floor. TrendForce reported in March that UMC, VIS, Powerchip, and Nexchip were preparing price increases of up to 10% from April through June this year, with the latter confirming a 10% hike effective from June.

One big factor is tightening supply alongside the cyclical recovery: TSMC has been reallocating 40-90nm production capacity toward CoWoS advanced packaging and silicon interposer fabrication for AI accelerators, reducing the available mature-node wafer supply from the world's largest foundry.

Demand from automotive (GF's automotive revenue alone is on track for $1.5 billion in 2026), power management ICs for AI servers (typically manufactured on 28-55nm BCD processes), DDICs, and embedded flash microcontrollers continues to grow.

Whether these three foundries remain independent is an open question. The Project Ultron reports suggest that at least one party has considered consolidation, and the logic for doing so, at least in terms of economics, grows as margins compress and capex requirements grow.

While SMIC's expansion is state-backed and largely insulated from commercial return calculations, GF is tied to U.S. industrial policy and defense spending, and UMC's future hinges on whether 12nm FinFET with Intel can deliver the revenues that pure mature-node services cannot.

Peking University's School of Integrated Circuits has unveiled a prototype electronic design automation (EDA) tool built specifically for Huawei's LogicFolding architecture, according to the South China Morning Post. The tool takes what researchers described as a "true-3D" approach, optimizing an entire multilayer chip as a single vertical structure rather than designing each layer in two dimensions and stacking them afterward. In early tests of open-source circuit designs, the university reported a 30% reduction in total internal wire length, along with improvements in performance and thermal management, compared to conventional EDA workflows.

The announcement came two days after Huawei presented LogicFolding and its accompanying Tau Scaling Law at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai. Huawei's goal is to produce chips with transistor density equivalent to 1.4nm processes by 2031, all without access to the extreme ultraviolet (EUV) lithography equipment restricted under U.S. export controls.

LogicFolding works by folding traditional 2D circuit layouts into vertical 3D stacks, shortening the physical paths that electrical signals travel through a chip. That reduces resistance and capacitance on critical wiring, compressing signal propagation delay. Huawei's Kirin smartphone processors launching later this year will be the first commercial chips to use the architecture.

Synopsys and Cadence both offer 3D IC design platforms for multi-die stacking and advanced packaging. But those tools address a different problem: integrating separate chiplets or dies within a package. LogicFolding folds transistor-level logic within a single chip into vertical layers, an intra-die optimization that requires place-and-route tools to work across the full vertical structure simultaneously instead of partitioning separate dies.

Peking University's prototype reportedly addresses this by treating the multilayer structure as a unified design space from the start, but whether their claim of 30% wire-length improvement holds up at production scale remains to be seen.

Synopsys, Cadence, and Siemens EDA command 31%, 30%, and 13% of the global EDA market, respectively, and their combined share within China exceeds 80%, according to EE Times China. The U.S. imposed and then lifted EDA export restrictions last year as part of a rare-earth materials deal. Still, the episode highlighted how dependent Chinese chipmakers remain on Western tools.

China's domestic EDA companies, including Empyrean Technology and Primarius, have made progress in analog, mixed-signal, and physical verification, but none offer a full digital design flow competitive with the Western incumbents at advanced nodes.

A university prototype is a very long way from production-grade commercial software. EDA tools require years of development, extensive process design kit integration with foundries, and validation across thousands of tape-outs before chipmakers trust them. "No single company can independently find all the answers along the path of semiconductor evolution," He Tingbo, chairwoman of the Huawei Scientist Committee and president of the company's semiconductor business department, said at a media briefing on Monday.

China's official technology security bodies on Tuesday certified nine domestically designed AI processors for state procurement, according to the South China Morning Post, creating a brand-new "AI training and inference chips" category under the country's Anke security certification framework. The approved products include Huawei's Ascend 310 and Ascend 910 processors, Alibaba's T-Head Zhenwu M530 and M890, and chips from Biren Technology, Hygon Information Technology, Iluvatar CoreX, MetaX, and Moore Threads. Two of China's most prominent AI chip developers, Cambricon Technologies and Baidu-backed Kunlunxin, didn’t appear on the list.

The certifications are valid for three years and were issued jointly by the China Information Technology Security Evaluation Centre and the National Secrecy Science and Technology Evaluation Centre. Their approvals function as a de facto procurement catalog for government agencies, central state-owned enterprises, and other entities covered by Beijing's Xinchuang initiative, the long-running campaign to replace Western hardware and software across sensitive Chinese IT systems.

The new list represents a substantial expansion from China's initial foray into certifying domestic AI hardware. In December, Beijing added only Huawei and Cambricon to the Xinchuang procurement list (a separate state approval mechanism) for AI processors. Five months later, seven vendors now hold Anke security certification for nine separate chips. The Xinchuang program had previously focused on replacing Intel and AMD CPUs and Oracle databases in government systems, but AI accelerators are the newest addition to that.

Cambricon's absence stands out given that the company was on the December list and is targeting 500,000 AI chip shipments in 2026. An anonymous source told the SCMP that companies can choose whether to submit products for testing, so exclusion doesn’t necessarily indicate a failed evaluation. Each chip must pass tests under the Anke V3.0 requirements to qualify.

Chinese chipmakers continue to eat into Nvidia's position in the domestic market. Chinese semiconductor firms delivered 1.65 million AI GPUs in 2025 out of a total of 4 million units, claiming 41% of local AI server shipments. Huawei alone shipped roughly 812,000 AI chips and is projecting $12 billion in AI processor revenue for 2026. Morgan Stanley estimates China's total AI chip market could reach $67 billion by 2030, with domestic supply covering roughly 76% of demand.

Wafer fab capacity remains a big constraint, however, with all of the certified chipmakers competing for limited production slots at SMIC, whose most advanced stable node is its N+2 process, which is roughly equivalent to 7nm. SMIC reported overall utilization rates above 93% for 2025 and spent $8.1 billion in capex last year, with plans to hold that level through 2026.

SK hynix announced iHBM today, a memory heat management technology designed to enhance AI system performance. The thermal packaging solution improves heat dissipation by integrating ICEs (integrated cooling elements) directly into the HBM package. SK hynix says the result is an over 30% reduction in thermal resistance, “ensuring stable operating characteristics even in high-temperature and high-load environments.”

The iHBM architecture embeds non-conductive silicon cooling elements directly into the Die-to-Die Physical Layer (D2D PHY), the critical, high-speed connection interface between the HBM base die and the AI processor, which is prone to high temperature spikes as a result of extreme data traffic. By placing cooling elements in this layer, SK hynix mitigates the severe thermal throttling that cripples AI system performance during heavy computational workloads.

The company believes that structurally preventing thermal throttling will enable next-generation memory layers (targeted for future generations like HBM5) to scale to higher stack heights and sustain maximum data transfer speeds under the heavy computational loads of AI data centers.

“iHBM is the optimal solution for minimizing heat generation developed by combining memory design capabilities and advanced packaging technology,” said SK hynix Vice President Lee Kang-wook. “We will proactively provide the value customers need in the AI environment and further solidify our leadership in AI memory.”

SK hynix plans to apply iHBM technology from next-generation products, such as HBM5, to meet the thermal management requirements of high-performance computing (HPC), AI data centers, and other ultra-high-density and ultra-high-bandwidth environments, thereby improving overall system stability and efficiency.

Heat management is one of the biggest challenges facing HBM (High-Bandwidth Memory) technology. Unlike conventional memory, HBM achieves massive bandwidth by vertically stacking multiple DRAM dies, dramatically shortening the distance data must travel and enabling far higher transfer speeds with better power efficiency.

To minimize latency and feed AI processors fast enough to avoid bottlenecks, HBM is placed extremely close to the GPU or AI accelerator on the same package, connected through a high-speed silicon interposer. However, this dense arrangement also creates severe thermal problems.

The Die-to-Die Physical Layer (D2D PHY) — the ultra-high-speed interface linking the processor and HBM stacks — continuously moves terabytes of data per second. As thousands of signaling lanes and billions of transistors switch at extremely high frequencies, switching losses, leakage current, and electrical resistance generate substantial heat.

The problem is compounded by the processor itself, which already produces enormous amounts of heat. With the HBM stacks packed tightly around the processor, heat accumulates rapidly in a very small area. When temperatures exceed safe limits, the system automatically reduces clock speeds and voltages through thermal throttling to prevent physical damage, lowering overall performance.

SK hynix's new iHBM approach attempts to tackle the problem at the structural level. Unlike conventional HBM cooling designs that primarily dissipate heat indirectly through the core die and surrounding package structures, the company's iHBM architecture instead places Integrated Cooling Elements (ICEs) directly around the D2D PHY region — the exact zone where thermal concentration is most severe. This approach creates a dedicated dissipation path at the source, reducing overall thermal resistance by 30% and allowing the chip to maintain stable operation under the high-temperature, high-pressure conditions that dense AI workloads demand.

SK hynix says the technology can be manufactured at scale using its existing Wafer Level Packaging (WLP) process, which is built on its Mass Reflow Molded Underfill (MR-MUF) packaging technology already used in commercial HBM products. The design is also architecturally compatible with existing System-in-Package configurations, meaning customers can integrate the new thermal capability without major redesigns.

Belgian semiconductor research giant imec this week announced what it describes as the world's first quantum dot qubit device fabricated using High-NA EUV lithography, marking one of the earliest demonstrations of advanced quantum hardware built using the semiconductor industry's most cutting-edge manufacturing technology. The device, unveiled at ITF World in Leuven on May 19, uses silicon quantum dot spin qubits — nanoscale structures that trap individual electrons and exploit their quantum spin states to store information — patterned at gate gaps of barely 6 nanometers.

At first glance, the announcement may seem like another entry in the increasingly crowded quantum computing race. The actual significance, however, has less to do with raw quantum performance and more to do with manufacturing — arguably the single biggest obstacle standing between experimental quantum systems and commercially useful quantum computers.

Qubits can theoretically solve computational problems that would take classical supercomputers longer than the age of the universe, but only at a scale nobody has yet achieved. With several advancements in the physics side of quantum computing, manufacturing now represents the major limitation. Imec claims to have addressed that directly by using the semiconductor industry's latest and most advanced lithography tool to fabricate silicon quantum dot spin qubits with tolerances compatible with industrial chip production for the first time. If that holds up, the implications for quantum scaling could be tremendous. It’s a significant step towards quantum computing, but we are still not quite there.

Manufacturing, not physics, is now quantum computing’s major bottleneck

Quantum computing’s central problem is no longer simply whether researchers can create functioning quantum systems. Our detailed quantum computing roadmap analysis showed that companies including IBM, Google, IonQ, Quantinuum, D-Wave, PsiQuantum, and others have already demonstrated a wide range of working architectures, from superconducting qubits to trapped ions and photonic systems. The problem is scaling those systems into reliable machines containing millions of reproducible, controllable qubits. — the level widely considered necessary for commercially useful, fault-tolerant quantum computers. The most ambitious industry players' roadmaps place that milestone around or beyond 2030, further proving that manufacturing, not physics, is the current hindrance.

Imec's technology directly targets that problem. The company’s approach centers on silicon quantum dot spin qubits, often described as “industry qubits” because they can, in theory, leverage conventional CMOS semiconductor manufacturing infrastructure. Instead of relying on exotic standalone fabrication ecosystems, silicon quantum dots attempt to piggyback on decades of transistor scaling and wafer manufacturing expertise already developed by the semiconductor industry.

The qubits themselves work by trapping individual electrons inside nanoscale silicon structures. The electron’s quantum “spin” state stores information, while surrounding metallic control gates manipulate interactions between neighboring quantum dots. While the concept may sound deceptively straightforward, its fabrication is exponentially more complex.

Quantum dot performance depends heavily on the spacing between those control electrodes. As neighboring quantum dots move closer together, coupling strength rises exponentially, improving controllability and interaction fidelity. But achieving those gains requires reliably patterning gaps measuring only a few nanometers across an entire wafer.

Imec says it fabricated functioning qubit arrays with gaps of barely 6nm between plunger and barrier gates, using High-NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography, the industry’s latest precision lithography technology.

High-NA EUV: not yet standard, already essential

High-NA EUV is the semiconductor industry’s next major lithography transition, developed primarily for future sub-2nm processors, advanced AI accelerators, and dense memory technologies. The systems, built by ASML, improve patterning precision by increasing the optical system’s numerical aperture, allowing dramatically smaller and more accurate features to be printed onto silicon wafers than current EUV systems can reliably achieve. The key difference between the new High NA EUV and conventional EUV is the increase in numerical aperture from 0.33 to 0.55

The machine weighs around 150 tons, spans the length of a double-decker bus, and requires an entirely redesigned optical system with mirrors twice as large and ten times heavier than those in standard EUV tools, polished by ZEISS to atomic precision. The technology is a ground-up engineering effort years in the making.

Even among mainstream semiconductor manufacturers, High-NA EUV technology is only just entering commercial deployment. Intel installed the industry's first commercial High-NA EUV lithography tool late last year, while imec received the technology in its 300mm cleanroom in March 2026 — two months ago. The machines themselves reportedly cost hundreds of millions of dollars apiece and represent one of the most complex manufacturing systems ever built.

The fact that imec has already applied High-NA EUV to quantum hardware — before most chipmakers have even integrated it into standard production flows — suggests quantum computing may be converging directly with the semiconductor industry's existing manufacturing roadmap rather than evolving as a separate technology stack entirely. That possibility can have significant implications. Instead of waiting for quantum-specific fabrication ecosystems to mature independently, silicon quantum hardware may be able to exploit the extremely advanced infrastructure of a multibillion-dollar industry, potentially significantly compressing quantum computing timelines. Although this does not mean manufacturable quantum computers are suddenly close.

The implications of imec’s achievement for quantum computing and the semiconductor industry

While imec's prototype remains far from a large-scale fault-tolerant quantum computer, it still represents a functioning silicon quantum dot spin qubit device — a type of quantum hardware designed to store and manipulate information using the quantum spin states of trapped electrons. These qubits belong to a class of quantum architectures viewed as promising candidates for tackling computational problems that quickly overwhelm even the world's most powerful supercomputers due to their enormous combinatorial and quantum-mechanical complexity.

Silicon quantum dot spin qubits are particularly notable among those candidates because their production process is compatible with standard CMOS semiconductor manufacturing — the same ecosystem that produces CPUs, GPUs, and AI accelerators. It is worth clarifying that imec's breakthrough lies in the manufacturing process, not in the qubit architecture itself. Silicon quantum dot spin qubits already exist and have been an active area of semiconductor and quantum research for over a decade. Previous devices have been demonstrated using conventional lithography at the laboratory scale. While that proved the architecture works, it stopped well short of what industrial scaling demands: consistent, reproducible fabrication at nanoscale tolerances across an entire wafer.

That is the gap imec is now targeting. By demonstrating that High-NA EUV lithography can pattern silicon quantum dot spin qubits at gate gaps of just 6 nanometers on a 300mm fab-compatible process, imec has shown for the first time that the semiconductor industry's most advanced manufacturing tool can be brought to bear on this class of quantum hardware — moving the architecture from lab-scale demonstration toward something that could eventually be manufactured like a chip.

If sufficiently scaled and stabilized, silicon quantum dot spin qubit systems could accelerate progress in molecular simulation, advanced materials discovery, pharmaceutical research, cryptography, logistics optimization, and complex physical-system modeling — fields whose computational demands can be prohibitively difficult for classical supercomputers, regardless of how powerful those machines become.

Rather than serving consumers directly, these systems would likely be deployed by hyperscalers, governments, national laboratories, pharmaceutical firms, and defense organizations tackling computational problems where even incremental breakthroughs could have massive scientific or strategic consequences. The technology would most probably be accessed through cloud-based quantum infrastructure rather than on-premises hardware.

Huawei has announced a new chip design framework aimed at closing the technology gap with global semiconductor leaders like TSMC and Nvidia, targeting '1.4nm-class' transistors and a 55% increase in transistor density. The firm also unveiled a new 'Tau Scaling Law' that's designed to replace Moore's Law for future chip scaling. Unveiled at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai on Monday, this new design method is intended to circumvent strict US trade sanctions. It allows the company to develop high-performance smartphones and AI processors without relying on restricted Western manufacturing equipment like extreme ultraviolet (EUV) lithography machines.

Delivering a keynote address at the symposium, He Tingbo — a Huawei board member and President of its semiconductor division, HiSilicon — unveiled the company's new, proprietary “LogicFolding” architecture. The cutting-edge design blueprint is built directly upon the newly introduced Tau Scaling Law.

He revealed that Huawei has spent the last six years quietly refining the methodology, secretly designing and mass-producing 381 chips based on the principle. The company will debut the LogicFolding architecture in flagship Kirin smartphone processors this autumn.

Traditional chipmaking relies on Moore's Law (geometric scaling), which involves shrinking physical transistor sizes. However, as US sanctions blocked China's access to the extreme ultraviolet lithography machines required to implement this approach, HiSilicon has pivoted to a completely different methodology: the Tau scaling law.

Tau Law is a "temporal scaling" framework that prioritizes signal speed, optimizing how fast data moves across a system rather than how small the components are. To execute this theory on a commercial level, Huawei engineered the LogicFolding architecture, a blueprint that physically folds and stacks logic circuits into a dual-layer framework. By drastically shortening internal wiring to eliminate signal delay, the resulting hardware achieves a 55% increase in transistor density and a 41% boost in power efficiency, enabling Huawei to build cutting-edge processors that rival foreign counterparts without Western equipment.

The company’s upcoming Kirin smartphone chips — highly anticipated for the flagship Huawei Mate 90 series — will be the first commercial processors to feature the LogicFolding architecture. The company aims to scale this architecture to its Ascend AI processors and high-capacity data center clusters by 2030. This will provide local alternatives to restricted Nvidia hardware. By 2031, Huawei confidently projects it can design high-end chips with a transistor density equivalent to a 1.4-nanometer (nm) process.

Huawei's announcement comes as China continues its push to end dependence on foreign semiconductor players — amid sanctions and concerns about over-reliance — by aggressively investing in domestic companies and alternative technologies.

Following the announcement, shares for China's largest contract chipmaker, SMIC, surged by 7.6%. The breakthrough is a major symbolic and practical win for Beijing’s push toward complete technological self-sufficiency. While global foundry leader TSMC expects to mass-produce true 1.4nm chips by 2028, Huawei's alternative path means China can dramatically close the performance gap by packaging and structuring chips differently — significantly mitigating the impact of the US clampdown.

Samsung's tentative profit-sharing deal with its largest labor union averted an 18-day strike just days ago, but the agreement has triggered internal conflict that’s now threatening the company's ability to ship AI memory on schedule, according to a Seoul Economic Daily report published yesterday.

It’s understood that meetings are being canceled across Samsung's non-memory and shared business units. That work negligence has become widespread in the foundry and TSP (Test & Package) divisions, which handle the back-end packaging and testing work essential to producing high-bandwidth memory. One source told the publication that “decision-making on major projects has come to a complete halt,” as inter-departmental resentment deepens over the bonus gap.

This disruption in TSP could be especially consequential for Samsung as it looks to ramp up its HBM4 production for Nvidia’s next-gen Rubin AI accelerators. TSP uses an integrated turnkey system that routes chips through its own foundry and packaging lines, and any slowdown in back-end operations will directly constrain HBM output as all three major memory producers are racing to fulfill hyperscaler orders.

Another source speaking to the publication warned that continued negligence on production and verification lines could damage Samsung's customer relationships and jeopardize delivery commitments.

The root of the conflict is a massive disparity in proposed payouts. Under the tentative deal, employees in Samsung's memory division stand to receive bonuses of roughly 600 million won (~$400,000). In contrast, workers in the DX (Device eXperience) division, which covers smartphones, TVs, and home appliances, would receive approximately 6 million won (~$4,000). The deal allocates 10.5% of the semiconductor division's operating profit as stock-based bonuses, with an additional 1.5% in cash.

Workers outside the memory unit have pushed back hard, with a smaller union representing DX employees filing a court injunction this week to block the larger, chip-dominated union from handling collective bargaining. That union's membership surged from 3,000 to nearly 13,000 after the deal was announced. Separately, the Korea Shareholder Action Headquarters has threatened legal action, arguing the profit-linked bonus structure requires shareholder approval under Korean law.

Union members began casting electronic ballots on Friday, with voting open through May 27. Ratification requires participation from more than half of eligible members and a majority yes vote, but approximately 43,000 non-memory union members within the DS division could swing the outcome. According to reports from Korea, internal message boards have shown strong opposition from workers who view the deal as favoring the memory unit at everyone else's expense.

Samsung's semiconductor CEO, Jun Young-hyun, urged employees in an internal memo Thursday to move past the conflict, but the dispute now poses a tangible risk to Samsung during what Bloomberg estimates will be a record year, with 2026 operating profit projected at 330 trillion won (~$218 billion).

AMD has announced that its 6th Gen EPYC processor, codenamed Venice, has entered production ramp on TSMC's N2 (2nm-class) process technology in Taiwan. The chip, which packs up to 256 Zen 6 cores and claims a 70% compute performance gain over the current EPYC Turin lineup, is the first high-performance computing product in the industry to reach production on N2. AMD also announced a follow-on processor called Verano and said it plans to eventually produce Venice at TSMC's Arizona campus as well.

TSMC began volume production on its N2 node late last year, and the foundry is ramping five separate 2nm fabs this year to meet what it has described as record demand. Apple reportedly secured the lion’s share of initial N2 capacity for consumer silicon, but it’s AMD with Venice that’ll be the first HPC product on the node. Server and data center dies are larger and architecturally more complex than smartphone SoCs, and getting them through yield qualification on a brand-new process is a much bigger challenge.

"As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster," said Dr. Lisa Su, chair and CEO of AMD, in the company's press release.

Venice brings the new SP7 socket, up to 16 memory channels delivering 1.6 TB/s of per-socket bandwidth, and doubled CPU-to-GPU bandwidth that likely indicates PCIe 6.0 support. AMD previewed these specs at its Advancing AI event last year and at CES in January, but this announcement puts the chip on track for commercial shipments later this year.

AMD could face limited next-gen competition in the server market right now, with Intel’s Diamond Rapids — the P-core Xeon 7 family that would be Venice's direct counterpart — rumored to be delayed to mid-2027. Intel's only new server product expected this year is Clearwater Forest, an E-core design built on Intel 18A with up to 288 cores. Clearwater Forest is optimized for high-density deployments at scale, not the high single-thread and general-purpose performance segment that Venice is targeting.

AMD already holds a record 46% server CPU revenue share as of Q1 2026, according to Mercury Research, up from roughly 40% at the company's Financial Analyst Day in November last year. Venice will likely extend that momentum into a segment where Intel will be relying on its existing Granite Rapids Xeon 6 lineup for at least another year.

AMD also confirmed Verano, another 6th Gen EPYC processor built on TSMC 2nm and optimized for performance-per-dollar-per-watt. AMD also says it plans to ramp Venice production at TSMC’s Arizona facility. That’s likely referring to Fab 21 Phase 3, which broke ground last April and is slated for N2 and A16 processes. Volume 2nm production isn’t expected before 2028 at the earliest here, however.

Lip-Bu Tan, chief executive of Intel, this week confirmed that the company had already begun to work on its 10A and 7A fabrication technologies that will succeed Intel's current-generation 18A and next-generation 14A production nodes sometime in the next decade. Both 10A and 7A processes will presumably be able to use ASML's EUV lithography tools with high numerical aperture optics (High-NA), which will first be used for 14A.

"Now I am starting to work 10A, 7A, the roadmap," said Lip-Bu Tan at JP Morgan's Global Technology, Media and Communications Conference. "People do not [simply] go to you, they are looking for the roadmap for the future. So we want to build a long-term business. […]."

Tan emphasized a long-known business practice that ambitious roadmaps that are properly executed are as important as competitive products or fabrication technologies, as many companies do not just buy products, but roadmaps, as they prefer to work with suppliers for years to come. That said, Intel must offer its partners long-term roadmap visibility, so it has to work on technologies that are years from commercialization.

When it comes to Intel's 14A, its development is proceeding as planned, with version 0.5 of the process design kit (PDK) already available and version 0.9 of the PDK due in October.

"Clearly, the 14A, and we announced in Q1, we have v0.5 PDK so that they can do the test chip to look at our yield and see whether they can, over time, to really design their product and fabricate with us," Tan said. "The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Tan says multiple customers have expressed interest in 14A, though Intel has not yet disclosed them.

"We have multiple customers engaged with us [with 14A], and to really define what product, what foundry location wants to be, what kind of capacity we need," Tan said. "I do not disclose the customer. If the customer wants to disclose, we will support that."

As for Intel's 14A timeline, Intel expects risk production in 2028 and then volume production in 2029, which is about the time when TSMC begins to volume produce chips on its A14 fabrication technology.

Three things must be kept in mind here. Firstly, TSMC's A14 is not a direct rival for Intel's 14A as the latter features backside power delivery and is better suitable for high-end data center-grade processors. Secondly, TSMC is said to start making chips using A14 in late 2028, and the company tends to initiate high volume manufacturing (HVM) with very high yields and volumes. By contrast, Intel initiates volume production at development fabs, and it takes the company some time to reach comparable yields and volumes. Thirdly, Intel's 14A will be one of the first nodes to be compatible with High-NA EUV lithography systems (for select layers) and will be the first production node to have the capability to use such scanners for high-volume manufacturing.

Insertion of all-new High-NA EUV tools — along with new photoresists, new photomasks, new pellicles, new metrology tools, new design rules, new computational lithography flows, and a lot of other innovations — is not going to be easy for Intel, so the company is hard at work working with both ASML and partners to ensure that the new ecosystem is ready for prime time. Coincidentally, Christophe Fouquet, the head of ASML, reportedly said that the first test chips made using these High-NA EUV tools will emerge in the coming months, though he did not specify at which vendor or facility.

SMIC founder Richard Chang and AMEC chairman and CEO Dr. Gerald Yin appeared together on CCTV's Dialogue program on May 17th to make a coordinated case for Chinese chipmakers to give homegrown equipment more production-line trial time, according to DigiTimes.

The strange joint TV appearance came days after Chinese industry figures told Securities Times that the next three to five years will determine whether domestically built tools can move from functional prototypes to equipment that meets the yield, throughput, and uptime demands of volume manufacturing.

China's semiconductor equipment vendors collectively posted record revenues in 2025, but profitability is under pressure from domestic price competition, and the hardest remaining bottleneck, lithography, has no credible near-term domestic solution. U.S. export controls, meanwhile, continue to tighten.

Record revenues, falling margins

China's equipment industry grew incredibly fast last year. AMEC, the country's leading etch-tool maker, reported full-year revenue of $1.74 billion USD (12.38 billion RMB), up 36.6% year-on-year, with net profit totaling around $310 million (2.11 billion RMB), up 30.6%.

Naura Technology, the broadest-line domestic supplier, posted $3.91 billion (27.14 billion RMB) in revenue across just the first three quarters, while Piotech, which specializes in thin-film deposition, roughly doubled its nine-month revenue to $617 million (4.22 billion RMB). ACM Research, the U.S.-listed cleaning-equipment maker with the bulk of its operations in Shanghai, booked $901.3 million for the full year, up 15.2%.

Despite these lofty revenues, margins moved in the opposite direction: AMEC’s full-year 2025 gross margin fell 1.9 percentage points to 39.2%, with the third quarter alone dropping 5.8%, and ACM Research's gross margin slid from 50.1% in 2024 to 44.4% in 2025. The pattern was consistent across the sector.

This squeeze is coming from domestic competition rather than foreign pressure. With U.S., Japanese, and Dutch export controls restricting shipments of advanced tools to Chinese fabs, domestic vendors are competing fiercely with each other for orders that previously went to Applied Materials, Lam Research, and Tokyo Electron; Needham & Co. analyst Charles Shi recently told Nikkei Asia that this internal price war is the primary driver of margin erosion.

Chinese fabs are now thought to be sourcing roughly 35% of their equipment domestically, up from about 25% a year ago. Beijing's informal target for new fab construction is 50% domestic content, a threshold that YMTC's third Wuhan fab has reportedly already cleared, but the gains are concentrated in mature-node tool categories. Etch localization at mature nodes sits at roughly 50% to 60%, and resist stripping exceeds 80%. According to data from Ijiwei thin-film deposition runs from 20% to 30%, and lithography sits below 5%.

A public appeal

The Chang-Yin CCTV appearance was ultimately a strange, public, state-sanctioned appeal to Chinese fabs. Chang argued that domestic equipment can’t improve without real production-line trials and said fabs should start with small wafer batches of up to 100 wafers before scaling up to limit the risks of early adoption. Meanwhile, Yin said that Chinese customers still default to foreign tools out of habit, and even new systems from the world's largest equipment vendors typically require two to three years of tuning when first deployed at leading fabs.

Industry-standard timelines for qualifying a new etch or deposition tool on a leading-edge production line run 18 to 24 months from installation to qualified production status. The process tests reliability, particle contamination, process drift, and throughput under sustained operation, not just whether the tool can produce a working wafer under controlled conditions.

An example highlighted by Yin is that of AMEC, which, in December 2023, decided to enter the large flat-panel display equipment segment, a category he said was previously 100% imported. The tool in question weighs roughly 150 tonnes and measures 15 by 15 meters, but AMEC reportedly built a working prototype in 12 months, met a customer's next-gen specifications four months later, and shipped the tool to a production line within 18 months total. Needless to say, those claims haven’t been independently verified and shouldn't be taken at face value.

AMEC also claims SMIC has purchased at least 800 of its tools, a figure Chang cited on the same broadcast, and that its etch technology is used in TSMC's supply chain at nodes from 65nm down to 5nm and 3nm. TSMC hasn’t publicly confirmed the scope of AMEC's role in its production lines, however.

Recent disclosures show that SMIC faced yield losses tied to equipment maintenance and validation stalls in 2025, the exact production-line qualification problem Chang acknowledged on CCTV. The foundry has reportedly acquired some foreign tools that are sitting idle because spare parts and field service from sanctioned suppliers are no longer available under normal terms.

Still no lithography solution

None of China's equipment progress addresses the most critical chokepoint: lithography. Shanghai Micro Electronics Equipment (SMEE), the only Chinese supplier of lithography scanners in any volume, produces a 90nm-class ArF system. While a 28nm-class tool has been reported in development, it’s not confirmed in mass production, and details are scarce.

One project to watch, however, is the Shanghai Yuliangsheng immersion DUV scanner under test at SMIC. That tool, linked to Huawei-backed SiCarrier under the codename "Mount Everest," resembles ASML's Twinscan NXT:1950i from 2008, two product generations behind the NXT:2000i used in current 7nm and 5nm production. SMIC is thought to be targeting the Yuliangsheng tool for its 28nm production flow in 2027, but sub-10nm lithography on purely domestic equipment is unlikely before 2030.

In Q3 2025, 42% of ASML's system sales by revenue went to Chinese customers, confirming that Chinese fabs are buying DUV scanners as fast as current export rules allow. But Washington is working to narrow this window further, with the MATCH Act, which was introduced last month. It names and designates the likes of AMEC, Naura, Piotech, ACM Research, SiCarrier, and SMEE, among SMIC, YMTC, Hua Hong, CXMT, and Huawei, as “Covered Facilities” and would impose a country-wide prohibition on exporting DUV immersion lithography tools to China.

The House Foreign Affairs Committee passed the bill 36 to 8 in late April after removing a proposed ban on cryogenic etch tools, which would have affected Lam Research and Tokyo Electron. The DUV immersion ban remains in the bill as it heads toward a Senate floor vote. As of the time of writing, it’s currently sitting in a Senate Committee.

China criticized the legislation less than a week before the duo’s state-sanctioned television address to chipmakers. The broadcast itself is ultimately best viewed as part of Beijing's response: a coordinated message that domestic fabs need to accelerate qualification of Chinese-built alternatives before the remaining supply lines are cut.

Russia’s Mikron is earning a bit of cash on the side by selling picture-framed test wafers as souvenirs. There are 12 designs in the product gallery, all priced at 12,500 rubles (~$170), with various frame backgrounds and commemorative texts. Mikron says supplies of these exclusive silicon wafer artworks are limited.

Spotted by Dmitrii Kuznetsov @torgeek on X, some of these wafers will feature the AMUR MIK32 RISC-V chip, produced in Russia since 2022. The computer and data science enthusiast also notes that Mikron is busy “preparing to release a new RISC-V — MIK32-2.” (machine translation)

The souvenir product pages also reveal that the framed 200mm wafers may also come packing between 30 to 120,000 chips, depending on the product. For example, one of the wafer designs may be full of transport card chips as used by the Moscow Metro.

Buyers visiting the Mikorn souvenir shop pages will choose their framed wafer by selecting the frame color and/or theme. For example, there are products with simple black or white frames. But there are other designs with lace, paisley, or even an outer space theme. What kind of wafer you get with your choice of frame, appears to be pot luck.

We used machine translation on the new 2026 edition wafer souvenirs, to see what the information panel to the lower left of the frame said. The top row of the table reads: 2026 | Made in Russia | Techno exclusive | Russian chips | 200mm. Moving to the second row: Silicon wafer with integrated circuits | The satellite plate is used in the technological process for quality control at all stages of microcircuit production.

If you manage to buy one of these Russian semiconductor industry souvenirs, you will need a space on your wall for a 270 x 270 x 15mm (10.6 x 10.6 x 0.6-inches) frame, which weighs 365g (~13 ounces). I think they look smart, but it would be even better if you had a piece of tech that actually used one of the chips from the wafers for your wall presentation.

If you have followed the link to Mikron’s souvenir shop and had a browse around, like us, there are a few other interesting trinkets to see. A much cheaper souvenir flagged as ‘new’ is the small tube of air from the firm’s NWP clean room in Zelenograd, priced at around $2. Elsewhere there are gift shop trinkets of the style you might find anywhere, like dolls, mugs, magnets, and puzzles.

President Donald Trump described a pending $14 billion arms sale to Taiwan as a "very good negotiating chip" with China in a Fox News interview taped in Beijing on Friday, saying he had not yet approved the deal and was holding it "in abeyance." The package, which includes PAC-3 MSE interceptors and NASAMS air defense missiles, had been ready for Trump's signature since Congress approved it in January.

Trump's remarks came at the close of a two-day summit with Chinese President Xi Jinping, during which Xi warned that Taiwan is "the most important issue" in the bilateral relationship and that mishandling it could lead to "clashes and even conflicts." Trump told reporters aboard Air Force One that the two discussed Taiwan arms sales "in great detail."

Karen Kuo, spokesperson for Taiwanese President Lai Ching-te, called China the "sole destabilizing factor" in the Indo-Pacific and said arms sales between the U.S. and Taiwan reflect Washington's security commitment under the Taiwan Relations Act.

Secretary of State Marco Rubio told NBC News that U.S. policy toward Taiwan is "unchanged" and called any Chinese attempt to take the island by force "a terrible mistake." A bipartisan group of U.S. senators had written to Trump ahead of the trip, urging him not to treat Taiwan's defense as a bargaining tool, stating that American support for the island "is not up for negotiation."

Trump, however, framed the situation in transactional terms to Fox News, saying that when looking at the odds, “China is a very, very powerful, big country. That's a very small island," adding, "I do say this: Taiwan would be very smart to cool it a little bit."

Taiwan produces more than 90% of the world's most advanced semiconductors through TSMC, which fabricates chips for Nvidia, AMD, Apple, and Qualcomm. That concentration of manufacturing capacity is the foundation of what analysts and Taiwanese officials call the island's "silicon shield," the idea that global dependence on Taiwanese chips gives allied nations a strategic incentive to defend it.

Trump's willingness to treat Taiwan's military support as leverage over Beijing could, however, test that assumption. The U.S. struck a trade deal with Taiwan earlier this year that commits Taiwanese firms to over $500 billion in U.S. semiconductor investment, and TSMC is already building $165 billion in Arizona fab capacity. But reshoring chip production takes years, and the most advanced nodes remain in Taiwan under legal restrictions designed to preserve that shield.

In 2023, U.S. intelligence officials privately briefed the CEOs of Nvidia, Apple, and AMD that China could invade or blockade Taiwan by 2027. Trump announced an $11 billion weapons package for Taiwan in December 2025, but has yet to begin fulfilling it.

All three leading-edge foundries — Intel Foundry, Samsung Foundry, and TSMC — have initiated mass production of chips using 2nm-class process technology. Samsung was the first one to start production using its SF2 node (though it could be argued that this is a rebadged SF3P) around mid-2025, Intel followed suit with its 18A node in November (albeit at development lines in Oregon, not production lines in Arizona), and TSMC initiated high-volume manufacturing using its N2 process at two volume fabs in Taiwan in December. We outline what's next for these three leading-edge foundries.

The current state of the market

The amount of capital, expertise, and experience required to develop leading-edge process technologies and build high-volume fabs supporting advanced nodes is so high that only three companies in the world are currently capable of producing them. Companies like Rapidus have yet to prove they are a viable leading-edge chipmaker. Meanwhile, all three leading foundries are transitioning from traditional node scaling to a more segmented, architecture- and product-driven approach, but are doing so with different priorities.

TSMC is focused on predictable scaling, combined with aggressive specialization, which is why its roadmap is split into high-performance computing-oriented technologies with backside power delivery network (BSPDN) and cost/density-optimized nodes without it.

Samsung has a wide range of node variants, though it is currently more focused on yield improvement, rather than on scaling, which is why its roadmap appears more iterative than breakthrough-focused. This is perhaps why it is behind competitors with its BSPDN implementation.

Intel seems to be pursuing the most aggressive technological roadmap with a conjoined implementation of gate-all-around (GAA) RibbonFET transistors and PowerVia BSPDN, rapid iteration, and the aggressive pursuit of High-NA EUV lithography in 2027 – 2028, years before its rivals.

Intel Foundry: The most ambitious chipmaker

Being a new player in the foundry market and a large integrated design manufacturer (IDM), Intel is pursuing a multi-faceted strategy aimed at addressing the needs of its own products, as well as attempting to land customers that do not necessarily require leading-edge process technologies.

Intel's roadmap is the most ambitious, but arguably the most volatile one, when compared to the plans of other leading foundries. On the one hand, Intel needs the best fabrication technologies to differentiate its own consumer and data center products. To that end, with its 18A and subsequent process technologies, Intel bet on the simultaneous implementation of GAA transistors and a BSPDN to maximize performance, power efficiency, and transistor density. On the other hand, since Intel has zero customers from the automotive and smartphone sectors, it does not have any technologies tailored specifically for these applications.

Intel's 18A is probably the most important technology for the company in years, as it will return production of the company's consumer CPUs back to its own fabs, something that promises to greatly improve margins. Although the company is in the process of improving yields on 18A and current 18A volumes are not significant, Intel is already preparing follow-on refinements such as 18A-P (with enhanced performance and improved power efficiency) and 18A-PT (which supports through silicon vias (TSVs) and can be used for 3D-integrated systems-in-package).

Beyond that, Intel is targeting 14A and 14A-E for 2027 ~ 2028 production readiness and an early ramp. The nodes will introduce Intel's 2^nd Generation RibbonFET GAA transistors, revamped PowerDirect backside power delivery, and Turbo Cells to improve the performance of critical data paths.

These will be the company's first nodes to use High-NA EUV lithography, at least for some 14A and 14A-E variants, which will be another attempt to introduce a technology that will differentiate Intel compared to competing nodes. Intel has said that the interest in 14A from external customers is significant. Musk's Terafab project is set to make use of Intel's 14A, as a licensee, but not as a customer.

At the same time, Intel is heavily relying on node variants to address different use cases, including performance enhancements (P), feature enhancements (E), and through-silicon via support (T). These process technologies are required to enable Intel to build custom multi-chiplet products for consumer and data center applications, which directly support its strategy to produce most of its products at in-house fabs.

Intel's roadmap also includes continued investment in mature nodes such as Intel 16 and UMC 12 as the company pursues a strategy to capture demand outside leading-edge applications, to ensure steady revenue streams.

While Intel's plans are aggressive and ambitious, the abrupt cancellation of 20A in late 2024 highlights the execution risks associated with such a roadmap.

Samsung Foundry: When yields matter more than nodes

Samsung was the first company to adopt GAA transistors with its SF3E technology in 2022, three years before Intel and TSMC. However, low and unpredictable yields have limited the adoption of this technology to niche applications like cryptocurrency mining ASICs. While SF3 was more mature, it was still adopted by select applications, mostly internally. As a result, the highest-performing chips made by Samsung are produced using FinFET-based SF4P and SF4X, which puts the company behind its rivals.

For now, reducing defect density, increasing yields, and ensuring stable yields are the top priorities for Samsung. Last year, it began making mobile system-on-chips (SoCs) using its SF2 node (which it calls the 1^st Generation 2nm GAA process), but among the major goals for the company for this year is to ramp up '2^nd Generation 2nm [SF2P] and prepare performance and power-optimized 4nm process,' which suggests limited adoption of SF2. The fact that the low-power 4nm-class node will be a major workhorse for the company. The company's roadmap also indicates SF2X (HPC-oriented) in 2026 as well as SF2A (for automotive applications) and SF2Z (SF2X with BSPDN) in 2027, though we can only wonder whether these nodes will be widely adopted.

Nonetheless, Samsung's iterative approach to the evolution of its SF2 nodes (SF2=>SF2P=>SF2X=>SF2X with backside power) is evident, which gives us hope that the company's yields will gradually improve.

Samsung's next major node will be SF1.4, a 1.4nm-class process technology optimized for consumer and smartphone applications, which won't feature backside power delivery. Samsung's slides put SF1.4 above the SF3 and SF2 families, which may suggest that this manufacturing process will feature some major enhancements, such as a new GAA transistor design or other major refinements. Samsung expects to mass-produce chips on its SF1.4 technology in 2027, so it can formally leave Intel and TSMC behind with its 1.4nm node.

A big question lingers, and that's whether Samsung plans to finally start using pellicles with its EUV lithography tools starting with SF1.4, or later. A lack of pellicles greatly increases the number of potentially yield-killing stochastic mask-borne defects, which are increasingly dominant at the 2nm and are getting much worse at thinner nodes.

TSMC: New technologies like clockwork

TSMC's roadmap remains the most structured and execution-focused among the three. The world's largest contract chipmaker initiated mass production of chips using its N2 process technology — its first node with GAA nanosheet transistors — at two fabs simultaneously late last year in a bid to meet demand from a wide range of applications, starting from Apple's smartphones and all the way to AMD's server-bound EPYC 'Venice' CPUs. Initiating volume production at two fabs simultaneously is something that rarely happens in the industry, though it looks like structural changes caused by demand from the AI segment are changing many things in the industry.

TSMC is on track to start making chips using performance-enhanced N2P with traditional frontside power delivery and A16 technology that adds backside power delivery on top, a split which highlights TSMC's increasingly segment-specific approach to leading-edge technologies.

Going forward, the company is set to continue offering advanced technologies with and without BSPDN, as this feature may be too expensive for consumer and smartphone applications, but is clearly valuable for heavy-duty data center processors. For example, A14 will emerge as a smartphone-oriented node in 2028, but then will re-emerge as a data center-oriented node once it gets BSPDN in 2029.

In addition, the company will continue to offer mainstream nodes like N4C, N3C, and eventually N2C for applications that are more sensitive to costs. Automotive-specific nodes (N7A, N5A, N3A) will lag leading-edge nodes by one to two generations, as they prioritize reliability and longevity over performance and transistor density.

TSMC's segmentation and yearly cadence for advanced manufacturing nodes enable the foundry to address the most demanding clients like Apple, AMD, Intel, Nvidia, or Qualcomm with competitive process technologies. Ultimately, such cadence and a wide range of nodes reinforce TSMC's position as the most predictable and commercially disciplined foundry.

Fractured futures

To sum things up, TSMC continues to bet on execution discipline and segmentation as it ramps its 2nm-class node at two fabs to meet overwhelming demand from a variety of applications, starting from humble cell phones all the way to heavy-duty servers.

Intel leads in architectural ambitions, as currently it is the only company that uses a process technology that features both gate-all-around transistors and backside power delivery. However, the company admits that its yields will only get to world-class level by 2027, which likely makes Intel's 18A node significantly less attractive to demanding customers.

Samsung sits somewhere in the middle, offering a wide variety of process technologies for different applications, but the company's yields with GAA-based nodes have been a challenge, which is why the firm is now focused on yield increases rather than on breakthroughs, so it does not attempt to leapfrog its competitors.

TSMC's board of directors on Tuesday approved a capital injection of $20 billion into the company's wholly owned subsidiary TSMC Arizona, which will be used to continue the expansion of the Fab 21 site. While the allocation proves that the project is moving smoothly, the company is still facing multiple challenges in Arizona, including labor and water shortages, according to a report from Taipei Times.

The approval of a capital injection is a formal procedure that grants TSMC management the right to use the money for the expansion of Fab 21, and while it is an important milestone, it is a formality, as this is a part of the $165 billion expansion plan that the company introduced last year. What is more important is that TSMC's Fab 21 earned $514 million in profit last year, according to Yeh Chun-Hsien, Taiwan National Development Council (NDC) Minister. Making a profit in a new fab in the first year of full-scale operation is quite a big deal for foundries.

TSMC informed Taiwanese officials that the startup phase of its first Arizona fab proceeded more smoothly than originally projected, which strengthens confidence in the long-term viability of the site, according to Yeh Chun-hsien. At the same time, the company continues to deal with multiple operational difficulties in the U.S., including limited water availability, labor shortages, visa complications for foreign employees, concerns about long-term electricity supply, and regulatory compliance, the report claims.

Water access remains one of the most pressing issues for the project due to the dry and hot climate in Arizona. The company has previously attempted to ease concerns regarding water usage and long-term water supply at Fab 21 by incorporating extensive water recycling and treatment infrastructure capable of supporting advanced fab requirements, though it is unclear whether this has already been done. TSMC hopes to receive assistance from Arizona authorities to ensure reliable water resources for its operations, though environmental and electricity consumption regulations remain concerns as they complicate the project and prevent securing stable power delivery for the site.

Labor availability also remains another major issue. To make matters worse, the company faced difficulties obtaining visas for overseas personnel needed to support operations in Arizona due to the Trump administration's $100,000 fees on the entry of new H-1B visa holders.

In addition, TSMC is encouraging Taiwanese suppliers of semiconductor chemicals and manufacturing equipment to establish operations in the U.S. adjacent to its Arizona campus. However, Yeh noted that enabling broader supplier migration could require adjustments to Taiwan's investment-related laws.

NASA has announced that it has just partnered with Microchip Technology Inc. to build next-generation chips that will power its spacecraft. This project, dubbed High-Performance Spaceflight Computing, aims to build a system-on-a-chip (SoC) that will deliver 100 times the computing capacity of current processors designed for spaceflight. The space agency said that it will come in two flavors — a radiation-hardened version for geosynchronous, deep-space, and long-duration missions and a radiation-tolerant version for low Earth orbit satellites. The former is primarily aimed at supporting missions to the Moon, Mars, and beyond, while the latter is tailored for commercial applications.

The SoC will combine both computing and networking capabilities on a single device, reducing cost and complexity, as well as allowing for better power efficiency. More importantly, it will feature a scalable architecture so operators can turn off unnecessary functions in case they need to conserve energy. We’ve seen NASA selectively turn off instruments on distant spacecraft to reduce power consumption — it executed this procedure on the nearly 50-year-old Voyager 1, which left the solar system in 2012, after scientists noticed an unexpected drop in onboard power levels.

These chips are also designed to scale as multiple units connected via advanced Ethernet. This would give NASA spacecraft massive computing power and even allow for some autonomy, like deciding the speed at which a rover will traverse a landscape or using it to analyze images independently. The Perseverance rover actually used something similar when it paired NASA’s satellite data of the Red Planet’s surface with its panoramic camera and a Qualcomm Snapdragon 801. This allows it to compare what it sees with the information gathered from space so it can determine its location with pinpoint accuracy.

What’s interesting, though, is that NASA envisions that the technology developed from this project will be used in Earth-bound applications, as well. The agency said that its potential applications include “drones, energy grids, medical equipment, communication services, artificial intelligence, and data transmission.” This won’t be the first time that space-borne technology has become ubiquitous on our planet. Several technologies that we use daily were initially built for space exploration, says NASA’s Jet Propulsion Laboratory. This includes camera phones, CAT scans, LEDs, water purification systems, wireless headphones, and memory foam, among others.

Advancements in the semiconductor space have so far been driven by chip makers, like Apple and Nvidia, and fabs such as TSMC. This partnership will allow NASA and Microchip to build technological advancements of their own. But instead of focusing on raw computing power, the two entities will push for reliability, power efficiency, scalability, and security.

Share prices of both Intel and SK hynix have surged following a ZDNet Korea report claiming that SK is conducting R&D with Intel on 2.5D packaging using Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology, with the intention of integrating high-bandwidth memory (HBM) and logic semiconductors. Citing unnamed industry sources, ZDNet Korea reports that the company is also evaluating the materials and components required for production.

SK hynix shares have hit an all-time intraday high of $1,320 (1,946,000 Korean Won) on the Korea Exchange, climbing as much as 14.5% and pushing the company's market cap past $900 billion. Likewise, Intel's share price is up nearly 14% at the time of publication, marking a rise of 229% in the last six months, and 91% in the last month alone.

EMIB connects multiple semiconductor dies using small silicon bridges embedded directly in the package substrate, rather than relying on the large silicon interposer that underpins TSMC's Chip-on-Wafer-on-Substrate (CoWoS) platform. The approach is less expensive per package and avoids some of CoWoS's thermal complexity, though the two technologies target different segments of the market.

Intel Foundry has been actively marketing EMIB and its next-gen variant, EMIB-T, to external customers. Intel CFO Dave Zinsner told the Morgan Stanley TMT conference in March that the foundry division is "close to closing some deals that are in the billions per year in terms of revenue" on advanced packaging alone. EMIB-T, which adds through-silicon vias to the bridge for HBM4 compatibility and higher bandwidth, is expected to enter production fab rollout this year.

TSMC's CoWoS lines, meanwhile, have been massively oversubscribed for more than two years. Nvidia alone is expected to account for roughly 60% of global CoWoS demand this year, with Broadcom and AMD absorbing another 26%. That leaves limited capacity for custom ASIC vendors and smaller AI chip developers, creating an opening for alternative packaging providers.

Intel has already confirmed that some customer designs originally scoped for CoWoS have been ported to EMIB or Foveros, with reports last month that Google and Amazon are among the hyperscalers showing interest in Intel Foundry's advanced packaging capabilities, no doubt at least driven in part by limited access to CoWoS.

SK hynix is already building its own 2.5D packaging facilities independently of Intel. The company recently broke ground on a $3.87 billion advanced packaging plant in West Lafayette, Indiana, which is expected to begin operations in 2028, and approved a ₩19 trillion ($12.9 billion) packaging and test facility in Cheongju, South Korea, in January. If the Intel EMIB partnership materializes, it would give SK hynix an additional packaging pathway alongside its own in-house facilities and its longstanding reliance on TSMC's CoWoS.

Neither SK nor Intel has confirmed the rumors.

Sources close to both Apple and Intel have said that the two companies have reached a preliminary agreement for Intel to manufacture processors for Apple. According to The Wall Street Journal, the two parties have been in talks for over a year, and they’ve been finalizing a formal deal over the past few months. Apple is reportedly looking for alternative fabs to TSMC, as it wants to diversify its supply chain in the midst of ongoing chip shortages, and it seems that this latest development is a confirmation of this report.

It’s currently unclear which chips the U.S. semiconductor company will be making for the largest consumer electronics firm in the world, but it previously made the x86 processors used in Macs and MacBooks from 2006 to 2023. Intel also had the chance to build the A-series chips that Apple used for the iPhone and iPad, but it fumbled the opportunity — with Tim Cook complaining to TSMC founder Morris Chang, “Intel just does not know how to be a foundry.”

Intel apparently learned its lesson, though, as Apple was reportedly considering Intel’s 18A process for its entry-level M-series chips as early as November of last year. Even before this, the two companies were already in discussions about a potential investment into the chip maker, something that President Donald Trump alluded to in early 2026. Aside from Apple, Intel has also received a $5-billion investment from Nvidia and that the two are partnering to develop an x86 RTX SoC for PCs. Elon Musk also tapped Intel for his TeraFab project, which will use the company’s 14A process to make AI chips.

These developments are excellent news for Intel CEO Lip-Bu Tan, who has been working hard to put the company back on track after former CEO Pat Gelsinger announced disastrous results in July 2024. It has also caused the company’s stock price to skyrocket, hitting a record high of $126.23 at the time of writing and beating its former peak during the dot-com boom of 2000. But we'll have to wait for confirmation from the two companies — as neither has officially commented on this news yet — to learn the details of this groundbreaking deal.

Global semiconductor revenue reached $298.5 billion in the first quarter of 2026, up a whopping 25% from the previous quarter, according to the Semiconductor Industry Association (SIA). The SIA believes that the industry is on track to top $1 trillion in sales this year.

That nearly $300 billion of total revenue accounts for sales of logic, memory, analog, mixed signal and other types of chips. In March 2026, monthly revenue stood at $99.5 billion, which represents a 79.2% increase from $55.5 billion recorded in March 2025 and 11.5% higher from February 2026 levels. These monthly figures are calculated as a rolling three-month average by World Semiconductor Trade Statistics.

The Semiconductor Industry Association represents 99% of semiconductor revenue generated by U.S.-based companies and nearly two-thirds of chip firms headquartered outside the U.S., which means that actual sales of chips by various makers was higher than $300 billion in Q1 2026.

Unfortunately, the actual total revenue of semiconductor makers across the world is hard to estimate accurately, as privately owned companies do not share their financial results with the public.

Some companies are partially integrated and sales of their semiconductors cannot be accurately estimated (e.g, Apple, Bosch, Huawei, Sony, and Tesla). Numerous companies from China tend to fly under the U.S. radar and are therefore reluctant to share sales data with the SIA.

On a regional basis, March 2026 sales compared to the same month a year earlier increased by 108.5% in Asia Pacific, 83.1% in the Americas, 74.8% in China, 46.5% in Europe, and 7.4% in Japan. Sequentially, March sales also grew across all key markets, including 13.3% in Americas, 12.7% in China, 9.8% in APAC, 8.4% in Europe, and 7.1% in Japan.

"Global chip sales remain on track to reach $1 trillion in 2026, with Q1 sales significantly exceeding sales in Q4 2025," said John Neuffer, SIA president and CEO. "Strong sales across the Asia Pacific region, the Americas, and China drove global semiconductor market growth, highlighting broad and robust demand for semiconductors and the countless tech products they enable."

Given the current AI-driven semiconductor supercycle and predictions of years-long shortages of critical chip types, total revenues across the industry seem sure to continue their sharp rise, and manufacturers of chips of all types will likely be able to continue cashing in on the AI bonanza with every chip they can make.

Apple is reportedly talking with Intel and Samsung to produce processors for the company as it’s grappling with a shortage of chips for its latest products. According to Bloomberg, Cupertino has had multiple early-stage discussions with Team Blue, while some key Apple executives have also visited a Samsung plant that’s still in development — likely its Taylor, Texas, fab, which is set to start risk production this year.

None of the talks have resulted in any orders, so far, the report states. There have been concerns about using non-TSMC tech in Apple products, especially as it has been producing chips for the iPhone since the A8 used in the iPhone 6 and iPhone 6 Plus. However, the AI infrastructure build-out is negatively affecting the company, with Apple CEO Tim Cook conceding that it’s constrained by TSMC’s supply of advanced chips. Nvidia CEO Jensen Huang said that his company has dethroned the consumer electronics giant as TSMC’s number one customer, and even alluded that Apple might have to pay more for its chips. But even before this, Cupertino has reportedly been considering using Intel’s 18A process to build future M-series chips, especially as global geopolitical events are threatening the stability of the global supply chain.

If we look at Apple’s history, both Samsung and Intel have closely worked with the company for years. The first iPhone, all the way to the iPhone 5S, was powered by Samsung chips, while Macs and MacBooks used x86 Intel processors from 2006 until they were replaced by Apple silicon in 2023. If successful, these talks would resume Apple’s partnership with one (or both) of the companies.

This would be a win for Intel as it’s looking to land a major customer for its foundry business — something that it fumbled in 2011 when Cupertino first approached it for its custom chip needs. A move like this could also help bolster Samsung’s foundry business, as it sits at a distant second place when compared to TSMC. At the same time, it would reduce Apple’s risk of relying on a single supplier for the majority of its advanced chip supply. Even though TSMC’s Arizona plant is ramping up production and it’s estimated that it will deliver 100 million chips for Cupertino this year, it is just a fraction of Apple’s demands, with the majority of its advanced SoCs still expected to come from Taiwan.

Tim Cook has been well aware of the situation with TSMC for years now. He even said in a 2022 all-hands company meeting, “Regardless of what you may feel or think, 60% coming out of anywhere is probably not a strategic position.” This was likely highlighted with the AI-driven chip shortage. “The primary constraint is the availability of the advanced nodes our SoCs are produced on, not memory,” the Apple CEO said during the company’s latest earnings call. “I believe it will take several months to reach supply-demand balance.”

But even if Apple were to strike a deal with both Intel and Samsung today, it will take some time for production to ramp up, and consumers won’t feel its effect for several months, if not a couple of years.

A report by Nikkei Asia claims that China wants 70 percent of the silicon wafers used by its chipmakers this year to be sourced from domestic suppliers. The move marks another step in the country’s increasingly urgent push to localize its semiconductor supply chain, as chips become ever more critical in the age of AI.

According to the report, reliable sources say the Chinese government's target has become an unspoken mandate among chipmakers to use locally made 12-inch wafers. "Only 30% of the market will still be open to foreign players. Some Chinese chipmakers are still aiming to produce more advanced chips, and that part of the market still requires foreign market leaders' support," a chip industry executive reportedly told Nikkei Asia. "But for the local market in mature and legacy chips, basically local Chinese silicon wafers can already meet the demand and requirements.”

Earlier this month, we reported that Huawei was on track to challenge NVIDIA in the Chinese market, buoyed by rising demand and growing pressure from Beijing for tech firms to prioritize domestic suppliers. These developments are part of a broader, coordinated push to reduce reliance on foreign players across the semiconductor stack.

Today, many of the most critical segments remain dominated by overseas companies. Samsung Electronics and SK Hynix lead the global memory market, while Intel and NVIDIA remain dominant in high-performance computing chips. Even at the materials level, the supply chain is still largely controlled abroad, with the two largest silicon wafer manufacturers — Shin-Etsu Chemical and SUMCO — both based in Japan.

Together, these companies command a significant share of the global semiconductor supply chain, underscoring the scale of China’s challenge as it seeks to build a fully localized ecosystem.

China is already largely self-reliant in producing 8-inch silicon wafers, which are typically used for older-generation chips and certain power electronics. However, competing at the cutting edge requires access to more advanced 12-inch (300 mm) wafers, which are essential for manufacturing high-performance logic and memory chips. China still depends heavily on foreign suppliers for these larger wafers. We reported late last month that the US government is preparing to further block the export of advanced AI chips to China, further intensifying the country’s push to localize its semiconductor supply chain.

According to the report, China’s push into advanced wafer manufacturing is being led by Xi'an Eswin Material Technology, which is targeting 1.2 million 12-inch wafers per month by 2026 — enough to meet about 40 percent of domestic demand and push its global share past 10 percent. The report highlights a wider expansion across players such as National Silicon Industry Group, Zhonghuan Advanced, and Hangzhou Lion Microelectronics, with Eswin described as the most aggressive, adding roughly 700,000 wafers per month through new facilities in Xi’an and Wuhan.

The report said Eswin already supplies several major domestic chipmakers, including Semiconductor Manufacturing International Corporation (SMIC), and is increasingly becoming the default supplier for new fabs. It also claims links to global customers such as Micron Technology and United Microelectronics Corporation, while Samsung Electronics and SK Hynix are validating its wafers.

The report also added that Chinese foundries, alongside Huawei-linked firms, are ramping production of advanced chips — roughly in the 7 nm to 5 nm class — to meet AI demand. However, some production still depends on foreign wafers. It cites estimates from Bernstein Research suggesting that China met about 50 percent of its 12-inch wafer demand by 2025, with domestic players’ global capacity share rising from 3 percent in 2020 to 28 percent in 2025, and potentially to 32 percent by 2026.

ASML shipped 48 EUV lithography systems and 131 immersion DUV tools in 2025, generating €32.7 billion in total revenue and ending the year with a €38.8 billion order backlog.

The Dutch company holds a 100% monopoly on EUV lithography and approximately 83% of the global lithography market overall, and its roadmap now spans four distinct generations of technology: DUV immersion systems that still handle the majority of layers on every advanced chip, low-NA EUV scanners that enabled the 5nm and 3nm era, High-NA EUV tools now entering early production at Intel and Samsung, and a Hyper-NA concept that remains in feasibility studies for the 2030s.

Each step up this ladder delivers finer resolution at exponentially higher cost and complexity, and just how aggressively the industry's largest chipmakers adopt each generation will determine the pace of transistor scaling for the next decade and beyond.

DUV immersion and low-NA EUV

ASML's DUV immersion systems are still the backbone of semiconductor manufacturing when it comes to volume production. The company sold 131 immersion DUV tools in 2025. Even a chip built on TSMC's 3nm node uses EUV on only a handful of critical layers; the majority of patterning steps still run on DUV immersion tools like the TWINSCAN NXT:2100i, which delivers 295 wafers per hour at 1.35 NA with 1.3nm overlay.

DUV single-exposure is also the standard in mature nodes powering automotive and industrial chips. While DUV multi-patterning can push down to 7nm and even 5nm, it comes at an enormous cost of up to 34 patterning steps at 7nm versus nine with EUV.

Chinese customers purchased an estimated 70% of ASML's DUV immersion systems in 2024, stockpiling ahead of tightening Dutch export restrictions that now cover the NXT:1970i and newer models. SMIC demonstrated 7nm production using DUV multi-patterning for Huawei's Kirin 9000S, according to TechInsights. But the process requires significantly longer cycle times than EUV-based production, and questions exist around whether yields are sufficient for volume commercialization.

On the EUV side, ASML's low-NA systems operate at 0.33 numerical aperture with 13.5nm wavelength light, achieving 13nm single-exposure resolution. The TWINSCAN NXE:3600D, introduced around 2021, delivers 160 wafers per hour with 1.1nm matched-machine overlay. Its successor, the NXE:3800E, began shipping in March 2024 and pushes throughput to 195 wafers per hour, upgradable to 230 — following ASML's recently updated roadmap — while tightening overlay below 1.1nm. Each NXE:3800E costs roughly $180 million. It shares its bottom module, including wafer handler and faster stage mechanics, with the High-NA EXE platform, a decision that reduces ASML's manufacturing complexity and provides fabs with a degree of serviceability continuity when they upgrade.

ASML's roadmap extends low-NA further, with the NXE:3800F expected around 2027. It targets a ≤0.9nm overlay and over 260 wafers per hour. A subsequent NXE:4200G targets a ≤0.8nm overlay and over 300 wafers per hour, with an NXE:4200H beyond that at a ≤0.7nm and 330 wafers per hour. Further out, ASML has disclosed a High Productivity platform, the NXE:4600, targeting 400 wafers per hour or more.

TSMC has confirmed that it will not use high-NA EUV for its A16 (1.6nm) or A14 (1.4nm) nodes, instead relying on low-NA with multi-patterning. Kevin Zhang, TSMC's Deputy Co-COO and Senior Vice President of Business Development, said at the company's European Technology Symposium last May that TSMC would adopt high-NA "whenever we see high-NA will provide meaningful, measurable benefit," adding that the technology team continues to extend the life of current EUV.

Computational lithography is one reason low-NA can stretch further, with ASML's Brion subsidiary developing inverse lithography technology and curvilinear mask optimization software that computationally corrects for optical distortion beyond specification, effectively squeezing better resolution from existing 0.33 NA optics without hardware changes.

TSMC has been a major user of these techniques, and their continued advancement narrows the gap between low-NA double patterning and High-NA single exposure. ASML's installed base management business, which services and upgrades the global fleet of lithography tools, reached €8.2 billion in revenue in 2025, up 26% year-over-year. That recurring revenue stream grows with every tool shipped and is increasingly important as fabs push older systems to higher utilization rates.

High-NA EUV

The jump to 0.55 numerical aperture with high-NA is the largest optical leap in EUV's history, shrinking minimum resolution from 13nm, which itself was down from 30nm with DUV, to 8nm and enabling approximately 2.9 times higher transistor density in a single exposure. ASML's first High-NA tool, the EXE:5000, shipped to Intel in December 2023 as a development platform.

Each unit of the production-capable EXE:5200B weighs in at 150,000 kilograms, requires 250 shipping crates, and takes six months and 250 engineers to assemble on-site, says Intel. Priced at approximately $380 million, the EXE:5200B delivers 175 wafers per hour at 50 mJ/cm² dose with 0.7nm overlay. ASML told Reuters in early 2024 that it had taken 10 to 20 orders by that point and planned to deliver 20 annually by 2028.

Intel announced that it had completed acceptance testing of its EXE:5200B in December 2025 at its Hillsboro D1X fab and that the tool will be used for the development of Intel's 14A fabrication process. 14A is expected to be the first production node to rely on High-NA for its most critical layers, with risk production targeted for 2027.

In September, SK hynix became the first memory manufacturer to install a commercial High-NA system at its M16 fab in Icheon, South Korea. Samsung, meanwhile, received its first EXE:5200B in October, with a second unit due in the first half of 2026 for its 1.4nm foundry node. Imec, the Belgian research institute, secured an EXE:5200 last month with a Q4 2026 qualification target for sub-2nm process development.

ASML's near-term High-NA roadmap includes the EXE:5200C, targeting 190 wafers per hour without stitching and 160 with stitching at sub-0.8nm overlay, followed by the EXE:5200D at 195/175 wafers per hour and eventually the EXE:5400E at 210/180 wafers per hour with sub-0.7nm overlay. A High Productivity variant, the EXE:5600, targets 250 wafers per hour or more.

Analysts from SemiAnalysis believe TSMC won’t adopt High-NA EUV until its 1nm-class A10 node, which would place volume deployment around 2029 to 2030, because existing low-NA EUV systems can match High-NA's 8nm resolution using double patterning, and SemiAnalysis estimates that approach may still cost less than High-NA single patterning. High-NA tools also require substantial changes to existing fab buildings to accommodate their size.

Hyper-NA and pellicles

ASML placed Hyper-NA on its official roadmap for the first time at imec's ITF World in May 2024, with former CTO Martin van den Brink commenting a few months prior that an NA above 0.7 "is certainly an opportunity that will become more visible from around 2030." The primary target is 0.75 NA, with 0.85 NA also under investigation. Zeiss has begun preliminary lens designs. Estimated tool cost: roughly $720 million per system, according to TrendForce.

At 0.75 NA, however, polarization effects begin destroying imaging contrast because one polarization orientation effectively cancels light at extreme incidence angles, thereby necessitating the use of polarizers that block photons and reduce efficiency. Depth of focus shrinks further, and resists must be made even thinner than the sub-30nm films used for high-NA, worsening etch selectivity and stochastic defects from photon shot noise. On top of all that, an electron blur of approximately 2nm may impose a solid resolution barrier regardless of optical improvements.

Pellicle development is another bottleneck. These ultra-thin membranes protect masks from particle contamination during exposure but must transmit EUV light efficiently at rising source power levels. ASML's current composite silicon-based pellicle achieves over 90% transmission at 380 W source power, but for future systems running at 600 W to 1,000 W, carbon nanotube pellicles are the next-gen technology, achieving up to 97% transmission while withstanding temperatures above 1,500 C. Mitsui Chemicals is building dedicated CNT pellicle production capacity targeting 5,000 sheets per year and commercialization aimed for this year.

Export controls and Canon NIL

EUV systems have never been sold to China, blocked since 2019 under U.S. pressure despite existing orders from Chinese customers. In addition, Dutch export controls, effective since late 2023, required licenses for advanced DUV immersion systems (NXT:2000i and newer), and by September 2024, the restrictions expanded to include the NXT:1970i and NXT:1980i.

Servicing restrictions also prohibit ASML from improving overlay accuracy or increasing throughput by more than 1% on installed Chinese systems. China represented 49% of ASML's revenue at the peak of stockpiling in Q2 2024, falling to roughly 36% for full-year 2024. ASML's management guided China to approximately 20% of revenue in 2025 and 2026, which has seen South Korea and Taiwan emerge as the primary growth markets, with SK hynix alone placing a record $7.9 billion EUV order last month covering roughly 30 systems over two years.

Canon's FPA-1200NZ2C nanoimprint lithography system, announced in October 2023, represents the only credible alternative patterning approach. At roughly $15 to $20 million per system with 90% lower power consumption than EUV, it uses direct mechanical pattern transfer rather than optical exposure. Canon delivered the first commercial unit to the Texas Institute for Electronics in September 2024, and its current specs show some significant limitations: 80 to 100 wafers per hour (versus 195+ for low-NA EUV), 14nm minimum linewidth, and 2.4 to 3.2nm overlay (versus sub-1.1nm for EUV).

Japan's Dai Nippon Printing (DNP) is targeting 2027 mass production of 1.4nm-class nanoimprint templates, but no major foundry has committed to NIL for high-volume logic manufacturing. The technology's likely niche remains repetitive memory patterns, particularly high-layer-count 3D NAND, where its cost advantage could outweigh the throughput and overlay penalties. Defect density from direct physical contact between template and resist remains the fundamental barrier to logic adoption, where a single misplaced particle can kill an entire die.

ASML revenues continue climbing

ASML's 2025 results reflect the sheer scale of its roadmap, with €32.7 billion in revenue (up 16% year-over-year), 52.8% gross margin, and €9.6 billion net income. EUV became the leading source of system revenue at 48%, or €11.6 billion, up 39% from 2024. Net bookings surged 48% to €28 billion, with Q4 2025 alone delivering a record €13.2 billion in orders. The company recognized revenue on two High-NA systems during the year.

ASML's Q1 2026 results, published April 15, show €8.8 billion in total net sales at 53% gross margin, with €2.8 billion net income. The company shipped 16 EUV and 17 immersion DUV systems in the quarter, with South Korea accounting for 45% of system sales by region and China at 19%. ASML raised its full-year 2026 revenue guidance to €36 to €40 billion, with 51% to 53% gross margins

Each NA increase delivers diminishing resolution gains at exponentially rising cost and complexity. The most likely trajectory is not a clean generational handoff but an extended coexistence: low-NA handling the bulk of EUV layers well into the 2030s, High-NA reserved for the most critical pitches at sub-2nm nodes, and Hyper-NA arriving as a targeted tool for the most extreme features, subject to workarounds for the bottlenecks we’ve discussed above.

Intel is ramping up production of its CPUs on its 18A (1.8nm-class) process technology with promising results, but at the same time, the work on its enhanced version called 18A-P is well underway with production readiness looming in the coming quarters. The company's 18A-P introduces two new types of transistors, tighter process variability control, and improved thermals to enable higher performance and lower power consumption. This is perhaps why Apple and other fabless chip designers are rumored to be considering using 18A-P.

When compared to Intel's baseline 18A, 18A-P fabrication process promises to enable chip developers to either increase the performance of their designs by 9% (at the same power) or lower their power consumption by 18% (at the same performance and complexity), according to a paper Intel released at the VLSI 2026 conference. To achieve these improvements, Intel introduced new types of gate-all-around RibbonFET transistors, including high-performance devices with enhanced contacts as well as new low-power devices. Designers can now push higher frequencies on critical paths and reduce power consumption in less demanding regions, which greatly improves overall performance efficiency.

Meanwhile, 18A-P retains contacted poly pitch (50nm) and library heights (180nm and 160nm) of 18A as well as design compatibility with the base process, meaning that a chip originally designed for 18A can be ported to 18A-P and benefit from certain process-level improvements (which do not rely on new transistor types), though to fully realize performance and efficiency gains requires design re-optimization.

Another major improvement of 18A-P over 18A is -30% skew corner tightening, which also reduces variability and improves yield efficiency. The enhancement narrows the spread between fast and slow silicon and makes it closer to 'typical' silicon as well as center-to-edge variation across the wafer. Also, the production node adds extra threshold voltage (VT) options (over 5+ pairs of logic VTs compared to 4 pairs in 18A) to enable finer-grained binning and more consistent chip behavior, which increases the proportion of dies that meet target specifications. This improves parametric yield and enables chip designers to get more higher-end silicon from a single wafer. Meanwhile, tightening of process corners does not affect defect density as existing challenges with line-edge roughness (LER) and stochastic variability remain intact.

While Intel's 18A-P retains the contacted pitch of the base node, the company still tweaked the resistance and capacitance of its metal stack, which impacts signal speed, power consumption, and timing. Yet, Intel does not characterize the changes.

Last but not least, 18A-P introduces enhancements in thermals, reliability, and voltage behavior that are critical for an advanced process technology aimed at both client and data center applications. Intel says it improved thermal conductivity by 50%. Lower thermal resistance helps manage higher power densities associated with GAA transistors, which is important for client applications. Improved logic negative-bias temperature instability (NBTI) enhances long-term device stability under high-voltage stress, which is critical for data center processors. Finally, 18A-P better aligns logic and SRAM minimum operating voltage (Vmin) to improve low-voltage operation and stability.

Intel's 18A-P is a heavily optimized version of 18A-P that not only promises higher performance efficiency but also addresses things like parametric yields, thermals, and reliability. Altogether, these enhancements make 18A-P a more mature and attractive version of 18A, not only for Intel, but also for potential external customers like Apple.

TSMC's chip-on-wafer-on-substrate (CoWoS) packaging technology has become the de facto standard packaging method for advanced AI and HPC processors that use HBM memory, thanks to TSMC's aggressive development of the technology. Unlike lateral 2.5D CoWoS, TSMC's vertically integrated System on Integrated Chips (SoIC) technology with 3D interconnects has not been adopted as widely. However, now that the company has overcome the first generation's constraints, it will aggressively develop this technology in the coming years, as the company revealed at its recent North American Technology Symposium.

Different kinds of stacking

TSMC's 3D stacking SoIC technology has always been somewhat of a backburner project for TSMC, as it gained support for new process technologies slowly, when compared to CoWoS. From a pure interconnection pitch point of view, TSMC offered a rather fine 9 µm pitch in 2023, which was good enough to enable products like AMD's Instinct MI300-series. However, the 1^st generation SoIC had one major limitation: it only supported face-to-back (F2B) stacking, but not face-to-face (F2F) stacking, which is supported by the 2^nd generation SoIC technology. In 2025, TSMC achieved 6 µm pitches and expects the pitch size to decrease to 4.5 µm by 2029.

Face-to-back stacking imposes fundamental limits because signals cannot travel directly between dies. Instead, they must cross multiple metal layers and pass across through silicon vias (TSVs) in the bottom die, which increases latency, power consumption, and routing complexity.

In addition, this limits how densely connections can be implemented, since TSVs are relatively large structures that cannot be placed at fine pitch across active logic regions without affecting transistor density and design considerations. According to Broadcom, a real-world design using face-to-back stacking can achieve 1,500 signals/mm² with TSVs.

By contrast, face-to-face stacking removes the indirect signal path by aligning the metal layers of two dies directly and connecting them using hybrid copper bonding. This enables straight, ultra-short vertical interconnects without relying on TSVs, which increases signal density by an order of magnitude to 14,000 signals/mm², which therefore increases bandwidth, reduces latency, and cuts energy usage per bit.

As a result, communication between stacked dies resembles on-die wiring rather than chip-to-chip links, which is why companies like Broadcom view it as a crucial capability to scale compute density for next-generation AI and HPC processors.

3D packaging acceleration

Now that TSMC can do both F2F and F2B stacking, development of the technology will proceed much faster than before. The company now touts the usage of N3P dies on top of N4 dies, expects N2P on top of N3P within the next year, N2P on top of N2P by 2028, and envisions 3D stacked A14 dies by 2029.

Notably, the company hasn't demonstrated any process technologies with a backside power delivery in its SoIC roadmap. Yet, TSMC SVP Kevin Zhang reassured us that these nodes can support 3D integration as well.

"That may just be a simplification in the slide, A16 will have stacking capability," said Kevin Zhang, TSMC's Senior Vice President of Business Development and Global Sales, and Deputy COO.

"The SoIC roadmap shown does not cover all possible combinations — there are many permutations. The key takeaways are twofold. First, pitch scaling — from 9 µm to 6 µm, and eventually down to 4.5 µm. Second, the acceleration of stacking timelines. In the past, for example, you might stack N3P on N4, since the base die with TSV takes time to mature — 3nm TSV is only expected around 2027. But looking ahead to 2029, A14 TSV becomes available just one year after initial production. That shows how we are accelerating the schedule, enabling customers to stack the most advanced dies on top of each other much sooner."

The first face-to-face 3.5D designs

Being a leading developer of custom processors for hyperscalers, Broadcom is among the main users of TSMC's CoWoS and SoIC packaging technologies. Broadcom builds some of the world's largest system-in-packages, so it is not surprising that it is also among the first to use TSMC's F2F SoIC technology to build Fujitsu's Monaka supercomputer CPU.

On a high level, Fujitsu's Monaka processor is a heavy-duty general-purpose data center processor, and uses 144 Armv9 cores, spread over four compute chiplets made on TSMC's N2 technology, deploying a stacked face-to-face (F2F) atop dedicated SRAM chiplets (implemented on N5 technology) using hybrid copper bonding (HCB), equipped with a comparatively large I/O die that integrates the processor's memory controllers and PHYs for 12 DDR5 channels. Fujitsu's Monaka also features PCIe 6.0 connectivity with CXL 3.0 support for accelerators and memory expanders, as well as other interfaces expected from a modern data-center-class CPU.

Stacking N2-based CPU chiplets atop N5-made SRAM chiplets enabled Broadcom and Fujitsu to add massive amounts of cache to Armv9 cores to maximize their single-thread performance relatively cost-efficiently, but at the price of additional complexity and challenges surrounding thermals. Due to this, Broadcom and Fujitsu do not stack logic-on-logic, and it remains to be seen when TSMC's clients will actually start to use this option.

Broadcom is currently sampling Monaka with Fujitsu and aims to volume produce the CPU in 2027. Notably, while the company uses hybrid bonding, it also uses 9 µm pitches, which indicates that even innovators like Broadcom are cautious about using the latest versions of 3D integration technologies. This is in stark contrast to CoWoS, as TSMC's clients are eager to use the latest versions of the technology to build bleeding-edge processors.

Nonetheless, TSMC clearly positions its SoIC 3D stacking as a way to increase compute density, so it clearly has reasons to expect this technology to be used widely. After all, if transistor scaling is slowing down, packaging is inevitably becoming the scaling engine.

Google announced its eighth-generation Tensor Processing Units at Cloud Next on April 22, shipping two distinct chip designs for the first time in the TPU program's decade-long history. The two chips — TPU 8t and TPU 8i — are intended for use in different workloads. TPU 8t targets large-scale model training, while TPU 8i is built for low-latency inference and reasoning workloads.

The split also extends to the supply chain, with MediaTek having joined Broadcom as a silicon design partner for the eighth-gen program back in December, ending Broadcom’s exclusive role in TPU development since 2015. Both chips are fabricated on TSMC's N3 process family with HBM3E memory and will be available to Google Cloud customers later this year.

Optionality for customers

In terms of raw specs, TPU 8 doesn’t close the gap with Nvidia or AMD. According to Google’s own technical deep dive, the TPU 8t delivers 12.6 FP4 PFLOPs with 216 GB of HBM3e running at 6,528 GB/s, while TPU 8i offers 10.1 FP4 PFLOPs, 288 GB of HBM3e at 8,601 GB/s, and 384 MB of on-chip SRAM. In comparison, Nvidia's Vera Rubin R200 is rated at 35 FP4 PFLOPs for training with 288GB of HBM4 at 22 TB/s, and AMD's MI455X reaches 40 FP4 PFLOPs with 432GB of HBM4. That makes the gap roughly 3:1 in raw compute per-socket.

Then there’s the choice of HBM3E over HBM4, which appears to be a deliberate cost and yield trade-off. TPU 8t carries 12.5% more memory capacity than the previous-gen Ironwood TPU, but delivers 11.5% less bandwidth, running slower memory to improve yield and bring down cost per chip per analysis from Next Platform. This is an odd strategy on the face of it, but it seems that Google, rather than trying to take on Nvidia in terms of raw performance, is creating options for external customers that want alternatives.

A TPU 8t superpod packs 9,600 chips into a single cluster with two petabytes of shared HBM, connected by a proprietary inter-chip interconnect running at double the previous generation's bandwidth. Google claims 121 FP4 ExaFLOPs from a single superpod, with the new Virgo Network fabric tying up to 134,000 TPU 8t chips into a single non-blocking data center fabric with 47 PB/s of bisection bandwidth, extending past 1 million chips across multiple sites.

So, yes, while individual Nvidia GPUs are faster, Google holds an advantage with its pod-level throughput at that mass scale; training workloads consume thousands of accelerators, not one, and Nvidia’s current-gen GPUs top out at 576 accelerators in a single NVLink deployment.

Interestingly, Google also announced Vera Rubin NVL72 instances running over the same Virgo Network fabric at Cloud Next, so TPUs are clearly not intended to act as a direct replacement for Nvidia silicon.

TPU 8i architecture

The TPU 8i’s architecture is a radical departure from the norm for Google, with TPU 8i abandoning the 3D Torus interconnect that has been inside TPU pods since the second generation. Instead, it’s replaced with a topology that Google calls “Boardfly,” inspired by the 2008 Kim/Dally Dragonfly paper. Boardfly is a three-tier hierarchy: four-chip building blocks connected into 32-chip groups by copper cabling, with 36 groups linked by optical circuit switches into a pod of up to 1,024 active chips.

In a 1,024-chip 3D Torus configuration, the worst-case packet path traverses 16 hops. Boardfly cuts that to seven, a 56% reduction in network diameter that directly benefits mixture-of-experts (MoE) models, where token routing requires frequent all-to-all communication across unpredictable chip pairs.

TPU 8i also replaces the SparseCore embedding accelerators that Google has used since TPU v4 with a new fixed-function block called the Collectives Acceleration Engine (CAE). The CAE offloads reduction and synchronization operations during autoregressive decoding, cutting on-chip collective latency by up to five times. Combined with the tripled SRAM, which holds more of the KV cache on-chip during long-context inference, Google claims 80% better performance per dollar over Ironwood for large MoE models at low-latency targets.

TPU 8t, meanwhile, retains the 3D Torus at a larger scale and keeps SparseCore for the irregular memory access patterns typical of embedding lookups during training. It introduces native FP4 compute to double MXU throughput at reduced precision, and a new TPUDirect RDMA path that bypasses the host CPU to pull data directly from high-speed managed storage, delivering what Google describes as ten times faster storage access over the previous generation. Both chips now run on Google's Arm-based Axion CPU hosts, replacing x86 for the first time.

Two suppliers instead of one

The MediaTek partnership means that there’s a second silicon design house in the TPU program alongside Broadcom, with MediaTek understood to be handling the design of the TPU 8i inference chip while Broadcom handles the design of the 8t training chip.

TrendForce reported back in December that MediaTek initially booked 20,000 TSMC CoWoS wafers for the program, with allocation potentially scaling to 150,000 by 2027. According to Bank of America analyst Vivek Arya, the dual-sourcing arrangement could reduce per-chip cost by up to 30% compared to solely sourcing from Broadcom, whose role is secured through at least 2031 per an April 6 SEC filing, which also formalized a 3.5 GW TPU capacity commitment from Anthropic starting in 2027. That deal sits on top of the one gigawatt of Anthropic capacity already coming online this year under a separate Google Cloud agreement.

Meanwhile, Meta has signed a separate multi-year, multi-billion-dollar TPU rental agreement, estimated to involve 500,000 to 800,000 TPU chips by 2027 if initial testing meets expectations, and Apple is routing Gemini-powered Siri workloads to Google Cloud on TPU infrastructure, valued at roughly $1 billion per year.

At the North American Technology Symposium 2026, TSMC revealed its updated CoWoS packaging roadmap with major enhancements. Within chipmaking, the reticle limit is the largest size that a chip can be printed within a single step of the manufacturing process. TSMC's previous CoWoS-based system-in-packages (SiPs) roadmaps topped out at a 9.5-reticle size.

Now the company expects to produce 14-reticle and over 14-reticle-sized System-in-Packages (SiPs) with up to 24 HBM5E stacks by 2029. Such high integration is designed to meet the insatiable demand that AI accelerators have for both compute and memory bandwidth, and signals that packaging, not lithography, acts as a primary driver for semiconductor technologies.

"AI compute scaling is driven by the combination of advanced logic, SoIC 3D stacking, and CoWoS technologies," a statement by TSMC reads.

Bigger, hotter and hungrier

It is common for contemporary process technologies to scale slowly in transistor density, while full-node scaling enables 15% to 20% higher transistor density every three years. Intra-node improvements yield diminishing returns in density, but continue to provide performance improvements and greater power efficiency. This may not be a big problem for consumer product-makers, but it greatly affects the developers of AI and HPC applications, who must improve their solutions every year or two to remain competitive.

For those customers, TSMC has begun mass production of 5.5-reticle-sized CoWoS SiPs, supporting up to 12 HBM3E/HBM4 stacks and has achieved yields over 98%, according to the company.

In 2027, TSMC's CoWoS roadmap outlines a 9.5-reticle-sized interposer that supports 12 HBM5 stacks, which is expected to require a 120 mm by 150 mm substrate. In 2028, the company expects to produce a 14-reticle-sized interposer capable of carrying 20 3D-stacked compute chiplets and 20 HBM5 modules. By 2029, TSMC expects to produce interposers over 14 reticle sizes, with up to 24 HBM5E stacks. One standard reticle measures 26 mm by 33 mm (858 mm²), so a 14-reticle-sized interposer measures 12,020 mm², or the size of a small plate, and slightly larger than a CD.

An SiP that uses a 14-reticle-sized interposer and measures 12,020 mm² will consume an enormous amount of power, will require an exotic cooling solution (think exotic cold plates like those developed by Frore Systems, immersion cooling, or a combination of both), and will require a massive substrate, which will occupy a significant share of a server motherboard's real estate. The dimensions of the SiP alone will redefine how AI servers are built, whereas power consumption and cooling requirements are poised to open doors to a host of new technologies.

48x more compute transistors, 34x more bandwidth by 2029

Such gargantuan multi-chiplet processors show that advanced packaging is now the de facto scaling engine for the industry. In fact, TSMC's lateral CoWoS and vertical SoIC technologies enable faster growth of transistor budgets than traditional Moore's Law scaling. In addition, such SiPs also offer more memory bandwidth.

Based on TSMC's expectations, its customers will be able to put (at least) as many as 24 3D-stacked compute chiplets on one 14 reticle-sized CoWoS interposer by 2029, when A14 will be in mass production. When combined with scaling enabled by the latest process technologies (4x from N7 to A14), an ultra-high-end SiP from 2029 with 24 3D-stacked A14-based chiplets will be able to carry 48x more compute transistors than a high-end SiP with two N7-based chiplets from 2024, according to TSMC. Granted, we've rarely seen frontier dual-chiplet N7-based SiPs in 2024, even a cautious Nvidia opted to use 4NP instead.

There is a catch regarding 3D-stacked compute transistors, though. The bottom die may overheat, whereas the top die must get enough power to reach its full potential. To that end, many designs use the bottom die for cache (e.g., AMD's Zen 5-based CPUs with 3D V-Cache), not for compute.

Nonetheless, even a 24x increase in the number of compute transistors per high-end SiP in five years is a breakthrough that could not be achieved by Moore's law alone. However, such integration comes at a price. In the 2030s, cutting-edge SiPs with 24 3D-stacked compute chiplets and 24 HBM5E modules will likely cost an order of magnitude more than a high-end SiP from the mid-2020s.

In addition to compute capability, large CoWoS interposers also enable considerably higher memory bandwidth simply because they can carry more HBM stacks. It is not that simple, though. Total memory bandwidth scales dramatically, driven by the combination of wider HBM4 and HBM5 interfaces, more advanced HBM base dies built on TSMC’s N3P process, and ongoing CoWoS improvements that enable faster interconnect speeds. As a result, a high-performance SiP integrating 24 HBM5E stacks in 2029 is expected to deliver up to 34x higher bandwidth when compared to a reference SiP with eight HBM3 stacks in 2024, according to TSMC.

"HBM bandwidth scaling comes from multiple factors," said TSMC. "First, there is the memory itself — progressing from HBM3 to HBM4, with higher I/O counts. In addition, we are leveraging more advanced logic technologies for the base die, which allows us to push data rates well beyond 10 Gb/s per pin, something that was unheard of in traditional DRAM. At the same time, our CoWoS technology enables integration of more HBM stacks within a single package. […] All of these factors together — higher data rates, more I/O, and more stacks — contribute to the overall bandwidth scaling."

Slower transistor scaling

One of the things that strikes the eye about the current and upcoming process technologies due later this decade is the slow scaling of transistor density. While A14 is set to increase per-chip transistor density by 20% compared to N2 technology in 2028, its optical-shrink successor (A13) is only poised to provide a 6% higher density a year later.

Fortunately, TSMC continues to aggressively develop its CoWoS packaging technology, which promises to enable developers of system-in-packages to put 24 3D-stacked compute chiplets and 24 HBM5E modules onto one massive 14 reticle-sized interposer before the end of the decade. This will increase compute transistor count and memory bandwidth per SiP by 48x and 34x, respectively, compared to high-end data center SiPs in 2024, according to TSMC.

However, this level of integration will likely come at a high cost. System-in-packages with up to 24 3D-stacked compute chiplets and 24 HBM5E stacks in the 2030s will probably cost an order of magnitude more than high-end SiPs from the mid-2020s.

Bolt Graphics has announced its completed tape-out of a test chip for its Zeus GPU, marking the California-based startup's first move from FPGA emulation to manufactured silicon — which it claims can deliver 17 times lower cost of compute.

The test chip was designed into TSMC's 12nm FFC process and will be used for customer benchmarking ahead of a planned production ramp in Q4 2027. Bolt says it’s targeting companies in the HPC, electromagnetic simulation, and graphics rendering markets, which it values at over $55 billion combined, that "can’t afford the level of compute needed for their applications."

This is a concrete step for a company whose ambitious performance claims have, until now, rested entirely on internal simulations and FPGA testing. When Bolt first introduced Zeus in early 2025, it said the GPU could deliver up to 10 times the path tracing throughput of Nvidia's GeForce RTX 5090. Those figures obviously drew attention as well as skepticism, given the absence of working silicon. In a set of FAQs released alongside the announcement, Bolt says that its architecture has been running on FPGA and under evaluation by customers for four years.

TSMC’s 12nm FFC node is part of the company’s mature 16nm/12nm FinFET family, offering lower cost and well-established IP libraries compared to leading-edge processes. According to Bolt, however, the Zeus architecture is also designed for "advanced nodes, including 5nm," suggesting the 12nm test chip is more of a validation step and that the company will look to use more advanced nodes for final production.

According to Bolt’s product specs, Zeus will ship in PCIe card and 2U server form factors. The PCIe cards range from a single-slot, 120 W model with 5/10/20 TFLOPS at FP64/FP32/FP16, up to a dual-slot, 250 W card offering twice those figures. All cards feature 128 MB to 256 MB of on-chip cache, up to 384 GB of memory through a combination of soldered LPDDR5X and DDR5 SO-DIMMs, and integrated 400 GbE networking.

Bolt's stated product pipeline exceeds $500 million, and the company says over 14,000 enterprises, developers, and end users have joined its early access program. It closed a Series A that was reportedly 50% oversubscribed, though neither the funding amount nor lead investors have been disclosed.

Timelines have shifted somewhat since Bolt first appeared on the scene, with the company originally aiming for developer kits in late 2025 and production in late 2026. At CES in January, the company demoed a prototype card but still lacked functional silicon. This new announcement pins production to Q4 2027 to supply chains for HPC, rendering, and next-gen workloads, with no updated timeline for developer hardware.

Elon Musk on Wednesday said that TeraFab plans to use Intel's 14A fabrication technology when it has its own production capacity later this decade and when the manufacturing process matures. He also revealed that Tesla will be responsible for building and operating a pilot production line, whereas SpaceX will be responsible for high-volume manufacturing of chips.

TeraFab to use Intel 14A

"We plan to use Intel's 14A process, which is state-of-the-art and in fact not yet totally complete," Elon Musk, chief executive of Tesla, said during Tesla's earning's call with analysts and investors. "By the time TeraFab scales up, 14A will be probably fairly mature or ready for prime time. 14A seems like the right move and we have a great relationship with Intel, a lot of respect for the CEO, the CTO, and the new team there."

Based on the comments made by Musk, he wants to use Intel's 14A manufacturing technology at TeraFab, which likely means licensing the fabrication node from Intel and integrating it at a fab operated by TeraFab. Meanwhile, Musk has never mentioned licensing per se, which means that while Intel is expected to participate in TeraFab as a partner, actual details of its role have yet to be defined.

As for Tesla and SpaceX, the division of responsibilities is straightforward: Tesla handles the research fab, while SpaceX builds and operates a high-volume manufacturing facility.

Tesla handles R&D, SpaceX handles manufacturing

In the short term, Tesla intends to construct a semiconductor R&D facility at its Texas campus, with an estimated cost of around $3 billion. This site will be a small pilot line capable of processing a few thousand wafers per month, and its purpose will be to experiment with new ideas in semiconductor manufacturing as well as validate whether these ideas can be realized in a production-like environment. From what we can tell, 14A will barely have anything to do with the pilot line in Texas.

"In the near term, Tesla plans to build a research fab at its Gigafactory Texas campus," Musk said. "This is something we expect to be a $3 billion initiative and support a few thousand wafers per month. "It is really intended to try out ideas […] for improving the fundamental technology of how chips are made, some of new physics we would like to test out. We also want to test out the ability to see if something is working in production [environment]. You need kind of like a few thousand wafer starts a month to make sure that a production process is sound."

For scaling beyond the pilot phase, SpaceX is expected to build an actual high-volume manufacturing facility. However, coordination between Tesla and SpaceX introduces many challenges, as any joint effort must be approved by both companies' boards and pass conflict-of-interest reviews, which will inevitably slow down the project.

"That is basically what we have figured out thus far is Tesla's doing the research fab, SpaceX doing the initial part of the large-scale TeraFab and then we got to figure out the rest," Musk said.

Licensing a process technology is one of the ways for TeraFab to get a fabrication node quickly (as it may take a decade to design a manufacturing tech from scratch), whereas for Intel, this could mean an influx of cash. Historically, chipmakers have licensed process technologies from others if they could not design their own node on time, or the parties wanted to create a virtual foundry with compelling capacity to compete with larger contract chipmakers.

For example, GlobalFoundries licensed Samsung's 14nm-class process technologies in 2014 – 2015 after it failed to complete development of its own 14nm XM production node. While there were rumors that GlobalFoundries produced some of Samsung's Exynos processors at its fab in New York, the first clearly attributable, high-volume GF-built 14nm products — AMD's Radeon RX 400-series 'Polaris' GPUs only showed up in 2016. This incited rumors about GF's inability to integrate the node and maximize yields. Rapidus is a more recent example, as it has licensed IBM's 2nm technology for its fabs.

It remains to be seen whether it is possible to license Intel's 1.4nm-class process technology and then port process recipes, tune tools, and maximize yields at a TeraFab facility. After all, modern process technologies are dramatically more complex than those from a decade ago.

TSMC revealed its general manufacturing technology roadmap through 2029 at its North American Technology Symposium 2026 on Wednesday. Among the key highlights the company presented were its 1.2nm and 1.3nm-class fabrication processes called A12 and A13, an unexpected extension of the N2 family named N2U, and the lack of plans to use High-NA EUV lithography for any nodes through 2029. Perhaps the most notable part of the technology-related announcement was firming the multi-faceted approach to new node development.

"Last year we announced A14 as our most advanced, 2^nd Generation nanosheet technology, scheduled for production in 2028," said Kevin Zhang, senior vice president of business development and global sales and deputy COO at TSMC.

"This year, we are introducing derivatives of A14, including A13 and A12, both planned for production in 2029. A13 is an incremental enhancement of A14 achieved primarily through optical shrink, delivering about 6% area reduction while maintaining full design-rule and electrical compatibility, enabling customers to benefit with minimal redesign."

Changing the rules of the game

Historically the lion's share of TSMC's revenue originated from the smartphone industry, but more recently AI and HPC have outpaced handsets. This was clearly reflected in the company's plans, so TSMC's latest roadmap highlighted a deliberately bifurcated strategy that segments leading-edge nodes by end-market requirements rather than pursuing a one-size-fits-all approach. As a result, the company is adopting a new strategy for process technology introductions in which it will continue to offer a new node for client applications every year and will roll-out a new node for heavy-duty AI and HPC applications every two years.

On one hand, processes like N2, N2P, N2U, A14, and A13 are aimed at smartphones and client devices — where costs, power efficiency, and IP reuse are crucial and strong design compatibility is welcome, while incremental improvements can be tolerated as long as TSMC can deliver a new node every year.

On the other hand, nodes such as A16 and A12, aimed at AI and HPC application, must offer strong performance improvements to justify transition to newer technologies, and costs are less important. These nodes integrate Super Power Rail backside power delivery (SPR) to address power integrity and current delivery constraints of AI data center and HPC workloads and offer tangible performance, power, and transistor density improvements — albeit, at a biennial cadence.

*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.

A13 and N2U: New nodes for client applications

Last year TSMC introduced its A14 process technology, which is set to rely on the company's 2^nd Generation gate-all-around (GAA) nanosheet transistors, offer additional design flexibility with NanoFlex Pro technology, and serve as the foundry's premium node for high-end smartphone and client applications sometimes in 2028. This year the company announced A13, which will build upon A14.

TSMC's A13 is an optical shrink of A14 designed to extract additional efficiency with minimal disruption. A13 reduces linear dimensions by about 3% (to ~97% scale), which translates into roughly 6% higher transistor density amid maintaining full design-rule and electrical compatibility with A14. From many points of view, A14 continues TSMC's long-standing tradition of offering optical shrinks of its process technologies (N12, N6, N4, N3P) — though, previously, these could deliver more tangible benefits in general. The approach enables TSMC's customers to reuse IP with little to no redesign effort, but with only incremental improvements.

While A14 is set to deliver full-node improvements in power, performance, and density, to extract them, chip and IP designers must use all-new tools, IPs, and design methodologies. By contrast, A13 delivers incremental gains enabled by design-technology co-optimization (DTCO), but which does not require to change anything to extract these gains. A13 is expected to enter production in 2029.

In addition to offering customers its all-new A14 node in 2028, TSMC plans to offer them a cheap way to improve their N2-based designs with N2U. N2U will be the third-year extension of the N2 platform that leverages DTCO to provide about 3% – 4% higher performance at the same power or 8% – 10% lower power at the same speed while allowing a modest 2% – 3% logic density improvement. The node will maintain compatibility with N2P IP, which will enable its customers (particularly from the client space) to build new products without transition to an all-new process and incur rather massive costs. For example, if a company plans to build a mid-range product using IP of a high-end product implemented using N2P in 2027, it can do it with N2U in 2028.

"We continue to extend our 2nm platform with N2U, which provides additional improvements in performance, power, and density through design-technology co-optimization," Zhang said. "Our strategy is to continue enhancing each node after introduction, allowing customers to maximize the return on their design investments while still gaining incremental PPA benefits."

A16, A12, and N2X: Maximum performance at any cost

While TSMC's N2 is set to be adopted both for client and data center applications, the company preps A16 with its Super Power Rail backside power delivery that is specifically tailored for high performance data center applications. Essentially, A16 is N2P with SPR that will rely on the 1^st Generation nanosheet GAA transistors and provide significant power, performance, and transistor density advantages over N2 and N2P nodes, albeit at higher cost.

It is noteworthy that TSMC now lists A16 as a 2027 process technology, which is technically a slip from 2026.

"A16 will be ready for production in 2026," Zhang said. "However, actual product ramp depends on customers, and we expect volume production to begin in 2027. That is why we aligned it to that timeline."

Interestingly, the arrival of A16 does not replace N2X, a performance-enhanced variant of N2P that uses traditional front side power delivery to push clocks of N2-based designs to the max.

A16 will pass the baton to A12 — set to arrive in 2029 — which is projected to bring full-node advantages to TSMC's data center-class nodes. While TSMC does not disclose actual numbers, expect A12 to offer the same kinds of benefits over A16 as A14 brings over N2 as it is set to rely on the company's 2^nd Gen nanosheet GAA transistors and NanoFlex Pro technology.

“I can say that A16 is our first-generation technology with Super Power Rail, or backside power delivery, and A12 is the next generation,” Zhang said. “A13 and A12 are built on A14 with significant geometric scaling. To continue shrinking the frontside geometry, you also need to scale the backside to achieve overall density benefits. So there are many enhancements being implemented as we move from A16 to A12, particularly related to backside power delivery. That is all I can share.”

No High-NA on horizon

One interesting thing to note about TSMC's upcoming A13 and A12 process technologies due in 2029 is that none of them will require High-NA EUV lithography tools, which is stark contrast to Intel's approach to its 14A production node and successors that are set to use High-NA EUV scanners starting in 2027 – 2028.

"I tell you, I am amazed by our R&D team," said Kevin Zhang. "They continue to find a way to drive the technology scaling without using High-NA. One day they may have to use it, but at this point, we continue to be able to harvest the benefit from current EUV, not have to go to High-NA, which, you know, very, very expensive."

A bipartisan group of U.S. lawmakers introduced the Multilateral Alignment of Technology Controls on Hardware Act, or MATCH Act, in early April, targeting the sale and servicing of advanced chipmaking equipment to China.

The bill, filed as H.R. 8170 in the House and with a companion in the Senate, would impose country-wide prohibitions on exports of DUV lithography systems to China, designate five Chinese semiconductor firms as restricted entities by statute, and give U.S. allies 150 days to adopt equivalent controls before Washington expands the Foreign Direct Product Rule unilaterally.

Still in the committee stage, the bill, which has drawn broad congressional support, has since been amended to remove a blanket ban on cryogenic etch tools, though core proposals remain intact.

Two mechanisms of restriction

The MATCH Act builds its controls on two independent mechanisms. The first is a country-wide prohibition on exports of specific "chokepoint" manufacturing equipment to any destination in China, regardless of end user. Named in the original Bill were DUV immersion lithography systems and cryogenic etch tools, but a recent amendment dropped the latter entirely, leaving DUV lithography tools as the sole country-wide prohibition.

That covers ASML’s NXT:2000i-class scanners and Nikon’s NSR-S631E, which are widely used by Chinese chipmaker SMIC in its 7nm production lines. China has no domestic equivalent for volume manufacturing; SMEE’s SSA/800-10W scanner remains unconfirmed in production use.

The second mechanism names five Chinese companies directly in statute: SMIC, CXMT, YMTC, Hua Hong, and Huawei. All of their fabs, facilities, subsidiaries, and affiliates would be classified as “Covered Facilities” and subject to a presumption-of-denial licensing regime extending beyond equipment sales to servicing, spare parts, and technical support for already-installed tools.

While the Bureau of Industry and Security’s Entity List currently restricts SMIC (since 2020), Huawei (since 2019), and YMTC (since 2022), it requires Commerce Department officials to evaluate each subsidiary or affiliate on a case-by-case basis and grants the executive branch discretion to approve licenses. Codifying restrictions against these and other Chinese entities into law would eliminate that discretion, meaning that a subsidiary spun off next year or a joint venture created under a different name would be automatically covered.

U.S. Representative Michael Baumgartner (R-WA), who introduced the Bill, says that the legislation closes loopholes that Chinese firms have been exploiting through front companies and third-country routing.

The Chairman of the House Select Committee on Strategic Competition between the United States and the Chinese Communist Party, Representative John Moolenaar (R-MI), co-sponsored the bill alongside Democrats including Representatives Jared Golden (D-ME), John Mannion (D-NY), Josh Riley (D-NY), Maggie Goodlander (D-NH), and Suhas Subramanyam (D-VA).

Meanwhile, the Senate companion was introduced by Foreign Relations Chairman Jim Risch (R-ID), Senator Pete Ricketts (R-NE), and Senator Andy Kim (D-NJ), with Democratic Leader Chuck Schumer joining as a co-sponsor.

150 days for multilateral coordination

MATCH's enforcement mechanism is built around a deadline for multilateral coordination. Within 60 days of enactment, the Departments of Commerce, State, Defense, and Treasury, along with the Office of the Director of National Intelligence, must identify all covered equipment and facilities. Commerce then has 150 days to negotiate equivalent country-wide controls with allied supplier nations, principally the Netherlands and Japan, home to ASML and Tokyo Electron.

If those negotiations fail, the bill directs Commerce to expand the Foreign Direct Product Rule to cover any foreign-manufactured tool that incorporates U.S.-origin software, technology, or components. In practice, this would function as a near-zero de minimis threshold (meaning that goods would be liable for customs duties and formal entry procedures), since virtually every advanced chipmaking tool in the world relies on some U.S.-origin intellectual property in its EDA software, metrology subsystems, or process control algorithms.

The Netherlands and Japan have so far declined to comment publicly on the bill, but both countries tightened their own export controls in 2023 and 2024 following U.S. pressure. Neither, however, has adopted restrictions as broad as what MATCH proposes.

The FDPR expansion could prove to be a sticking point, which, if enacted, would give the U.S. the ability to block sales of equipment manufactured entirely outside the United States, by non-U.S. companies, to non-U.S. customers, based on embedded U.S. technology. That extraterritorial reach has historically been a point of tension with allied governments, and the explicit statutory deadline could force a confrontation that the executive branch has so far managed to defer through diplomatic channels.

Interestingly, the bill’s sponsors circulated a revised draft on April 16th that removes two provisions that had drawn significant opposition. The country-wide ban on cryogenic etch equipment, dominated by Lam Research and Tokyo Electron, was dropped entirely, while the automatic presumption of denial on licenses to service equipment installed inside Covered Facilities was also softened — however, this revision hasn’t yet appeared on Congress.gov.

That cryogenic etch concession is narrower than it appears, however, given that existing BIS rules already restrict cryogenic etch tools when destined for advanced-node fabs, defined as sub-16/14nm logic, sub-18nm DRAM, and 128-layer-and-above NAND. The DUV immersion lithography restrictions survived in full, as did everything related to Covered Facilities, the 150-day alignment deadline, and the FDPR expansion authority. The five named Chinese firms also remain in the bill without modification.

Executive discretion vs. statutory mandate

The biggest change with the MATCH Act is the transfer of authority from the executive branch to Congress, not that Congress’s authority appears to matter to the incumbent administration.

Since October 2022, U.S. semiconductor export controls have been administered entirely through BIS rulemakings under the Export Control Reform Act of 2018. Those rules can be tightened or loosened by any administration without congressional approval, and each new rule requires a fresh assessment of each entity, each subsidiary, each end use.

MATCH would lock the five named firms and the DUV lithography machine ban into statute, meaning any future relaxation would require an act of Congress to implement. For Applied Materials, Lam Research, and KLA, which booked a combined $19 billion in China revenue in 2025 despite direct U.S.-to-China shipments falling 34%, the bill introduces a layer of permanence that executive-branch rulemaking doesn’t.

ASML, which drew around 30% of its total 2025 revenue from China, faces a different challenge because the servicing restrictions in the original bill threatened the company's maintenance contracts for scanners already operating in Chinese fabs. While the April 16th revision eased that pressure, the FDPR expansion authority could eventually reach tools manufactured at ASML's Veldhoven headquarters if the Netherlands doesn’t adopt matching controls within the 150-day window.

At present, the Bill’s path through Congress remains uncertain; HR 8170 sits in House Foreign Affairs, and the Senate version has been referred to Banking and Foreign Relations. No committee has yet scheduled a markup, and equipment makers that derive 30% or more of their revenue from China are bound to lobby hard against it. But the bipartisan coalition behind the Bill is difficult to dismiss, and current trade tensions between the U.S. and China have narrowed the political runway for opposing new restrictions.