RISC-V, the open source ISA, has made some great progress over the years, and the new HiFive Premier P550 from SiFive is claimed to be “The Highest Performance RISC-V CPU Development Board in the World” and for $400 it better be. The unit that I have on the bench is the $399 16GB RAM model, but if you want / need more RAM, for $499 you can grab a 32GB model. Also, don’t forget to add your sales tax.

Before we get too deep into the review, we have to qualify that this isn’t a board for those of you who want a PC form factor SBC. It's not a desktop computer, nor is it a Raspberry Pi alternative. This is a development board for those that want to develop software and hardware around the RISC-V platform.

If you were looking for a Raspberry Pi killer, I’ll save you some time, this isn’t it. But, what I can say is that this is showing that RISC-V has improved, and could offer a viable platform for those who demand a truly open platform.

RISC-V is an important and interesting concept. An open standard instruction set architecture (ISA) based on RISC (Reduced Instruction Set Computer), RISC-V is open source meaning that anyone can make their own RISC-V board. Linux support was added around 2022 (Kernel 5.17).

SiFive are a well known name in this space and have produced a number of RISC-V boards that follow PC motherboard form factors. RISC-V is important to the open source community as it offers a truly open ISA when compared to the closed source ISA produced by the big names (Intel, AMD, Arm etc). The chips may not be as powerful as their contemporaries, but they are steadily improving over time.

So, how does the HiFive Premier P550 work, and what can we do with it? Let's find out!

HiFive Premier P550 Technical Specifications

HiFive Premier P550 Design

Right away you know that this isn’t a Raspberry Pi type SBC. The HiFive Premier P550 is more closely aligned to a Mini-ITX desktop PC but with a large SO-DIMM slot for the SoM. Essentially the motherboard is just a large breakout board for the SoM. We’ve got a collection of the typical ports along one edge of the motherboard. Including a USB Type C and Ethernet port which are there for debug and monitoring the onboard MCU.

The PCIe Gen 3.0 x16 slot supports up to x4 mode and you could connect a GPU but driver support isn’t stellar, so an older AMD card will get you better results than the best GPUs for gaming. You’ll find a better use with a PCIe based storage card, just remember that you are limited to PCIe Gen 3 speeds! Wait, why do we need a PCIe card for storage? Well there is no onboard M.2 NVMe storage option, the only M.2 connector is for a Wi-Fi / Bluetooth card. There are no other M.2 slots, not on the motherboard or the SoM. Yeah we have a SATA 3 connector, and that should be fast enough for most.

There is a 40-pin GPIO, but we hit a catch. How do we use it? There is nothing in the user guide or forums to show how it can be used from Linux. I reached out to SiFive for guidance and its response was "GPIO access is not currently supported in Ubuntu 24.04 for the HiFive Premier P550. This is an item for future updates."

The only means of networking are two Gigabit Ethernet ports. If you want Wi-Fi then you will need to add your own card via the M.2 slot. I was unable to test this as I have no compatible cards. Did you spot the additional Ethernet port? This RJ45 port is for remote board management using the dedicated MCU

A USB Type-C (USB 2.0) port provides a USB to serial connection between the P550 and another machine. Using PuTTY on my Windows 10 machine, I was able to make a serial connection to the P550 and run a terminal. Handy if there are boot issues, or you just need to make a quick connection.

How do we power the board? Via the DC barrel jack? Nope. We need a 24 pin ATX power supply, yes the same one that is probably inside your PC. I used a Cooler Master MWE Gold 550 that I picked up cheap. It's not just a matter of connecting the power and away you go. There are two switches and a power button in the process to power up. First there is the ATX PSU’s power switch, then the P550’s power switch. Lastly there is a power button which spins the fans and powers up the board. Yeah, the last bit eluded me for a few moments.

On the 128GB eMMC, we have Ubuntu 24.04.1 LTS pre-loaded and ready to run. Ubuntu is a great choice of OS. It is easy to use, there are plenty of applications and it is relatively lightweight. Though Lubuntu / Xubuntu would’ve been lighter, and you can install it yourself if you wish. As Ubuntu 24.04 is a Long Term Support (LTS), it is a great choice. The stability of an LTS means that developers aren’t running bleeding edge, and often fragile applications.

HiFive Premier P550 Performance

Let’s set the record straight; this is no Raspberry Pi 5 killer. In fact, the Raspberry Pi 4 gave the HiFive Premier P550 a thorough beating. Running a Geekbench 6 benchmark, the HiFive Premier P550 achieved a single-core score of 136 and multi-core score of 423. For a Raspberry Pi 4, the same benchmark returned 295 single-core and 719 multi-core. For further reference, the Raspberry Pi 5 returned 784 single-core and 1566 multi-core.

Yeah, the HiFive Premier P550 may be the most powerful RISC-V machine, but it's not going to beat a Raspberry Pi just yet. But that isn’t its goal; rather it is an open source ISA offering an alternative to closed source ISA that we typically use.

YouTube Playback

In the technical specifications, we can see that there is an Imagination AXM-8-256 GPU, but this GPU is not yet supported in software. This means that video encoding and decoding is not supported by the OS and for now that leaves the CPU doing all of the heavy lifting. At 1080p and using the default Firefox browser, Big Buck Bunny dropped 96.4% of the frames. Essentially I saw a few frames over a one minute period. The P550 really needs software support for video decoding.

I re-tested with a 720p video and it was better, but not a great performance. Dropping 82.9% of the frames is an improvement, but it still doesn’t make for a great viewing experience.

We really need video decoding support to be enabled, and hopefully someone will do that in the near future.

CPU Temperature Benchmark

Normally we see a big difference between the idle and stress temperatures, but with the P550 we don’t. Why? Because the fan is always on and it's not that quiet!

The fan is always on, and always at 100% so the idle temperature of 31.39 degrees Celsius is low! Using the Stress Bash tool I set all four cores to 100% for five minutes and monitored the temperature. The highest CPU temperature recorded was 35.9C, not much higher than idle. The CPU always runs at 1.4 GHz, there doesn’t seem to be a scaling governor in place

Despite a decent eMMC, boot times are quite sedentary. Largely down to a GRUB bootloader and then a lengthy boot process that streams a log of data to the screen.

The Raspberry Pi 5, booting from micro SD, managed to boot in a third of the time.

Opening Applications

Synthetic benchmarks don’t really tell us how the P550 “feels” in use. So, let's test opening applications.

These times aren’t bad, and feel about right for a RISC-V PC. They certainly feel faster than the Sipeed Lichee that I reviewed last year. But then, the P550 is proclaiming itself as “The Highest Performance RISC-V CPU Development Board in the World”.

Compared to a Raspberry Pi 5 4GB running from micro SD, the Pi 5 wins with GIMP and Libreoffice, but Firefox was 2.3 seconds slower than the eMMC used on the P550. So what does this indicate? Well it proves that the P550 isn’t a generic SBC for desktop use; rather it is for RISC-V developers who want the best. Sure it can be used as such, but why pay over the odds when a Raspberry Pi 5 will do the job?

Storage Performance

The onboard 128GB eMMC is decent and provides enough storage and speed for RISC-V developers. But, how fast is the onboard storage? Using Ubuntu’s Disk Benchmark tool I recorded the following.

The eMMC speeds are good and certainly fast enough. The PCIe Gen 3 speeds were achieved using a WD Black SN850X (a PCIe Gen 4 drive) in the PCIe x16 (x4 in reality) slot via an adapter. Those speeds are on par with the Raspberry Pi 5’s PCIe Gen 3 performance with the plethora of M.2 HATs. I couldn’t find a way to boot from NVMe, but it should be possible with some tweaking. The same applies to SATA 3 which would offer a noticeable boost over eMMC.

Who is the HiFive Premier P550 for?

This is an easy answer, RISC-V developers. In the RISC-V ecosystem, this board is the top dog and it will enable developers to get their RISC-V projects built at pace. This is a board for those who want to push the open source ISA and develop their own products.

Who is it not for? Those of us looking for a Raspberry Pi alternative. The OrangePi 4A is a cheaper alternative to consider, but the Radxa X4, powered by an Intel N100 is a serious alternative to the Pi 5.

Bottom Line

I love what this board represents: the onward march of progress in the RISC-V sphere. I’m not the intended customer. I don’t build RISC-V projects; I’m a maker. But if I were a RISC-V developer, then the SiFive HiFive Premier P550 would be the board that I would use. But, the $400 price tag for our review unit seems to further place this as a tool for developers and not the general public.

It is well made, and offers decent performance and port selection. Booting via NVMe would’ve been nice, but the onboard eMMC is fast enough. The PCIe slot is useful, as long as your intended add-on has a driver. I can’t fault the hardware build quality, it is solid. This is a considered purchase for developers.

RISC-V firm Milk-V demonstrated that it can get AMD’s RX 7900 XTX graphics card to work on one of its RISC-V boards.

The PC shown in the video uses Milk-V’s Megrez board, which is equipped with Chinese RISC-V chip maker Eswin’s EIC7700X, a system-on-chip (SoC) that hosts four P550 CPU cores designed by SiFive. The P550 core has been around since 2021, so it’s nothing cutting-edge at the tail end of 2024. The SoC sport H.265 encoding and decoding at 8K, and has a 20 TOPS NPU, which are both reasonably robust for PCs.

The particular 7900 XTX that Milk-V used was made by XFX and ran on Debian Linux. There wasn’t much choice in terms of the OS, as Linux boasts the best support for RISC-V at the moment. The brief demo showed the system running the glmark2 benchmark, which renders 3D objects at the highest framerate possible.

However, Milk-V got a 7900 XTX up and running on this RISC-V board, which marks another milestone for RISC-V’s ambitions in PCs. So far, the open-standard architecture has been primarily used for data centers, AI, and tiny, low-function chips that form just one small part of a whole product. Although the usage of RISC-V has been growing steadily for the last few years, the architecture hasn’t penetrated the PC market, the domain of x86, and now Arm.

A few RISC-V laptops have made it to market, such as DeepComputing’s DC-ROMA and the Lichee Console 4A, but you could count them all on one or maybe two hands. No fully assembled RISC-V-powered desktop exists, but some motherboards come with RISC-V chips, such as those made by Milk-V.

Although no RISC-V CPU is in a position to realistically take advantage of support for AMD’s flagship gaming CPU, the support’s existence certainly won’t hurt. It will undoubtedly be difficult for RISC-V to make inroads into the PC ecosystem if Arm’s example is anything to judge by. Arm chip designer Qualcomm struggled for years to make its Snapdragon laptops an appealing choice until this year with the Snapdragon X Elite. Estimates show Arm CPUs will power as much as 40% of notebooks sold in 2029.

It is important to note that Arm has the full support of Microsoft, which is crucial for Arm’s success in PCs since Windows is the most important OS for consumer desktops and laptops. Getting supported on Windows will probably be essential for RISC-V’s adoption in the PC market. Otherwise, RISC-V companies will have to bet on Windows getting serious competition from Linux or some other OS, which doesn’t seem likely to happen any time soon.

SiFive has introduced the SiFive Performance P870-D, a new RISC-V processor core designed for data center applications. The new P870-D not only sets the stage for RISC-V processors with up to 256 cores, but also enables building CPUs for mission-critical systems demanding the utmost reliability.

SiFive's Performance P870-D builds upon the regular P870, which is a six-wide out-of-order core with an RVA23 profile of the RISC-V instruction set architecture with vector and vector crypto processing acceleration. The P870-D adds an open AMBA CHI bridge for energy-efficient cross-cluster communications (each cluster has from one to four cores with shared L2 cache) as well as cross-cluster reliability, availability, and serviceability (RAS) features to enable building CPUs with up to 256 cores aimed at mission-critical applications. 

Additionally, the P870-D supports the RISC-V Sv57 extension, providing a 57-bit virtual address space that enhances its memory management capabilities. The processor also includes a distributed and scalable IOMMU, accelerating virtualized device IO, and meets modern safety and security standards.

"The new P870-D enhances our proven Performance architecture to bring new levels of performance, flexibility, and scalability," said John Ronco, SiFive SVP of Product. "The full solution offering from SiFive — including software, IOMMU, interrupt controller, and other uncore blocks — combined with our intelligence processors for dedicated AI compute makes it easy for our customers to achieve the most effective performance/watt/dollar metrics on AI and datacenter workloads."

To build processors with up to 256 cores, chip designers will have to license Ncore cache coherent network-on-chip from Arteris. Essentially, the SiFive P870-D allows CPU designs that are on par with those from AMD and Intel. In fact, given energy efficiency of RISC-V designs compared to x86, we can expect CPUs based on the P870-D to have an edge over rivals when it comes to performance-per-watt metrics.

"Network-on-Chip IP significantly helps streamline the process of building complex, multi-core heterogeneous SoCs with the lowest latency and high bandwidth to accommodate AI workloads," explained Michal Siwinski, CMO of Arteris. "We are pleased to continue the collaboration with SiFive, enabling the ecosystem to create high-performance and low-power RISC-V-based systems on time and budget while reducing risk." 

Currently, SiFive is offering samples of the P870-D to select customers (though it is unclear with how many cores), with full production of samples scheduled for the end of 2024. SiFive expects the first processors based on the P870-D to emerge already next year.

SiFive has unveiled the HiFive Premier P550, a new development board using the RISC-V architecture. It will be the first commercially available out-of-order RISC-V development board. Also intriguing (and surprising) is that the new hardware includes a Chinese-made Eswin SoC, even though SiFive is an Intel partner. The new development board is designed for many different market segments and applications, including machine vision, video analysis, and AI.

The P550 comes with 16GB of LPDDR5-6400 memory and a 128GB eMMC SSD for "fast bootable" storage. Connectivity comes in the form of a single PCIe 3.0 x4 interface connected to an x16 slot on the motherboard along with five USB 3.2 Gen 1 ports.

The Eswin EIC7700 SoC features four P550 cores, 256KB of L2 cache, and 4MB of L3 cache. The main selling point of the new chip is its out-of-order capabilities, which allow the processor to reorder instructions to increase throughput and performance. The superscalar P550 can issue three instructions per cycle per core.

Out-of-order CPU designs have been around for a long time, with Intel first adding the feature in the Pentium Pro back in 1995. Out-of-order architectures tend to use more power but offer greater performance. Out-of-order chips are also more vulnerable to side-channel attacks. Smartphones stuck with in-order designs until after 2010, but today, nearly all modern smartphones also feature out-of-order chip architectures.

The P550 SoC also comes with an integrated GPU (no details were provided other than that it offers 2D/3D acceleration), hardware video encoder and decoder, NPU, DSP, MIPI DSI, and a security subsystem. The P550 is designed as a cheaper alternative to the P550 Pro, which debuted last year. The latter sports significantly better connectivity and includes an Intel-made RISC-V "Horse Creek" SoC. Again, it's interesting that the P550 and P550 Pro use completely different core designs.

SiFive partnered up with Canonical to make the P550 compatible with Ubuntu — one of the most popular flavors of Linux. According to Gordan Markus, Silicon Alliances Director at Canonical: “Thanks to our collaboration with SiFive, developers using the HiFive Premier P550 board will be able to innovate at speed with Ubuntu. Additionally, Canonical’s software and services will accelerate time to market, and ensure long-term support and security maintenance for our enterprise partners.”

The P550 has a lot of potential, but availability might be its Achilles heel. According to The Register, the HiFive Pro P550, which launched a year ago, is still almost impossible to find. Hopefully, this same fate doesn't befall the P550.

Since the P550 uses an entirely different CPU from its Pro counterpart, that could help improve availability. SiFive partnered with Intel to create the Horse Creek SoC found in the P550 Pro, but Intel hasn't had a great track record with RISC-V and appears to have no problems killing its own RISC-V projects if necessary.

Due to the P550 Pro's lack of availability, it seems like the Horse Creek CPU was a complete failure — even though Intel says this wasn't the case. Regardless, there must be a very good reason why SiFive (again, a partner with Intel), decided to swing the pendulum the other direction and chose a Chinese-made RISC-V CPU for the P550.

SiFive expects to earn $240 million to $280 million in licensing revenue and new lifetime contracts in 2024, according to documents seen by Bloomberg. The revelation may indicate that the company is on track to sign another major contract with Google to supply processor core designs for its tensor processing units (TPUs), believes The Register.

Bloomberg indicates that IP provider SiFive pins a lot of hope on a 'second-generation chip for artificial intelligence servers' without elaborating, but this could be a major revenue driver for the company. Although SiFive can license its RISC-V cores to virtually everyone, The Register speculates that the IP developer is set to license its X390 core to Google, which is poised to use it for its next-generation TPU.

Google's current-generation TPU already uses SiFive's X280 general-purpose core to feed data to Google's matrix multiplication units or, as SiFive puts it, accelerate the accelerator. SiFive's X390 general-purpose core is tailored for AI and machine learning workloads. Neither SiFive nor Google have confirmed the rumor. Meanwhile, a significant reason to expect the cloud and search giant to keep using SiFive cores in its next-generation AI system-on-chips is to maintain backward compatibility with existing AI SoCs.

Given that the RISC-V instruction set architecture is gaining traction in datacenters, it is possible that SiFive may license its cores to other developers of AI and/or edge AI accelerators, so it is not cast in stone that Google is poised to license SiFive's technology.

In 2023, SiFive reported revenue of $38.2 million, primarily from licensing and royalty deals. Despite signing $186 million in lifetime deals, the company lost a lot of money last year due to its relatively high operating expenses of $148.9 million.

For 2024, SiFive has set ambitious revenue targets. It expects to earn $16 million in the first quarter, $43 million in the second, $103 million in the third, and $79 million in the fourth. This projected revenue includes lifetime royalties and licensing fees. The company's total future revenue from royalty contracts secured by the end of 2023 amounts to $233 million.

A little over two years ago an enthusiast managed to make AMD's Radeon RX 6700 XT work on a RISC-V development board under Linux, which was not a particularly easy task. Since then, AMD's Linux graphics drivers have made a big leap in working with RISC-V systems and now it is possible to use AMD's latest graphics cards, including the Radeon RX 7900 XTX, with RISC-V platforms out of the box. 

Legacy AMD Radeon graphics cards, such as those based on the company's original GCN architecture from early 2010s, can run on practically all platforms under Linux, according to Phoronix. By contrast, AMD's latest GPUs, such as those powered by the Navi architecture (which are among the best graphics cards), use a different display code to initialize and kernel-mode FPU support that were not supported on RISC-V — which is why they could not work on RISC-V boards out of the box, and required manual patching.

This issue is now being fixed thanks to new updates from SiFive, and it looks promising for the upcoming Linux 6.8 kernel release.

"This series allows using newer AMD GPUs (e.g., Navi) on RISC-V boards such as SiFive's HiFive Unmatched," a statement by SiFive reads. "Those GPUs need CONFIG_DRM_AMD_DC_FP to initialize, which requires kernel-mode FPU support."

These changes are under review and are expected to be included in the next Linux 6.8 kernel release, and will make it easier to use the latest AMD Radeon graphics cards with RISC-V and open-source drivers.

For now, there are hardly any mainstream 3D-accelerated games that directly support the RISC-V architecture. However, advancements like the improved compatibility of AMD GPUs with RISC-V systems could lead to more gaming software being ported or developed for RISC-V in the future.

SophGo, a China-based chip developer, is working on several high performance processors featuring RISC-V-based IP that it licensed from SiFive, a major RISC-V IP designer from the U.S., reports HPCwire. This endeavor somewhat underscores the rising influence of RISC-V in the global chip industry and shows why some U.S. lawmakers are concerned about this open-source technology.

SophGo's first RISC-V-based project is the SG2380 processor, which includes 16 four-issue, out-of-order SiFive P670 cores, SiFive's X280 accelerator for AI/ML workloads, and Imagination Technologies' AXT-16-512 graphics processing unit. The CPU is mostly aimed at high-performance desktops, but it could also be used for edge servers that require 16 general-purpose cores as well as AI capabilities.

But the SG2380 is not the only SiFive-based product in SophGo's portfolio, as the company has already announced its SG2044 system-on-chip, slated for release in 2024. This 120W SoC will pack up to 64 high-performance RISC-V cores from SiFive, the final version of RISC-V vector extensions, PCIe 5.0, GbE, and LPDDR5x support. This processor will succeed little-known SGF2042, which supports 0.7 version of RISC-V vector extensions and is currently used mostly by researchers.

Both SophGo's SG2380 and SG2044 are to be produced on TSMC's 12nm-class process technologies. These products clearly exemplify the collaborative and innovative spirit of RISC-V, akin to the Linux operating system in its global contribution and development model. However, some U.S. lawmakers are consideration limiting RISC-V cooperation between American and Chinese companies. That sparked quite the controversy, with RISC-V International, headquartered in Switzerland, strongly opposing such governmental interference.

Despite the advancements and potential of RISC-V, its widespread adoption in the server and supercomputer sectors remains a distant goal. The current market is heavily dominated by x86 chips produced by Intel and AMD, with Arm also posing significant competition. Meanwhile, Arm and x86 technologies are controlled by companies based in the U.S. and U.K., which means that they are subject to export control regulations. As a result, Chinese developers are turning their attention to RISC-V, as they can either get open-source designs and expand on them, or just design high-performance technology from the ground up without any controls from the U.S. or U.K. governments.

The RISC-V open standard instruction set architecture (ISA) has come a long way since it was introduced in August 2014, and according to RISC-V International, the architecture has already been used inside over a billion chips. But this is only the beginning, as the organization forecasts the technology to land into 16 billion chips by 2030. 

At the ongoing RISC-V Summit, Calista Redmond, the chief executive of RISC-V International, demonstrated a slide that forecasts RISC-V adoption to grow at a compound annual growth rate (CAGR) of 40% in the coming years. As a result, by 2030, the instruction set architecture will be used inside 16 billion system-on-chips, which is a massive increase from around 1 billion so far. The actual prediction comes from the SHD Group, which is set to make its RISC-V report available in December.

"We are already in billions of cores around the world, and some analysts have even pointed out that it is getting hard to find any new design starts that do not include RISC-V," said Redmond. "RISC-V is the most profound technical revolution of our time." 

RISC-V is widely used for microcontrollers today. For example, Qualcomm uses RISC-V for microcontrollers that accompany its mobile system-on-chips. However,  the technology is expanding rapidly, so we are seeing companies like Meta, Intel, Tenstorrent, and Ventana develop RISC-V-based solutions for artificial intelligence and high-performance computing. Over time, the technology will expand even further, for example, to GPUs, like with Imagination and Venata's nascent GPU program. 

To make RISC-V-based processors competitive against those powered by Arm and x86 architectures, RISC-V needs a more robust software and hardware ecosystem. Apparently, both are developing at a rapid pace. Currently, RISC-V is supported by over 4,000 software development companies from across the world, and there are plenty of motherboards aimed at software and hardware designers available from the industry.

Update: October 26, 03:36 PT: SiFive has contacted More Than Moore and the site has issued a correction. Reports regarding the roadmap change, from pre-designed to custom cores are untrue. The roadmap is being enhanced, claims SiFive, with the recent addition of new cores being part of that enhancement.

Update: October 24, 5:22 p.m. ET: SiFive sent Tom's Hardware a statement via email. This story has been updated to reflect the newest information.

SiFive, one of the key companies in the RISC-V ecosystem, is undergoing a significant restructuring marked by extensive layoffs and apparently a shift in business focus, reports More Than Moore. 

RISC-V has become quite a popular choice for making miniature low-cost cores, but there are several companies who are working on higher-performance RISC-V-based offerings. SiFive is one of such companies offering ready-to-use designs and also making custom cores based on what customers need. But now, SiFive has laid off somewhere between 100 to over 300 employees from around 700 in mid-October. Most of these were engineers, along with some sales and product personnel. Meanwhile, the company's leaders, including CEO Patrick Little, are still there. 

“In a statement sent to Tom’s Hardware late on Tuesday, SiFive confirmed that it was laying off about 20% of its employees (~ 140) from a variety of different groups.“As we identify and focus on our greatest opportunities, SiFive is shifting to best meet our customers' fast-changing requirements by undergoing a strategic refocusing of all our global teams,” a statement by SiFive reads. “Unfortunately, with this realignment, approximately 20% of employees across all different business groups and levels were impacted. The employees are receiving severance and outplacement assistance.”

The company also plans to offer standard and custom products for a variety of applications, including automotive, consumer, datacenters, artificial intelligence, high-performance computing, and wearables.

“We remain focused on our four product groups, essential, intelligence, performance and automotive, and as we explained in a press event earlier this month, have a robust roadmap to meet the needs of these markets,” the statement clarifies. We see tremendous new opportunities in AI and with consumer products like wearables and mobile as Google brings Android to the RISC-V ecosystem. We will continue to offer customization for specific customers, offering standard and custom products where it makes sense from a business standpoint.”

The company remains optimistic about its future as it is well funded and expects demand for its products to remain high. “SiFive continues to be excited about the long-term opportunities for the company and for RISC-V,” the company stated. “The growth of the company has never been stronger and the opportunities never better. We are well funded for years in the future and continue to work with the market leaders in every segment.”

The ramifications of SiFive’s restructuring raise pertinent questions regarding its future trajectory and influence within the RISC-V sector. The organizational changes, marked by significant layoffs and a potential shift in business strategy, cast uncertainty over the company’s forthcoming contributions to RISC-V standards and its broader impact on the industry’s evolutionary path.”

Qualcomm and Google announced that they had agreed to expand their partnership to development of a Snapdragon Wear platform based on the RISC-V instruction set architecture (ISA) designed for next-generation Wear OS products. The announcement is a milestone as it envisions custom RISC-V-based solutions from Qualcomm that will address the whole Google Wear OS ecosystem.

The announcement by the two high-tech giants means that Qualcomm will work on RISC-V-based hardware for wearable devices, whereas Google will work on software for these applications. In general, this means that the two companies are collaboratively developing a RISC-V platform for wearable devices — for smartwatches initially, but perhaps for something more advanced going forward.

"Qualcomm Technologies have been a pillar of the Wear OS ecosystem, providing high performance, low power systems for many of our OEM partners," said Bjorn Kilburn, General manager of Wear OS at Google. "We are excited to extend our work with Qualcomm Technologies and bring a RISC-V wearable solution to market."

While system-in-packages for wearable devices may be considered simplistic, that is not at always the case. In addition to the main processor that enables computing capabilities for the whole device, they feature multiple supporting capabilities like storage and sensors. All of these are typically based on cores featuring ISA developed by Arm, including Cortex A-series cores for compute as well as Cortex M-series cores for microcontrollers. All of these cores cost money and replacing them with RISC-V ones will reduce or even eliminate licensing fees to Arm.

The announcement lacks many details. For example, we do not know whether Qualcomm's Snapdragon Wear platform featuring RISC-V ISA will replace all Arm cores or only select ones. Yet, Google's involvement in the project clearly emphasizes its scope and importance.

"We are excited to leverage RISC-V and expand our Snapdragon Wear platform as a leading silicon provider for Wear OS," said Dino Bekis, vice president and general manager, Wearables and Mixed Signal Solutions, Qualcomm. "Our Snapdragon Wear platform innovations will help the Wear OS ecosystem rapidly evolve and streamline new device launches."

Having assembled a team of top-notch AI and CPU engineers, start-up Tenstorrent, helmed by industry icon Jim Keller, has huge plans that involve both general-purpose processors and artificial intelligence accelerators.

At present, the company is working on the industry's first 8-wide decoding RISC-V core capable of addressing both client and HPC workloads that will be first used for a 128-core high-performance CPU aimed at data centers. The company also has a roadmap of several more generations of processors, which we'll cover below. 

Why RISC-V?

We recently spoke with Wei-Han Lien, the chief CPU architect at Tenstorrent, about the company's vision and roadmap. Lien has an impressive background, with stints at NexGen, AMD, PA-Semi, Apple, and is perhaps best known for for his work on Apple's A6, A7 (world's first 64-bit Arm SoC), and M1 CPU microarchitectures and implementation. 

With many world-class engineers with vast experience in x86 and Arm designs, one may ask why Tenstorrent decided to develop RISC-V CPUs considering that the data center software stack for this instruction set architecture (ISA) is not as comprehensive as that for x86 and Arm. The answer Tenstorrent gave us is simple: x86 is controlled by AMD and Intel, and Arm is governed by Arm Holding, which limits the pace of innovation. 

"Only two companies in the world can do x86 CPUs," said Wei-Han Lien. "Due to the x86 license restriction, innovation is basically controlled by one or two companies. When companies get really big, they become bureaucratic hierarchically, and the pace of innovation [slows]. […] Arm is kind of the same thing. They claim they are like a RISC-V company, but if you look at their specification, [it] becomes so complicated. It is also actually kind of dominated by one architect. […] Arm kind of dictating all the possible scenario even to architecture [license] partners." 

By contrast, RISC-V is developing quickly. Since it is an open-source ISA, it is easier and faster to innovate with it, particularly when it comes to emerging and rapidly developing AI solutions, according to Tenstorrent. 

"I was looking for a companion processor solution for [Tenstorrent's] AI solution, and then we wanted BF16 data type, and then we went to Arm and said, 'Hey, can you support us?' They said 'no,' it requires like maybe two years internal discussion and discussion with partners and whatever," explained Lien. "But we talked to SiFive; they just put it in there. So, there is no restriction, they built it for us, and it is freedom." 

On the one hand, Arm Holding's approach ensures high quality of the standard as well as a comprehensive software stack, but it also means that the pace of ISA innovation gets slower, which might be a problem for emerging applications like AI processors that are meant to be developed quickly. 

One Microarchitecture, Five CPU IPs in One Year

Since Tenstorrent is looking forward and addressing AI applications at large, it needs not only different system-on-chips or system-in-packages but also various CPU microarchitecture implementations and system-level architectures to hit diverse power and performance goals. This is exactly the department of Wei-Han Lien. 

A humble consumer electronics SoC and a mighty server processor have little in common but can share the same ISA and microarchitecture (albeit implemented differently). This is where Lien's team comes in. Tenstorrent says that the CPU crew has developed an out-of-order RISC-V microarchitecture and implemented it in five different ways to address a variety of applications. 

Tenstorrent now has five different RISC-V CPU core IPs — with two-wide, three-wide, four-wide, six-wide, and eight-wide decoding — to use in its own processors or license to interested parties. For those potential customers who need a very basic CPU, the company can offer small cores with two-wide execution, but for those who need higher performance for edge, client PCs, and high-performance computing, it has six-wide Alastor and eight-wide Ascalon cores.  

Each out-of-order Ascalon (RV64ACDHFMV) core with eight-wide decode has six ALUs, two FPUs, and two 256-bit vector units, making it quite beefy. Considering that modern x86 designs use four-wide (Zen 4) or six-wide (Golden Cove) decoders, we are looking at a very capable core. 

Wei-Han Lien was one of the designers responsible for Apple's 'wide' CPU microarchitecture, which can execute up to eight instructions per clock. For example, Apple's A14 and M1 SoCs feature eight-wide high-performance Firestorm CPU cores, and two years after these were introduced, they are still among the most power-efficient designs in the industry. Lien is probably one of the industry's best specialists in 'wide' CPU microarchitecture, and, as far as we understand, the only processor designer who leads a team of engineers developing an eight-wide RISC-V high-performance CPU core. 

In addition to a variety of RISC-V general-purpose cores, Tenstorrent has its proprietary Tensix cores tailored for neural network inference and training. Each Tensix core comprises of five RISC cores, an array math unit for tensor operations, a SIMD unit for vector operations, 1MB or 2MB of SRAM, and fixed function hardware for accelerating network packet operations and compression/decompression. Tensix cores support a variety of data formats, including BF4, BF8, INT8, FP16, BF16, and even FP64.

Impressive Roadmap

Right now, Tenstorrent has two products: a machine learning processor called Grayskull that offers performance of around 315 INT8 TOPS that plugs into a PCIe Gen4 slot, as well as a networked Wormhole ML processor with approximately 350 INT8 TOPS of performance and uses a GDDR6 memory subsystem, a PCIe Gen4 x16 interface and has a 400GbE connection to other machines. 

Both devices require a host CPU and are available as add-in-boards as well as inside pre-built Tenstorrent servers. One 4U Nebula server containing 32 Wormhole ML cards offers around 12 INT8 POPS of performance at 6kW.

Later this year, the company plans to tape out its first standalone CPU+ML solution — Black Hole — that combines 24 SiFive X280 RISC-V cores and a multitude of 3rd Generation Tensix cores interconnected using two 2D torus networks running in opposite directions for machine learning workloads. The device will offer 1 INT8 POPS of compute throughput (approximately three times performance uplift compared to its predecessor), eight channels of GDDR6 memory, 1200 Gb/s Ethernet connectivity, and PCIe Gen5 lanes.  

In addition, the company is looking forward to adding a 2TB/s die-to-die interface for dual-chip solutions as well as for future use. This chip will be implemented on a 6nm-class fabrication process (we would expect it to be TSMC N6, but Tenstorrent has not confirmed this), yet at 600mm^2, it will be smaller than its predecessors produced on TSMC's 12nm-class node. One thing to remember is that Tenstorrent has not taped out its Blackhole yet, and its final feature set may differ from what the company discloses today. 

Next year the company will release its ultimate product: a multi-chiplet solution called Grendel that features its own Ascalon general-purpose cores featuring its own RISC-V microarchitecture with eight-wider decoding as well as a Tensix-based chiplet for ML workloads.  

Grendel is Tenstorrent's ultimate product set to be released next year: the multi-chiplet solution comprises an Aegis chiplet featuring high-performance Ascalon general-purpose cores and a chiplet or chiplets with Tensix cores for ML workloads. Depending on business requirements (and the financial capabilities of the company), Tenstorrent may implement an AI chiplet using a 3nm-class process technology and therefore take advantage of higher transistor density and Tensix core count, or it can keep using Black Hole chiplet for AI workloads (and even assign some work to 24 SiFive X280 cores, the company says). The chiplets will communicate with each other using the aforementioned 2TB/s interconnect.   

The Aegis chiplet with 128 general-purpose RISC-V eight-wide Ascalon cores organized in four 32-core clusters with inter-cluster coherency will be made using a 3nm-class process technology. In fact, the Aegis CPU chiplet will be among the first to use a 3nm-class fabrication process, something that will probably put the company on the map when it comes to high-performance CPU designs. 

Meanwhile, Grendel will use an LPDDR5 memory subsystem, PCIe, and Ethernet connectivity, so it will offer tangibly higher inference and training performance than existing solutions from the company. Speaking of Tensix cores, it is necessary to note that while all of Tenstorrent's AI cores are called Tensix, these cores actually evolve.

"The [Tensix] changes are evolutionary, but they are definitely there," explained Ljubisa Bajic, the company's founder. "[They add] new data formats, change ratios of FLOPS/SRAM capacity, SRAM bandwidth, network-on-chip bandwidth, new sparsity features, and features in general."

It is interesting to note that different Tenstorrent slides mention different memory subsystems for Black Hole and Grendel products. This is because the company is always looking at the most efficient memory technology and because it licenses DRAM controllers and physical interfaces (PHY). Therefore it has some flexibility when choosing the exact type of memory. In fact, Lien says that Tenstorrent is also developing its own memory controllers for future products, but for 2023 ~ 2024 solutions, it intends to use third-party MCs and PHYs. Meanwhile, for now, Tenstorrent does not plan to use any exotic memory, such as HBM, due to cost concerns. 

Business Model: Selling Solutions and Licensing IP

While Tenstorrent has five different CPU IPs (albeit based on the same microarchitecture), it only has AI/ML products in the pipeline (if fully configured servers are not taken into account) that use either SiFive's X280 or Tenstorrent's eight-wide Ascalon CPU cores. Thus, it is reasonable to ask why it needs so many CPU core implementations.  

The short answer to this question is that Tenstorrent has a unique business model that includes IP licensing (in RTL, hard macro, or even GDS forms), selling chiplets, selling add-in ML accelerator cards or ML solutions featuring CPU and ML chiplets, and selling fully configured servers containing these cards.  

Companies building their own SoCs can license RISC-V cores developed by Tenstorrent, and a broad portfolio of CPU IPs allows the company to compete for solutions requiring different levels of performance and power.  

Server vendors can build their machines withTenstorrent's Grayskull and Wormhole accelerator cards or Blackhole and Grendel ML processors. Meanwhile, those entities that do not want to build hardware can just buy pre-built Tenstorrent servers and deploy them. 

Such a business model looks somewhat controversial since, in many cases, Tenstorrent competes and will compete against its own customers. Yet, at the end of the day, Nvidia offers both add-in cards and pre-built servers based on these boards, and it doesn't look like companies like Dell or HPE are too worried about this because they offer solutions for specific customers, not just building blocks.

Summary

Tenstorrent jumped onto the radar about two years ago with the hire of Jim Keller. In two years, the company recruited a host of top engineers who are developing high-performance RISC-V cores for data center-grade AI/ML solutions as well as systems. Among the development team's achievements is the world's first eight-wide RISC-V general-purpose CPU core, as well as an appropriate system hardware architecture that can be used for AI as well as HPC applications. 

The company has a comprehensive roadmap that includes both high-performance RISC-V-based CPU chiplets as well as advanced AI accelerator chiplets, which promise to enable capable solutions for machine learning. Keeping in mind that AI and HPC are major megatrends poised for explosive growth, offering AI accelerators and high-performance CPU cores seems like a very flexible business model. 

Both AI and HPC markets are highly competitive, so getting some of the world's best engineers onboard is a must when you want to compete against the likes of established rivals (AMD, Intel, Nvidia) and emerging players (Cerebras, Graphcore). Like large chip developers, Tenstorrent has its own general-purpose CPU and AI/ML accelerator hardware, which is a unique advantage. Meanwhile, since the company uses RISC-V ISA, there are markets and workloads that it cannot address for now, at least as far as CPUs are concerned. 

We are now learning new details on the fruits of the partnership between SiFive and Intel. The two companies have announced that the HiFive Pro P550 development board is on track for release during the summer of 2023.

HiFive Pro P550 is powered by a "Horse Creek" SoC, which is a quad-core, 64-bit RISC-V design. The SoC features private L2 memory, with 128KB allocated to each core, while a total of 2MB L3 cache is shared among all four cores. The SoC operates in excess of 2GHz, according to Intel. Another important thing to remember is that the Pro 550 is built by Intel Foundry Services on the Intel 4 process (aka 7nm in traditional process node parlance).

"When we first looked at this opportunity with RISC-V, our first thought was: Let's put ourselves in the shoes of the developer. What do they need to develop software?" said Nikhil Krishna Gopalakrishna, Principal Engineer at Intel. "The core is fantastic, now let's bring together the most important peripherals around it to enable good ecosystem development."

As for the board itself, it features a microATX form factor (244mm x 244mm) and 16GB of onboard DDR5-5600 memory. Also included are two PCIe 5.0 expansion slots, integrated graphics, 10 GbE, and eight USB ports (two USB 2.0 and six USB 3.0). There are also two M.2 expansion slots (2230 and 2280).

"This is going to push RISC-V software development to new levels, new heights," added Sam Grove, Direct of Product Management at SiFive. "This is really for people building software, packaging software and distributing software to the rest of the ecosystem."

Regarding usage cases, Intel envisions the HiFive Pro P550 development board targeting premium software development, developer desktops, and RISC-V rack systems. However, given that the HiFive Pro P550 is aimed at the developer community, there is no word on pricing for everyday users looking to get their hands on it.

We should note that Intel attempted to acquire SiFive in 2021, but the two companies couldn't agree on financial terms (a reported $2 billion) or how the latter would be integrated into the former. Nevertheless, Intel has been looking for ways to branch out beyond the traditional x86 architecture used in its CPUs, and RISC-V has a lot of potential in low-power applications.

Looking forward, SiFive's next-generation RISC-V products include the P670 and its low-power companion chip, the P470, aimed at "next-generation wearables and smart consumer devices." The P670 will be built on a 5nm process node and will feature clock speeds of 3.4GHz+.

SiFive announced a pair of new high-performance RISC-V processors aimed at what it calls "next-generation wearables and smart consumer devices." Known as the P670 and P470, the processors offer new features and improved performance compared to previous CPUs based on the popular open-source architecture.

There's support for virtualization, including a separate IOMMU for accelerating virtualized device I/O, and a full out-of-order vector implementation based on the RISC-V Vector v1.0 spec that was ratified last year. The chips claim to be the first on the market to support the new RISC-V vector cryptography extensions. They also exhibit enhanced scalability, with clusters of up to 16 cores able to work together, though the company has talked up 128 cores in the past.

SiFive’s 600-series is performance-focused — the P670’s predecessor the P650 was expected to match the Arm Cortex A-77 for performance — while the 400-series is more of an efficiency chip. The P550 was the chip of choice for Intel’s Horse Creek development board, which paired RISC-V with DDR5 RAM and PCIe 5.0. Intel attempted to buy SiFive for $2 billion this time last year, but the deal fell apart after the companies failed to agree terms.

The P670 is built on a 5nm process and can achieve a maximum clockspeed of more than 3.4GHz. SiFive’s description makes it sound like a P650 with two added vector units, and the new chip aims to beat Arm designs in the performance-per-mm metric that measures the space a chip takes up against its processing capability.

The P470 is designed as a companion chip for the P670, and we expect it to appear in big.LITTLE configurations in exactly the same way Arm chips do in smartphones and tablets. It’s also designed on a 5nm node and hits the same clockspeed as its bigger brother. A P450 also exists, which is a P470 without its single vector unit, and it has been area-optimized to fit in particularly small places.

“The P670 and P470 are specifically designed for and capable of handling the most demanding workloads for wearables and other advanced consumer applications. These new products offer powerful performance and compute density for companies looking to upgrade from legacy ISAs,” said Chris Jones, SiFive VP of product. “We have optimized these new RISC-V Vector enabled products to deliver the performance and efficiency improvements the industry has long been asking for.”

There's no news of when the P670 and P470 will be available, nor which companies will be using them.

With global stocks of Raspberry Pi not being so plentiful, Raspberry Pi alternatives are becoming more and more attractive to makers. StarFive’s VisionFive 2 RISC-V SBC that crowdfunded over the summer is finally available to preorder in several configurations depending on what your networking needs are, with plenty of Linux support.

The board is an upgrade from the VisionFive 1 . VisionFive2 is built around SiFive’s U74 quad-core 64bit RV64GC running at 1.5Ghz. It’s almost the same chip as in the VisionFive 1, but that was a dual-core version. There's a choice of RAM - 2, 4 or 8GB of LPDDR4 - and an Imagination Technologies GPU that supports OpenGL, OpenCL and Vulkan. The VisionFive 1 was fixed at 8GB of RAM, and didn’t have a GPU.

Thanks to that video processor, VisionFive 2’s visual outputs are more useful than its predecessor, which was stuck at 1080p. The VisionFive 2 can output 4K over its HDMI port, and can decode video at the same resolution in either H264 or H265. There's a MIPI display output too, which can do 2K at 30FPS. Storage comes via an eMMC socket, or a micro SD card.

There's no built-in wireless networking on the VisionFive 2, but you can slot in a Wi-Fi / Bluetooth M.2 networking module. Ethernet fans can specify a board with either one or two ports, one gigabit, the other 10/100 - though a dual-gigabit version has also been promised. There's a pair of USB 3.0 ports for further expansion, plus some 2.0 sockets for a mouse and keyboard, and you can connect cameras via MIPI CSI. The board measures 100 x 72mm (3.9in x 2.8in) and comes with a 5V USB-C power adapter. A 40-pin GPIO header can be seen sprouting from the PCB too.

Linux support for RISC-V boards continues to expand. The original VisionFive launched with just Fedora support, but the VisionFive 2 has that and Debian at launch, with Ubuntu and openSUSE to come, according to the Kickstarter. 

The VisionFive 2 is available for pre-order now, starting at $65, from stores including AmeriDroid and Allnet China. Delivery is expected in December this year for some variants, and February 2023 for others.

Hardware based on the open-source RISC-V architecture keeps coming, with the latest Chinese vendor going by the name LeapFive, as spotted in the pages of CNX Software. Its NB2 processor comes with four cores and runs at a speedy 1.8GHz. It also comes with a GPU, making a Linux desktop a distinct possibility.

For now this is just a chip rather than a fully fledged SBC or anything to bother the Raspberry Pi hegemony, but we can guess at the features of such a hypothetical board by looking at the features the chip supports.

You could get 4GB of RAM, some built-in eMMC flash, and a Micro SD card slot. It would have two Ethernet sockets, both gigabit, a smattering of USB ports thanks to its 2.0 and 3.2 hosts, and 3.5mm audio thanks to the presence of a DAC. A UART connector provides RS232 and RS485 for serial applications, and there's I2C, PWM, GPIO, plus a Bluetooth and Wi-Fi module too. Video output appears to be through MIPI DSI 2.0 and LVDS, without common connections such as HDMI, which could be a barrier to producing a consumer-grade board.

Along with the GPU, which runs at 850MHz but otherwise hasn’t been revealed in detail, the chip has NPU (4 TOPS) and DSP co-processors, along with a VPU for encoding and decoding 4Kp60 H.264/H.265. The CPU cores deliver 2.5 DMIPS/MHz, which as CNX Software notes is the same as SiFive’s U74-MC 64-bit RISC cores that put out similar performance to Arm’s Cortex A55 designs. The presence of the SiFive Shield security platform is another hint that there might be something similar to SiFive’s chip there.

In a press release to accompany the launch, Dr Aglaia Kong, CEO and CTO of LeapFive Technology (pictured above), made much of how RISC-V plays into China’s aims for carbon peaking followed by carbon neutrality, known as dual carbon. “We think a lot about chip innovation: first, because we are serving dual carbon, we must consider low-power chips; second, because it is a platform around dual-carbon, our data must be safe, traceable, and non-tamperable during the process; most importantly, because of de-globalization, we also need to ensure the supply chain, and the chips must be based on a controllable and autonomous platform, so we think RISC-V, an open instruction set architecture, is a great choice.”

The chip will likely run a Linux distro such as Ubuntu Kylin, though mainstream Ubuntu has been making inroads into the RISC-V architecture itself. It will be used in smart appliances, intelligent logistics and warehousing, plus edge computing applications. No date appears to have been set for its release.

A little while ago we reported on noted SBC manufacturer Pine64 teasing a new board. This new board is based on the popular RISC-V architecture rather than the company’s usual Arm chips. The new board’s name hadn’t yet been announced, but Pine64 published a riddle that, when solved, would reveal the name. It was all very exciting, and despite not actually solving the riddle, we predicted that the board’s name would end in 64.

Well we were right! The name of the board is Star64 (the riddle required knowledge of astronomy and the London Underground to get there) and thanks to Pine64’s July update post, we also now know the specs.

The Star 64 is comparable to the Quartz64 model A, apart from the presence of a StarFive JH7110 64bit RISC-V CPU. This chip features four SiFive FU740 1.5GHz cores and comes complete with a BXE-2-32 GPU from Imagination Technologies, and boards will be available with 4GB and 8GB of RAM. Standard features include  an open-ended PCIe port, USB 3.0 and GPIO, as well as two gigabit Ethernet ports. A cheaper version with only one Ethernet socket is expected to follow. 

The Star64 is in its final layout stage, with some testing still needed, but Pine64 reports that the “initial review has yielded some very positive results, partly because the SoC runs cool without the need for passive or active heat dissipation, even under load”. The post also notes that it will still be some time before the board is available at retail, but they’re working on it. The Star64 is the first board in a whole range of RIAC-V computing products from Pine64, so the company clearly wants to get it right.

Pine64’s other news includes a new version of the Pinecil temperature-controlled soldering iron, which itself uses a RISC-V processor, and may be available by the time you read this. Plus the shipping of the first batch of QuartzPro64 boards to developers. This board is powered by the eight-core RK3588 chipset, and should make a very interesting addition to the maker space when it becomes generally available.

A group of researchers from the Università di Bologna and Cineca has explored an experimental eight-node 32-core RISC-V supercomputer cluster. The demonstration showed that even a bunch of humble SiFive's Freedom U740 system-on-chips could run supercomputer applications at relatively low power. Moreover, the cluster worked well and supported a baseline high-performance computing stack.

Need for RISC-V

One of the advantages of the open-source RISC-V instruction set architecture is the relative simplicity of building a highly custom RISC-V core aimed at a particular application that will offer a very competitive balance between performance, power consumption, and cost. It makes RISC-V suitable for emerging applications and various high-performance computing projects that cater to a particular workload. The group explored the cluster to prove that RISC-V-based platforms can function for high-performance computing (HPC) from a software perspective.

"Monte Cimone does not aim to achieve strong floating-point performance, but it was built with the purpose of 'priming the pipe' and exploring the challenges of integrating a multi-node RISC-V cluster capable of providing an HPC production stack including interconnect, storage, and power monitoring infrastructure on RISC-V hardware," the description of the project reads (via NextPlatform).

For its experiments, the team took an off-the-shelve Monte Cimone cluster consisting of four dual-board blades in a 1U form-factor built by E4, an Italian HPC company (note that E4's Monte Cimone cluster consists of six blades). The Monte Cimone is a platform 'for porting and tuning HPC-relevant software stacks and HPC applications to the RISC-V architecture,' so the choice was well justified.

The Cluster

The Monte Cimone 1U machines utilized two SiFive's HiFive Unmatched developer motherboards powered by SiFive's heterogeneous multicore Freedom U740 SoC that integrates four U74 cores running at up to 1.4 GHz and one S7 core using the company's proprietary Mix+Match technology as well as 2MB of L2 cache. In addition, each platform has 16GB of DDR4-1866 memory and a 1TB NVMe SSD.

Each node also sports a Mellanox ConnectX-4 FDR 40 Gbps host channel adapter (HCA) card, but for some reason, RDMA did not work even though the Linux kernel could recognize the device driver and mount the kernel module to manage the Mellanox OFED stack. Therefore, two of the six nodes were equipped with Infiniband HCA cards with a 56 Gbps throughput to maximize available inter-node bandwidth and compensate for the lack of RDMA.

One of the critical parts of the experiment was porting essential HPC services required to sun supercomputing workloads. The team reported that porting NFS, LDAP and the SLURM job scheduler to RISC-V was relatively straightforward; then, they installed an ExaMon plugin dedicated to data sampling, a broker for transport layer management, and a database for storage.

Results

Since using a low-power cluster designed for software porting purposes for actual HPC workloads does not make sense, the team ran HPL and Stream benchmarks to measure GFLOPS performance and memory bandwidth. The results were a mixed bag, though.

The peak theoretical performance of SiFive's U74 core is 1 GFLOPS, which suggests that a peak theoretical performance of one Freedom U740 SoC should be 4 GFLOPS. Unfortunately, each node only reached a sustained 1.86 GFLOPS performance in HPL, which means that an eight-node cluster's peak compute capability should be in the 14.88 GFLOPS ballpark assuming a perfect linear scaling. The whole cluster reached a sustained peak performance of 12.65 GFLOPS, which is 85% of the extrapolated attainable peak. Meanwhile, due to relatively poor scaling of the SoC, 12.65 GFLOPS is 39.5% of the entire machine's theoretical peak, which may not be that bad for an experimental if we do not take the poor scaling of the U740 model into consideration.

Regarding memory bandwidth, each node should yield about 14.928 GB/s of bandwidth using one DDR4-1866 module. In reality, it never went above 7760 MB/s, which is not a good result. Actual benchmark results in upstream, unmodified Stream are even less impressive as a 4-threaded workload only attained bandwidth of no more than 15.5% of the available peak bandwidth, which is well below results of other clusters. On the one hand, these results demonstrate mediocre memory subsystem of the Freedom U740, but on the other hand they also show that software optimizations could improve things.

In terms of power consumption, the Monte Cimone cluster delivers just what it promises — it is low. For example, the actual power consumption of one SiFive Freedom U740 peaks at 5.935W under CPU-intensive HPL workloads, whereas in idle, it consumes around 4.81W.

Summary

The Monte Cimone cluster used by the researchers is perfectly capable of running an HPC software stack and appropriate test applications, which is already good. In addition, the SiFive's HiFive Unmatched board and E4's systems indulge in software porting purposes, so the smooth operation of NFS, LDAP, SLURM, ExaMon, and other programs was a pleasant surprise. Meanwhile, the lack of RDMA support was not.

"To the best of our knowledge, this is the first RISC-V cluster which is fully operational and supports a baseline HPC software stack, proving the maturity of the RISC-V ISA and the first generation of commercially available RISC-V components," the team wrote in its report. "We also evaluated the support for Infiniband network adapters which are recognized by the system, but are not yet capable to support RDMA communication." 

But actual performance results of the cluster fell short of expectations. Such effects fell under the condition of the mediocre performance and capabilities of the U740, but software readiness played a role. That said, while HPC software can work on RISC-V-based systems, it cannot deliver on the expectations. It will change once developers optimize programs for the open-source architecture and proper hardware is released.  

Indeed, the researchers say that their future work involves improving the software stack, adding RDMA support, implementing dynamic power and thermal management, and using RISC-V-based accelerators. 

As for hardware, SiFive can build SoCs with up to 128 high-performance cores. Such processors are for data center and HPC workloads, so expect them to have proper performance scalability and a decent memory subsystem. Also, once SiFive enters these markets, it will need to ensure software compatibility and optimizations, so expect the chipmaker to encourage software developers to tweak their programs for the RISC-V ISA.

SK Hynix was the first memory vendor to start talking about HBM3 and was the first company complete development of memory under that spec. Today the company said that it had begun to mass produce HBM3 memory and these DRAMs will be used by Nvidia for its H100 compute GPUs and DGX H100 systems that will ship in the third quarter.  

SK Hynix's HBM 3 known good stack dies (KGSDs) offer peak memory bandwidth of 819 GB/s, which means that they support data transfer rates of up to 6400 GT/s. As for capacity, each stack packs eight 2GB DRAM devices for a total of 16GB per package. SK Hynix also has 12-Hi 24GB KGSDs, but since Nvidia seems to be the company's primary customer for HBM3, the company kicks off production with 8-Hi stacks.  

The start of HBM3 mass production is good news for SK Hynix's bottom line; for a while, at least, the company will be the only supplier of this memory type and will be able to charge a hefty premium for these devices. What is important for SK Hynix's public image is that it is beginning mass production of HBM3 ahead of its arch-rival Samsung.

Eventually, SK Hynix and other makers of memory will offer HBM3 packages with up to 16 32Gb DRAM devices and with capacities of 64GB per KGSD, but this is a longer-term question.

Nvidia's H100 compute GPU is equipped with 96GB of HBM3 DRAM, though because of ECC support and some other factors, users can access 80GB of ECC-enabled HBM3 memory connected using a 5120-bit interface. To win the contract with Nvidia, SK Hynix has worked closely with the company to ensure perfect interoperability between the processor and memory devices. 

"We aim to become a solution provider that deeply understands and addresses our customers’ needs through continuous open collaboration," said Kevin (Jongwon) Noh, president and chief marketing officer at SK Hynix. 

But Nvidia will not be the only company to use HBM3 in the foreseeable future. SiFive taped out its first HBM3-supporting system-on-chip on TSMC's N5 node about a year ago, so the company can offer similar technology to its clients. Furthermore, Rambus and Synopsys have both offered silicon-proven HBM3 controllers and physical interfaces for quite a while and have landed numerous customers, so expect an arrival of various HBM3-supporting SoCs (primarily for AI and supercomputing applications) in the coming quarters.

This week, Intel and the Barcelona Supercomputing Centre (BSC) said they would invest €400 million (around $426 million) in a laboratory that will develop RISC-V-based processors that could be used to build zettascale supercomputers. However, the lab will not focus solely on CPUs for next-generation supercomputers but also on processor uses for artificial intelligence applications and autonomous vehicles. 

The research laboratory will presumably be set up in Barcelona, Spain, and will receive €400 million from Intel and the Spanish Government over 10 years. The fundamental purpose of the joint research laboratory is to develop chips based on the open-source RISC-V instruction set architecture (ISA) that could be used for a wide range of applications, including AI accelerators, autonomous vehicles, and high-performance computing. 

The creation of the joint laboratory does not automatically mean that Intel will use RISC-V-based CPUs developed in the lab for its first-generation zettascale supercomputing platform but rather indicates that the company is willing to make additional investments in RISC-V. After all, last year, Intel tried to buy SiFive, a leading developer of RISC-V CPUs and is among the top sponsors of RISC-V International, a non-profit organization supporting the ISA.  

While around $21.3 million is a significant sum of money, Intel will be pouring a lot more into its x86-based products in the coming years, so spending on RISC-V processors does not mean a lower focus on x86 designs. On the contrary, throughout its history, Intel invested hundreds of millions in non-x86 architectures (including RISC-based i960/i860 designs in the 1980s, Arm in the 2000s, and VLIW-based IA64/Itanium in the 1990s and the 2000s). Eventually, those architectures were dropped, but technologies developed for them found their way into x86 offerings. 

With its RISC-V efforts, Intel could be killing several birds with one stone. First, suppose engineers from the joint laboratory manage to design a CPU technology that is more suitable for ZettaFLOPS-class supercomputers. In that case, Intel will be able to use it for its products. As an added bonus, Intel’s Foundry Services division will likely become a fab of choice for CPUs/SoCs developed in the joint lab. 

“High-performance computing is the key to solving the world’s most challenging problems, and we at Intel have an ambitious goal to sprint to zettascale era for HPC,” said Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel. “Barcelona Supercomputing Center shares our vision for this goal, with equal emphasis on sustainability and an open approach. We are excited to partner with them to embark on this journey.” 

Last year Intel set itself an ambitious goal to build a ZettaFLOPS-class supercomputer platform by 2027, which means to increase the performance of supercomputers by 1000 times in about five years. The company said it would need new compute architectures, new system architectures, high-speed memory and I/O interfaces, novel fabrication technologies, and sophisticated chip packaging methods, among other things. One of the company’s ways to radically improve compute performance is to build an architecture that would combine the company’s x86 general-purpose cores with Xe-HPC compute GPUs. The first product that uses this concept is Falcon Shores — which is already in development. 

AMD's Radeon Technology Group (RTG) is hiring a RISC-V CPU/GPU designer for its existing team of architects developing embedded RISC-V CPUs. A new job posting indicates that the development of RISC-V-based solutions is well underway at AMD, whereas the fact that Radeon Technologies Group is hiring specialists could give a hint about the applications RTG is working on. 

The job description provides some general details about AMD's expectations from its RISC-V micro-architect/RTL designer. The company is looking for a specialist with experience in high-performance GPUs; RISC-V RV64 CPUs; and CPUs with out-of-order execution, speculative execution, and branch predictors.  

According to the job posting, AMD has a team working on embedded RISC-V CPUs at AMD's Radeon Technologies Group in Orlando, Florida. The new candidate is expected to know and improve "existing and emerging graphics/compute paradigms and new APIs employing RISC-V processors." Also, they will have to analyze CPU workloads and make recommendations for improvements as well as understand bottlenecks and other challenges where an embedded CPU will improve performance. 

Evidently, AMD's Radeon Technologies Group does not develop its own CPUs, so we are probably not going to see AMD-branded RISC-V CPUs (or licensable RISC-V embedded CPU cores/designs) from RTG. Modern GPUs could use embedded CPUs for a variety of tasks, including managing certain onboard functions for a GPU, or could even be expanded for more exotic purposes, like running an operating system or processing general-purpose tasks such as fetching data from storage devices. RISC-V designs could also be used for other purposes, like security by providing a hardware-based root of trust. 

At this point, we don't know exactly what kind of RISC-V CPU cores AMD's Radeon Technologies Group is developing, but we do know that Nvidia uses RISC-V microcontrollers on its own GPUs to manage certain on-board functions.

The RISC-V open-source architecture is exceptionally well suited for emerging applications, so it's possible that AMD is working on something new. Meanwhile, since we are dealing with a 64-bit RISC-V architecture, we can be fairly sure that this is not a simplistic microcontroller.

SiFive this week announced that due to challenges with components supply, it would discontinue its current-generation HiFive Unmatched boards for RISC-V software and hardware developers. Instead, the company will focus on developing and producing next-generation HiFive single-board computers. 

"With such great ecosystem adoption, demand has exceeded our already high expectations, and we are close to selling out our production inventory," Phil Dworsky of SiFive announced at SiFive Forums (via Hackster.io). "Given the challenge of supply chain issues that we overcame for the first run of these boards (issues that we continue to face), we have decided to focus on the next generation SiFive HiFive development systems rather than trying to put together another build of the HiFive Unmatched platform in 2022." 

Today's SiFive HiFive Unmatched development board is based on the company's Freedom U740 system-on-chip that can run high-level operating systems. It features PCIe 3.0 x8/16 and M.2 slots along with GbE and USB ports. The board was a fine solution for RISC-V developers in 2020, but it may not be the most optimal choice for today's realities. This is probably one of the reasons why the company decided to focus on next-generation hardware instead of ordering another batch of the HiFive Unmatched.

About two years ago, most RISC-V developers designed solutions for rather simplistic products running RISC-V SoCs, and some focused on projects requiring a high-level OS. This made the Freedom U740 an optimal choice. But now that SiFive is looking at high-performance SoCs with up to 128-cores for datacenter applications, the Freedom U740 is not the optimum choice for developers building server-grade software or hardware for the upcoming RISC-V SoCs. Meanwhile, high-performance processors make no sense for developers of less sophisticated applications. So perhaps in the future, it is more reasonable for SiFive to offer a variety of HiFive boards targeting different applications. 

SiFive yet has to formally announce details about the future of its HiFive Unmatched products. 

"Our sincere apologies to anyone wanting a SiFive HiFive Unmatched board who has been unable to obtain one — please stay tuned for news on the next generation HiFive development systems soon," added Dworsky.

As one of the main driving forces behind the RISC-V architecture, SiFive tends to introduce and showcase RISC-V solutions not available from anyone else in the industry. This week the company demonstrated the industry's first RISC-V cluster that could be used for high-performance computing.

The four-way cluster built by AB Open is based on four SiFive HiFive Unmatched developer motherboards each featuring a Freedom U740 system-on-chip for compute tasks as well as a SiFive HiFive1 Rev. B development board providing control of four relays used to power on/off the four boards. Each HiFive Unmatched motherboard with the Freedom U740 SoC is an individual system that can run high-level operating systems and is equipped with PCIe 3.0 x8/16 and M.2 slots as well as GbE and USB ports.  

The Freedom U740 SoC barely offers decent performance for modern HPC applications, but SiFive has the capability to build SoCs with up to 128 high-performance cores. Companies that are interested in designing or using such processors need to ensure that they have proper software for RISC-V, and these boards should help drive the development of such apps. 

Since the intention was to build a relatively powerful rackmount system with multiple RISC-V processors (which were never meant to support symmetric multiprocessor technology) and convenient controls, an additional motherboard for controls was needed. That board is connected to a PSU and manages the power distribution to fans and supply sequencing for the HiFive Unmatched boards, each of which is connected to an individual Pico-ATX power supply. Also, the control board connects each GbE port, thus enabling their remote control. 

AB Open and SiFive say that the cluster can be used for typical data center or office workloads, but its main purpose is to enable software development and testing. Those who want to try using RISC-V for HPC applications can use multiple clusters to build farms and take advantage of multiple RISC-V cores.

San Francisco-based fabless semiconductor provider SiFive today announced a new processor it describes as “the fastest licensable RISC-V processor IP core in the market”. The SiFive Performance P650.

The SiFive Performance P650 will feature up to 16 cores and build upon the current SiFive Performance P550 processor, maintaining an efficient core pipeline while expanding the processor instruction-issue width to deliver an impressive (predicted) 40% performance increase per clock cycle and an overall 50% performance gain compared to SiFive’s previous fastest processor thanks to additional architecture enhancements.

Though we don’t have exact clock speeds, or many other details, for the new chip right now, the previous-generation four-core P550 ran at 2.4GHz on a 7nm process. It outperformed an Arm Cortex-A75 chip by 31% in SPECint2006, according to figures from SiFive. What we do know is that it’s a 64bit design with hypervisor and virtualization support, plus ‘advanced cryptographic features’. Its modular design is aimed toward use in clusters, and it’s expected to be used in data centers, cars, airplanes, and mobile networking contexts.

“With the new SiFive Performance P650 processor, SiFive’s engineering team has rapidly and successfully delivered a significant performance uplift for the SiFive processor family,” said Rohit Kumar, senior vice president of engineering at SiFive. “SiFive’s rapid execution and expertise is on display as we build world-class products and serve high-performance markets. At SiFive, we’re determined to push the envelope of performance and demonstrate RISC-V has no limits, and the SiFive Performance P650 is the next step in a far-reaching product development roadmap.” 

Preview versions of the chip are expected to be offered to lead customers in the first quarter of 2022, with general availability coming in the middle of the year.

A new single-board computer based on the RISC-V architecture has been revealed by StarFive, who previously announced, then cancelled the Beagle V in 2021. The $149 VisionFive V1 as reported by Liliputing looks set to be a rival for the Raspberry Pi .

Measuring 3.9 x 2.8 inch the board is slightly larger than a Raspberry Pi 4 and features a 1.5 GHz dual-core SiFive U74 RISC-V processor. The RISC-V CPU is backed by 8GB of LPDDR4 and a micro SD card slot, plus HDMI 1.4, gigabit Ethernet, 3.5mm audio out, 4 x USB 3.0 type-A ports and a type-C for power. There's Wi-Fi 4 and Bluetooth 4.2 onboard, and you get a 40-pin GPIO header which appears to be Raspberry Pi compatible, but the proof of this lies in software support. There are two MIPI connectors for use with compatible cameras and displays. 

The news follows the launch last week of the LycheeRV board from Sipeed, and the announcement from Canonical earlier this year that Ubuntu would support the open-source architecture. The VisionFive board will ship with support for a different flavor of Linux, Fedora (for which there's an image on GitHub) but we don’t know exactly when that will be yet. A set of slides for a talk due to be given at the RISC-V Summit on December 8 have leaked, and suggest a retail price of $149.

A second board, the VisionFive V2, is mentioned in the slide deck, and features a quad-core processor with GPU, plus support for HDMI 2.0 and PCIe 2.0 x2.

SiFive emerged from stealth mode as a developer of small, low-power cores for microcontrollers in 2016. By late 2020, the company had a chip that could run Linux and this week said that it developed a CPU core that is comparable to modern offerings designed by Intel and Arm. The company believes that such high-performance designs could be used for a wide variety of applications, including server-grade system-on-chips with 128-cores.

SiFive's next-generation high-performance core "is within reach of Intel's Rocket Lake family […] and Arm's Cortex-A78 design […] in terms of single-core performance," James Prior, senior director of product marketing and communications at SiFive, told The Register. The details are scarce at the moment, but Prior implies that the next generation core is architecturally similar to its existing Performance P550 design, but is enhanced in all directions to extract higher performance.

SiFive's Performance P550: Fast

Earlier this year SiFive introduced its new Performance-series P550 general-purpose core based on the company's 64-bit U84 microarchitecture with a 13-stage, triple-issue, out-of-order pipeline that is aimed at multi-core application processors. The P550 core features private 2x32KB L1 and 256KB L2 caches, a data precision FPU with bit manipulation extensions, and support for multicore coherence configurations with up to four cores with a unified 4MB L3 cache in a core complex. 

The company claims that the P550 core measures 0.23 mm2 when implemented in a 7 nm fabrication process and can operate at around 2.40 GHz. As for performance, the P550 delivers a SPECINt 2006 score of 8.65/GHz, which is comparable to performance of contemporary Arm and x86 cores. Meanwhile, SiFive says that the P550 offers a three times performance uplift per mm2 compared to Arm's Cortex-A75.

The P550 is available for licensing from SiFive. Since this is only a CPU core, licensees can add all kinds of special-purpose accelerators, IP, and I/O interfaces to them to get a unique system-on-chip that will address their needs (or targeted market segments/workloads).

SiFive's Performance P550: Furious… With up to 128 Cores per SoC

SiFive's next-generation core for performance demanding applications seems to be based on a very similar microarchitecture as the P550, but this one is actually a quad-issue out-of-oder microarchitecture with a higher performance per clock. In addition to a wider issue, the future core will also have larger L1 caches (up to 128KB), and up to 2MB private L2 cache. In addition, it supports multicore coherence with up to 16 cores with 16MB L3 cache in a complex.  

SiFive claims that the next-gen Performance core can offer 50% higher performance compared to the P550. Furthermore, it will be possible to scale designs all the way to 128 cores and address performance-hungry applications. Since SoCs with 128 cores are used in virtualized environments, the core also adds features like hypervisors and interrupts. Meanwhile, with performance-per-core on par with Arm's and Intel's latest microarchitectures, SiFive's next-generation core could address high-performance computing (HPC) applications over time, just as envisioned by RISC-V International, the organization that oversees the development of the RISC-V instruction set architecture. Though, we would expect HPC customers to want something more proprietary from SiFive.

Available Next Year

James Prior says that the next generation core will be available as an RTL deliverable next year. Customers will also be able to test drive the core on FPGA models.

While Intel was interested to acquire RISC-V processor developer SiFive and SiFive is considering its strategic options, the companies could not agree neither on financial terms nor on how SiFive technologies could be used at Intel reports Bloomberg. The latter company is still considering both an initial public offering (IPO) as well as a takeover by a larger player. 

SiFive is a world's leading developer of RISC-V-based processor cores and a contract designer of system-on-chips. Earlier this year it was reported that Intel had offered $2 billion for the startup and the two companies entered negotiations over other terms. As it turns out, the companies reportedly could not agree on financial terms and on how SiFive technologies would be integrated into Intel's roadmap. For obvious reasons, neither of the parties has issued a comment because the talks were private.

There are several reasons why Intel wanted to buy SiFive. Firstly, there are many applications that are beyond x86's reach that Intel would certainly like to address. The x86 market is limited to perhaps 350 ~ 360 million units per year. If Intel manages to get into RISC-V world early enough, it will be able to offer its customers high-volume low-power solutions produced at its own fabs several years down the road, which will greatly diversify the company's products offerings. 

While Intel could certainly develop and offer its own RISC-V cores to attract designers of SoCs for emerging applications, taking over a renowned RISC-V company with IP, clients, and people familiar with the ISA could be a preferable way to enter the RISC-V world. 

RISC-V is a dynamically developing open-source instruction set architecture (ISA) that is supported by multiple industry giants, including Google, Huawei, and Western Digital. While previously RISC-V cores could only address simplistic microcontrollers, today they can be used for more demanding applications and even run Linux. Adopters of RISC-V do not have to pay royalties for ISA and some of RISC-V cores are available free of charge. Meanwhile, there are commercial RISC-V implementations that should be licensed from their developers, yet even in this case there is no need to pay for the ISA itself. 

While Intel could certainly develop and offer its own RISC-V cores to attract designers of SoCs for emerging applications, taking over a renowned RISC-V company with IP, clients, and people familiar with the ISA could be a preferrable way to enter the RISC-V world. 

RISC-V is a dynamically developing open-source instruction set architecture (ISA) that is supported by multiple industry giants, including Google, Huawei, and Western Digital. While previously RISC-V cores could only address simplistic microcontrollers, today they can be used for more demanding applications and even run Linux. Adopters of RISC-V do not have to pay royalties for ISA and some of RISC-V cores are available free of charge. Meanwhile, there are commercial RISC-V implementations that should be licensed from their developers, yet even in this case there is no need to pay for the ISA itself. 

Si-Five is ahead of many RISC-V adopters and has better chances to address emerging applications that are not yet addressed either by x86 or by Arm architectures. To develop more competitive offerings, SiFive reportedly plans to expand its CPU development team form 200 to 400 engineers, which is why it needs money, either from private investors or from large companies. 

Intel updated its lineup of the famous Nios soft processors with the latest Nios V softcore, designed around the open-source RISC-V instruction set architecture.

The Nios family of processors is Intel's implementation of simple low-power processors designed to fit inside Field Programmable Gate Array (FPGA) designs and occupy just a tiny portion of it, supplying basic CPU functionality. According to Gartner, the Nios CPU family is the most widely-used softcore tech in the FPGA industry. These soft cores allow FPGA designs to have the basic functionality that the design would require from a CPU. This way, the company provides hardware designers with basic CPU needs with their Intel FPGAs, enabling faster hardware development.

The industry is becoming more interested in the open RISC-V ISA, and according to recent reports, Intel has also expressed interest in purchasing RISC-V startup SiFive for $2 billion. That makes plenty of sense given the wide range of applications that RISC-V can satisfy, just as we see with the Nios V soft cores. 

The importance of using RISC-V as an ISA template for these types of cores lies with the open-source hardware initiative that aims to open the whole ecosystem, making it accessible to anyone.

The Nios II, a predecessor of Nios V, is Intel's 32-bit digital signal processing (DSP) and system control based on reduced instruction set computer (RISC) design principles. The Nios II iteration is a 32-bit RISC CPU with 32 general-purpose 32-bit registers, a complete 32-bit instruction set, data path, address space, and single-instruction 32 × 32 multiply and divide, producing a 32-bit result. While we don't know the details of Nios V, we assume it is very similar.

For now, the Nios V is a microcontroller in the V/m form. This design uses the RV32IA part of the RISC-V specification with atomic extensions, a 5-stage pipeline, and AXI4 interfaces, creating a capable microcontroller design. However, Intel plans to continue engineering Nios V design IPs and develop a Linux-capable V/g general-purpose Nios V form of processor capable of running Linux kernel.

The introduction of Nios V means that Intel is finally jumping on the RISC-V open-source bandwagon. The company already offers some of the first designs based on the open ISA, and in the future, we could see more powerful designs emerge from Intel's design centers. 

As we can see with the new Mikron MIK32 chip, the open-source RISC-V architecture opens doors for companies to redevelop existing microcontrollers. That's becoming even more important as countries around the world look to wean themselves off of Western technologies. But just how feasible is that approach?

Inherited from the USSR, the modern Russian Federation has its own CPU architecture (Elbrus) and platforms to build PCs and servers. In addition, there are Russian companies that develop various Arm-based system-on-chips and controllers. The country also has 300-mm equipment purchased from AMD's fab near Dresden in the early 2000s. This means that, in theory, Russia could build CPUs for its own domestic needs (yet it will hardly satisfy even 50% of its needs as most programs are designed for x86 or Arm processors).

But there are some major caveats. Elbrus processors were designed to power specific mission-critical applications and cannot be efficiently used for all types of workloads. In addition, other CPU architectures are developed in the UK and the US, actual logic chips are built in Taiwan. In fact, nearly all supporting ICs and microcontrollers are developed in Europe or the USA. That makes it impossible for Russia to replace any significant portion of technology it uses with its own homegrown chips. This is where Zelenograd-based Mikron comes into play with its MIK32 chip based on the RISC-V architecture. 

The Mikron MIK32 is a classic microcontroller featuring an RV32IMC core that runs at 32 MHz. It also comes with all types of I/O, including I2C, UART, SPI, ADC, DAC interfaces, as well as numerous timers and an interrupt controller, reports CNX Software. The microcontroller can be used for various applications, including gas/water meters, industrial sensors, and healthcare equipment. These devices have a very long lifecycle, which could be a problem for the MIK32.  

As noted by CNX Software, MIK32's functionality mimics that of the widely-used ST Microelectronics' STML0 microcontroller, so swapping out the chips will require a lengthy validation process. Mikron has a development board to make the potential transition easier and faster, but only time will tell whether its customers will actually use the MCU. 

A company would rarely want to swap out a microcontroller on a long-life device, so we shouldn't expect the Mikron MIK32 to replace a large number of STM's chips in the coming years. Yet, the fact that Mikron has developed such a RISC-V-based MCU indicates that RISC-V is certainly getting traction.

RISC-V is a novel processor instruction set architecture (ISA) developed at UC Berkely. Originally designed for teaching purposes, the ISA has been released as an open-source, license-free template that is used for now millions or even billions of applications. However, as an average PC user, how could you use a RISC-V processor? Well, according to this week's announcement coming from StarFive (as reported on Lilliputing), you could be looking at a RISC-V-powered PC rather soon.

This approach has caught the attention of many board makers, and today we are presented with a single-board computer (SBC) from StarFive, that is powered by RISC-V ISA technology. In a joint venture with Radxa, the two hardware developers have announced that the duo will be producing an SBC powered by RISC-V processor, coming towards the end of Q3 2021.

The new board is using StarFive's JH7100 processor, based on a 28nm semiconductor node. It uses two SiFive's U74 cores that are modestly powerful to run many tasks with ease. While these cores are not the fastest on the market, they are a rough equivalent of Arm's Cortex-A55 designs. Alongside the CPU, there are additional IPs like Nvidia's NVDLA neural network accelerator with Vision DSP Tensilica-VP6 for computing vision.

We have already covered the implementation of StarFive's JH7100 processor here. The SBC was a joint collaboration between Seeed Studio and Beagleboard, however, the product was later aborted, and the development efforts have continued now with the StarFive and Radxa collaboration.

" The single-board computer will be officially released by the end of Q3 2021, and the next-generation JH7110 chip with new GPU feature support will soon be mass-produced.," notes the StarFive announcement, continuing that "Work-related to the development platform has been fully carried out." This notes that the updated JH7110 chip will feature a usable GPU for 3D workloads., unlike the JH7100 which doesn't feature a GPU.

The RISC-V ISA is free. You don't need special licenses in order to use it, and the documentation is fully open to anyone. Even the development of the ISA is done publicly with the help of open-source contributors, making it a unique approach in the world dominated by closed-source ISAs.

When SiFive introduced its HiFive Unmatchd RISC-V desktop motherboard for developers last year, it was clear from the start that sooner or later an enthusiast would attempt to try using its U7 SoC for something it is not meant for: general PC usage with high-performance graphics and video decoding. That time has come as an enthusiast has managed to make AMD's Radeon RX 6700 XT work with a RISC-V SoC under Linux. 

Computer scientist René Rebe decided to prove that the SiFive HiFive Unmatched not only can run Linux, but can also use a high-performance graphics processor, reports Hackster.io. To do so, he spent 10 hours patching the Linux kernel to add support for AMD's Radeon RX 6700 XT graphics card as well as the Mesa Gallium 21.1.5 driver. 

Rebe not only managed to make AMD's Radeon RX 6700 XT display Linux's GUI, but he even made it render 3D graphics in a hardware-accelerated mode and decode video. He did not try to launch games (there are certain limitations with video decoding) but as this is the world's first attempt to make a high-performance GPU work with RISC-V, the endeavor can be considered a success. 

SiFive's HiFive Unmatched board with the Freedom U740 SoC has all the PC I/O interfaces that PC users are used to, including PCIe 3.0 x8/16, M.2 slots, and USB ports. To that end, it is possible to install almost any piece of modern hardware into a PC powered by the HiFive Unmatched board. After all, the board is designed for developers working on client PC and server software for upcoming RISC-V SoCs. There is a limitation though: Linux does not support RISC-V properly since most RISC-V-based chips are microcontrollers that cannot run high-level operating systems. While there are some RISC-V SoCs that can run them (e.g., the Freedom U740), they are not particularly fast.

There are more details about the SiFive Unmatched RISC-V motherboard with AMD's Radeon RX 6700 XT experiment at Bits inside by René Rebe YouTube channel.

Canonical have announced that its Ubuntu operating system now supports two RISC-V boards from SiFive, the HiFive Unleashed and HiFive Unmatched.

SiFive might sound familiar. That’s because Intel has reportedly offered to acquire the company for $2 billion, said it will make SiFive’s chips, and revealed plans to incorporate the new SiFive P550 processors into its 7nm Horse Creek platforms.

The HiFive Unleashed and HiFive Unmatched preceded those announcements. The HiFive Unleashed has actually been discontinued, so curious enthusiasts who haven’t already purchased one will have to opt for the HiFive Unmatched instead.

“The availability of Ubuntu running on the HiFive boards comes as the result of the joint work between Canonical and SiFive engineering teams,” Canonical said in yesterday’s announcement. “Canonical’s team is engaged in an ongoing process of porting Ubuntu to HiFive boards, backed by the SiFive engineering team, as part of a long-term collaboration between the two companies.”

Why bother? Canonical said it was because “RISC-V has a lot of potential and is becoming a competitive ISA in multiple markets” and that meant “porting Ubuntu to RISC-V to become the reference OS for early adopters was a no-brainer.”

The deal should make SiFive’s products (and therefore RISC-V) more accessible to many people. Ubuntu might not be everyone’s favorite Linux distro, but it’s stable, and it’s easier to develop for an established operating system than a blank canvas.

There are currently three Ubuntu images available to SiFive customers. The HiFive Unleashed supports the current Ubuntu 21.04 release as well as the Ubuntu 20.04 long term support (LTS) release. The HiFive Unmatched can run Ubuntu 21.04 .

SiFive, the leading designer of chips based on the open source RISC-V architecture, announced its new SiFive Performance line of chips today that support 64-bit operating systems, like Linux. The company claims the P550's processors are the fastest RISC-V cores on the market and beat Arm's Cortex-A75 chips in terms of area efficiency. Perhaps not so surprisingly, Intel, which has reportedly offered $2 billion to buy the plucky startup, also announced that it would adopt the designs for use in its future 7nm Horse Creek platforms.

Intel hasn't shared many details of its Horse Creek development platform yet, but given that it uses the company's yet-to-be-released 7nm process, we expect the test chips to arrive in the 2022/2023 time frame. Intel will incorporate its own leading-edge interface IP, like DDR and PCIe, into the chip and notes that the 7nm Horse Creek platform is "a valuable and expandable development vehicle for cutting-edge RISC-V applications." As such, we imagine the project could expand to other connectivity options in the future, like the accommodations needed for 3D, chiplet, or tile-based processor designs.

Intel also says that it plans to "showcase to mutual customers" the P550 design incorporated into its Horse Creek platform. Hence, it's rational to think Intel could eventually productize a design as part of its pledge to produce RISC-V chips based on SiFive's designs. That will come through its new IDM 2.0 initiative that will find Intel operating as a third-party foundry for other chip companies (much like TSMC).

RISC-V is most commonly used in microcontrollers and small, simple chips, earning it quite the industry uptake. SiFive's Performance series is an application processor-class design, meaning the chips have a memory management unit (MMU) that enables running an operating system — in this case, Linux (albeit that doesn't mean as a general-purpose machine). This is preferable to the stripped-down real-time operating systems (RTOS) commonly used for embedded applications.

SiFive claims that its new Performance P550 core is the highest-performance RISC-V processor on the market, delivering a SPECINt 2006 score of 8.65/GHz that's comparable to existing proprietary application processors. The P550 scales up to four cores that can be crammed into the same amount of silicon area as a single Arm Cortex-A75 core, yet SiFive says it beats the A75 in performance metrics. The P550 comes with SiFive's U84 microarchitecture with a thirteen-stage, triple-issue, out-of-order pipeline.

The Performance P270 slots in as the lower-performance eight-stage, dual-issue, in-order processor that supports RISC-V Vector Extension v1.0, which SiFive says makes it an ideal candidate to replace SIMD architectures. SiFive also offers its Recode software to translate existing SIMD software from existing 'legacy' architectures to RISC-V vector assembly code.

RISC-V is evolving into more expansive use cases as the architecture matures. The RISC-V organization plans to evolve the standard to accommodate faster chips for high-performance applications in the future.

SiFive revealed the broad strokes of its new Performance platform today, but there's still much more to learn as it works its way to market. That starts with a July 14th webinar that will expand on the details. You can register here.

The open source RISC-V instruction set architecture is gaining more mainstream attention in the wake of Intel's rumored $2 billion bid for SiFive, the industry's leading RISC-V design house. Unfortunately, RISC-V has long been relegated to smaller chips and microcontrollers, limiting its appeal. However, that should change soon as RISC-V International, the organization that oversees the development of the RISC-V instruction set architecture (ISA), has announced plans to extend the architecture to high performance computing, AI, and supercomputing applications.

The RISC-V open-source ISA was first introduced in 2016, but the first cores were only suitable for microcontrollers and some basic system-on-chip designs. However, after several years of development, numerous chip developers (e.g., Alibaba) have created designs aimed at cloud data centers, AI workloads (like the Jim Keller-led Tenstorrent), and advanced storage applications (e.g., Seagate, Western Digital).

The means there's plenty of interest from developers for high-performance RISC-V chips. But to foster adoption of the RISC-V ISA by edge, HPC, and supercomputing applications, the industry needs a more robust hardware and software ecosystem (along with compatibility with legacy applications and benchmarks). That's where the RISC-V SIG for HPC comes into play. 

At this point, the RISC-V SIG-HPC has 141 members on its mailing list and 10 active members in research, academia, and the chip industry. The key task for the growing SIG is to propose various new HPC-specific instructions and extensions and work with other technical groups to ensure that HPC requirements are considered for the evolving ISA. As a part of this task, the SIG needs to define AI/HPC/edge requirements and plot a feature and capability path to a point when RISC-V is competitive against Arm, x86, and other architectures. 

There are short-term goals for the RISC-V SIG-HPC, too. In 2021, the group will focus on the HPC software ecosystem. First up, the group plans to find open source software (benchmarks, libraries, and actual programs) that can work with the RISC-V ISA right out of the box. This process is set to be automatized. The first investigations will be aimed at applications like GROMACS, Quantum ESPRESSO and CP2K; libraries like FFT, BLAS, and GCC and LLVM; and benchmarks like HPL and HPCG. 

The RISC-V SIG-HPC will develop a more detailed roadmap after the ecosystem is solidified. The long-term goal of the RISC-V SIG is to build an open-source ecosystem of hardware and software that can address emerging performance-demanding applications while also accomodating legacy needs.

How many years will that take? Only time will tell, but industry buy-in from big players, like Intel, would certainly help speed that timeline. 

According to Bloomberg's sources, Intel has offered $2 billion for startup chip designer SiFive, though neither company has officially acknowledged the offer. SiFive is the leading designer of chips based on the open source RISC-V architecture that has coincidentally attracted much more interest in the wake of Nvidia's ongoing acquisition of Arm for $40 billion. The reports of the possible SiFive acquisition come on the heels of SiFive's announcement that it will collaborate with Intel's newly-christened foundry services.

SiFive, most recently valued at $500 million, is reportedly considering takeover offers from multiple firms and it may still choose to remain an independent outfit. Much of the new interest in SiFive and RISC-V stems from firms looking to avoid any potential pitfalls due to Nvidia's potential control of Arm. 

RISC-V is an open source instruction set architecture (ISA) for RISC chips that discards the traditional notion of licensing fees associated with designing chips around a certain ISA, as we see with Arm. The ISA is maintained by the non-profit RISC-V International organization comprised of more than 1,000 members in 50 countries.

RISC-V is most commonly used in microcontrollers and small, simple chips, which has earned it quite the industry uptake with companies like WD, which ships over two billion RISC-V controllers a year in its products. The RISC-V organization plans to evolve the standard to accommodate faster chips for high-performance applications in the future.

Chinese chip firms have shown a keen interest in RISC-V chip designs in the wake of US restrictions on their use of Arm designs due to US national security interests. Naturally, RISC-V's open source licensing, which eschews fees, and the fact that the company is incorporated in Switzerland and doesn't "take a political position on behalf of any geography" is enticing to Chinese firms. 

Intel CEO Pat Gelsinger's recent announcement that the company would begin licensing its own x86 processor designs to other firms as part of its new IDM 2.0 initiative was surprising, and the company even revealed that it would be open to fabbing third-party Arm designs in its new custom foundry outfit, Intel Foundry Services (IFS).  

If the reports are true, it's natural to expect that Intel will look to add RISC-V designs to its own arsenal and also offer custom designs to customers of its new foundry services business, all of which ties in nicely with the company's pledge to help "re-shore" semiconductor manufacturing in the US. Having yet another ISA in the cannon might also help to fire back at Arm competitors, like Apple's M1 and AWS's Graviton2, in the future. 

Tenstorrent, a developer of heterogeneous processors for AI applications led by ex-AMD engineers Ljubisa Bajic and Jim Keller, has licensed a general-purpose CPU design developed by SiFive based on the RISC-V architecture. Licensing general-purpose cores and IP will speed up time-to-market of Tenstorrent's products. 

Tenstorrent develops high-performance AI training and inference system-on-chip architectures based on its own Tensix processor cores optimized for machine learning (ML). To run traditional workloads, Tenstorrent's SoCs will use SiFive's new general-purpose Intelligence X280 64-bit RISC-V-based cores with fully integrated 512-bit wide RISC-V Vector extension (RVV). SiFive is expected to disclose details about its vector processing solutions later this week at the Linley Spring Processor Conference.  

Along with SiFive's Intelligence X280 IP, Tenstorrent will also get a RISC-V software stack that will further speed up time-to-market for the AI SoC company.  

"SiFive Intelligence is a new initiative dedicated to bringing cutting-edge software and hardware technologies to those looking to innovate in the AI market," said Chris Lattner, President of Engineering and Product at SiFive. "Tenstorrent, with its team of industry leaders and an already impressive track record of silicon success, is an ideal partner for SiFive’s new products targeted at machine learning applications." 

The AI SoC designer has not disclosed all of the specifications of its upcoming processors just yet, but it is now obvious that the company wants its SoC architectures to be capable of general-purpose processing, vector processing (for AI inference and high-performance computing), and ML. Ultimately, Tenstorrent's architectures could be used for a wide variety of applications, including next-generation supercomputers that require both AI and HPC capabilities. 

Ljubisa Bajic and Jim Keller spent decades working on x86-based designs at AMD. Keller has also worked on multiple Arm-based designs while at Apple. The very fact that Tenstorrent chose to use SiFive-developed RISC-V CPU design is noteworthy by itself and is a testament to the new architecture.

"The Tenstorrent architecture addresses the growing demands that come with data-written code as part of Software 2.0," Keller said in a press release. "We are excited to partner with SiFive because of their ability to deliver CPUs and software for the modern RISC-V ecosystem."

SiFive on Tuesday said that that its OpenFive division has successfully taped out the company's first system-on-chip (SoC) on TSMC's N5 process technology. The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs. Meanwhile, elements from this SoC can be licensed and used for other N5 designs without any significant effort.

The SoC contains the SiFive E76 32-bit CPU core(s) for AI, microcontrollers, edge-computing, and other relatively simplistic applications that do not require full precision. It uses OpenFive's D2D (die-to-die) interface for 2.5D packages as well as OpenFive's High Bandwidth Memory (HBM3) IP subsystem, which includes a controller and PHY that supports data transfer rates of up to 7.2 Gbps.

The announcement represents a milestone for SiFive and OpenFive, as the SoC is the first RISC-V-based device to be made using a 5nm node. Meanwhile, the announcement also contains two interesting facts. The first one is of course OpenFive's implementation of an HBM3 solution and its rather bold data transfer rate expectation (2X compared to the fastest HBM2E available today). The second one is OpenFive's D2D interface for chiplets that uses 16 Gbps NRZ signals with clock forwarding architecture, comprised of 40 IOs per channel, and provides throughput of up to ~1.75Tbps/mm. 

The current design will hardly ever be used 'as is', but parties interested in building a high-performance 5nm RISC-V SoC for AI or HPC applications can take it as a the base design and equip it with their own or third-party IP (e.g., custom accelerators, high-performance FP64-capable cores, etc.).

Alternatively, all three key components of the SoC implemented using TSMC's N5 node — the E76 core, the D2D interface and its physical implementation (which includes built-in PLL, programmable output drivers, and link training state machines), and the HBM3 memory solution (controller, I/O, PHY) — can be licensed separately.

The tape out means that the documentation for the chip has been submitted for manufacturing to TSMC, which essentially means that the SoC has been successfully simulated. The silicon is expected to be obtained in Q2 2021.

The RISC-V CPU architecture is making progress across a plethora of devices. From soldering irons and watches to desktop computers, the open source RISC-V CPU looks set to make an impact in 2021. Seeed Studio and Beagleboard have today announced an official collaboration with StarFive, a leading RISC-V solutions provider. The focus of this announcement is the Beagle V, an affordable single board computer (SBC) which runs Linux and is powered by a dual core RISC-V.

Powering Beagle V is a dual core 64-bit U74 RISC-V CPU clocked at 1.5 GHz and up to 8GB of LPDDR4 RAM. From a CPU perspective Beagle V looks to be slightly faster than a Raspberry Pi 4, but looking at the StarFive JH7100 System on Chip (SoC) we can see a Tensilica-VP6 used in computer vision projects, an Nvidia Deep Learning Accelerator (NVDLA) used for artificial intelligence and finally a Neural Network Engine. All of these point towards a board that looks on paper to be quite the AI / machine learning powerhouse. Best of all Beagle V is a purely open source product, with both the hardware and the software offered under an open source licence.

At its heart, Beagle V is still an SBC and as such it has what we come to think as the "standard complement" of ports. With four USB 3.0 ports, Gigabit Ethernet, Micro SD card and a single HDMI port, capable of 1080P 30fps. A 40 pin GPIO suggests compatibility with Raspberry Pi HATs, and a casual glance at the pinout shows that the standard digital I/O, I2C and SPI seem to be mapped correctly. Dual camera (CSI) and a single display connector (DSI) suggest that Beagle V may be compatible with the official Raspberry Pi camera and display. Wireless connectivity is provided via 2.4 GHz WiFi and Bluetooth 4.2. A shame that 5 GHz WiFi and Bluetooth 5.0 are not present, but we can live without it. Power is provided via a USB-C port, and from the datasheet we can see that Beagle V requires 5V at 2A but a 3A supply would be a real benefit.

Starting from $119 for the 4GB model, or $149 for the 8GB, Beagle V is slightly more expensive than a Raspberry Pi 4 but for RISC-V and AI enthusiasts this is a small price to pay for a RISC-V machine of such power. With an anticipated early access release date of March, with larger availability from September 2021, Beagle V looks to be a worthy contender to the Nvidia Jetson for AI and machine learning projects. It may not be a direct competitor to the Raspberry Pi, but it will be interesting to put the two against one another to see both of their pros and cons.

Learning to code can be fun, and with boards such as the Raspberry Pi and the upcoming BBC Doctor Who HiFive Inventor Coding Kit a collaboration between BBC Learning, Tynker and SiFive we can learn new skills and save the galaxy while traveling with Doctor Who. This $75 kit provides the equipment and story lead lessons to develop your own sci-fi themed projects. 

The hand shaped board developed by SiFive is powered by a 150 MHz RISC-V SiFive RISC-V FE310-G003 processor, an open source alternative to x86_64 and ARM processors. This choice of processor is unusual, typically boards of this nature are powered by chips from Arm or Atmel. RISC-V has yet to enter the mainstream maker community, but could this be the first commercial board aimed at children?
The HiFive comes with onboard Wi-Fi and Bluetooth enabling creation of IoT projects. Onboard sensors for light, orientation and direction provide interesting ways to provide input for experiments. A 6 x 8 RGB LED matrix provides a colorful method of output.

The HiFive features an edge connector very similar to that used on the micro:bit, whether this is fully compatible remains to be seen and we shall be testing the board as soon as they are released.

Writing code for the HiFive is made possible using the Tynker block programming language and the child's learning is supported via a series of lessons told as stories in the Doctor Who franchise. The block language is aimed at children from seven years upwards, but an optional MicroPython library will enable older children to use the board for more advanced projects.

The kit will retail for $75 and will be available via Amazon from November 23, known to fans as Doctor Who Day.

SiFive has introduced its first desktop-class motherboard powered by a RISC-V system-on-chip (SoC) that's designed for Linux software developers, just as it promised last month. The HiFive Unmatched announced this week is a Mini-ITX platform for desktops and has all the industry-standard PC interfaces that software makers might need now -- and at least a couple of years to come.  

SiFive's first RISC-V CPU cores from 2016 were primarily aimed at microcontrollers and simplistic SoCs for low-power devices. Eventually, the company became much more ambitious and launched U-series, Linux-capable 64-bit application processor cores, as well as S-series 64-bit cores designed for mission critical or deterministic processing. T

hese cores allow SiFive to play on the same field with Arm's A-series and R-series cores, but since RISC-V doesn't have an ecosystem comparable to Arm's, for now U-series and S-series IP cores are reserved for select projects and developers who do not need advantages offered by Arm. 

In a bid to build software and hardware ecosystems around RISC-V cores, SiFive has developed its HiFive Unmatched motherboard that allows engineers to run programs (both applications and drives) on RISC-V. 

The HiFive Unmatched platform is based on the SiFive FU740 heterogeneous multicore SoC that packs four U74 cores and one S7 core using the company's proprietary Mix+Match technology. The combination of cores enables the chip to address developers of both performance-demanding and real-time applications.

The Mini-ITX motherboard features a standard ATX power connector, 8GB of DDR4 RAM and 32MB of QSPI flash memory. It also has a GbE port and USB 3.2 Gen 1 connectors. Meanwhile, developers can also use a PCIe 3.0 x8 slot for graphics cards or FPGAs, a microSD slot, an M.2-2230 slot for Wi-Fi/Bluetooth adapters and an M.2-2280 slot for high-end SSDs with a PCIe 3.0 x4 interface. 

With a motherboard like the HiFive Unmatched, developers could build low-power desktops akin to those based on x86 processors and then test whatever they need to test. Of course, popularity of the board will depend on the interest for RISC-V in general, but considering the number of RISC-V backers, SiFive should sell quite a lot of these. 

SiFive's HiFive Unmatched is $665 and will be available directly from the company shortly . The board will ship with a bootable SD card that includes Linux and system developer packages.

Many leading analysts agree - Nvidia's recently-announced ARM acquisition will result in broader industry uptake of the open-source RISC-V CPU architecture, and SiFive, one of the major driving forces behind the RISC-V CPU architecture, made a timely announcement today. 

SiFive disclosed plans to provide interested software designers with desktop PCs running a RISC-V chip to assist of software development or porting to the open-source CPU architecture. The announcement comes as the open-source RISC-V CPu architecture enjoys more interest in the wake of Nvidia's acquisition of ARM.

SiFive also said it would announce RISC-V processing cores that support the latest RISC-V vector (RVV) extensions and can run high-level operating systems in October. RVV will enable RISC-V CPUs to address performance-demanding applications.

High-level OS-Capable RISC-V CPUs with Vector Extensions

SiFive introduced its first RISC-V CPU cores back in 2016 targeting microcontrollers and simplistic SoCs for low-power devices. Last year, the company added U8-series out-of-order processor cores into its IP portfolio to address performance-demanding applications. At this year’s Linley Group Fall Processor Conference, SiFive plans to disclose additional details regarding its upcoming Linux-capable superscalar multi-core processor design that will feature the latest RISC-V Vector extensions. 

Vector extensions, such as Intel’s AVX, are used to more efficiently process vectorized data sets and are commonly used by high-performance computing and multimedia applications. Introducing vector extensions to RISC-V will bring the architecture closer to Arm, PowerPC as well as x86 and will allow it to compete for modern performance-demanding applications, such as AI and ML.

SiFive Development PC Incoming: U7-Based Desktop

Having secured over 100 design wins to date, SiFive is interested in making the RISC-V architecture more widespread. To make this happen, it plans to provide RISC-V-based PCs to developers to enable them to create applications compatible with the instruction set.

The PCs will be based on the yet-to-be announced SiFive Freedom U740 SoC that features a heterogeneous core complex combined with modern PC interfaces and expansion capabilities. The desktop computer will come with a set of tools to develop bare-metal or Linux-based applications as well as to port existing programs to the new hardware platform.

Source: SiFive