SK hynix early on Friday announced that it had decided to abandon plans for a potential initial public offering (IPO) of Solidigm, its U.S.-based enterprise SSD subsidiary, citing unfavorable stock market conditions and semiconductor share price trends. At the same time, SK hynix confirmed it plans to build a new fab for Solidigm in the U.S. to address growing demand for enterprise SSDs. Although an IPO could have helped finance a new fab in the U.S., SK hynix claims that its subsidiary’s expansion remains a priority.

Solidigm specializes in high-capacity data center SSDs based on floating gate 3D QLC NAND memory. As AI infrastructure deployments accelerate, demand for high-capacity storage increases, whereas Solidigm's existing manufacturing capacity is barely sufficient to address its projected needs. Consequently, SK hynix believes that Solidigm requires additional production facilities in the U.S., although it has yet to disclose the planned fab's capacity, investment requirements, or construction schedule. Such a facility could also strengthen SK hynix's American manufacturing footprint, which is important, given the current environment and on-shoring trends.

SK hynix had considered multiple options — including direct investment, a pre-IPO funding round, and IPO of Solidigm — to finance capacity expansion. An IPO would have enabled SK hynix to raise capital from outside investors without taking on more debt. Furthermore, it could have revealed the true value of the subsidiary, which SK hynix believes is not properly reflected in its own market capitalization. In addition to financing the expansion, the proceeds could have been used for dividends, share repurchases, and share cancellations.

However, SK hynix says that increased market volatility and the ongoing correction in semiconductor stocks have made an IPO less attractive. As a result, the company believes that current market conditions would prevent Solidigm from achieving a valuation that adequately reflects its growth prospects. Consequently, it has discontinued its review of both pre-IPO financing and an IPO, even though it will continue to evaluate alternative funding mechanisms.

The cancellation of the IPO raises an obvious question: why would SK hynix abandon a financing mechanism that could provide billions of dollars for Solidigm's expansion just as demand for enterprise SSDs is at a record high and set to increase further over the next couple of years? After all, constructing a modern 3D NAND fab requires tens of billions of dollars, and external financing could reduce the burden on SK hynix's balance sheet and preserve capital for other projects (e.g., new capacity elsewhere).

One possible explanation is Solidigm's exceptionally strong profitability. Micron's enterprise storage division recently reported a non-GAAP gross margin of 90%, and given Solidigm's unique position in the market (it controls 21.1% of the enterprise SSD market together with its parent company), its margins may well be higher as it sells exclusive products. If extraordinary margins are sustainable over the next two or three years, its operations could substantially boost SK hynix’s consolidated profitability and generate considerable cash for future investments. Given these circumstances, SK hynix could potentially finance Solidigm's U.S. manufacturing expansion through a combination of internally generated cash and debt even without diluting its ownership. Financing the entire project with cash alone may also be possible, even though such an approach would be less likely given the massive capital requirements of advanced semiconductor production facilities nowadays. In any case, it is natural for SK hynix to prefer retaining full ownership of a highly profitable subsidiary to selling part of it at a valuation it considers inadequate.

The two biggest NAND flash memory manufacturers on the planet, Samsung Electronics and SK Hynix, are reportedly working to upgrade their Chinese factories to produce more advanced chips for use in AI data centers, Reuters reports. The move comes as the two companies continue to fight off competition from the fast-growing Chinese memory makers like CXMT. Fierce competition in the lucrative AI RAM market has already seen manufacturers slash consumer-focused production to allow them to increase production capacity for the more advanced — and money-spinning — components.

Citing four people familiar with the companies' plans, the report claims that Samsung Electronics aims to switch its Xian plant to the production of 286-layer flash chips by the end of the year. SK Hynix has its sights set a little lower, targeting chips with 240 or more layers at its Dalian facility. That factory was taken over back in 2021, but a timescale for the new upgrades isn't clear.

However, while Samsung Electronics and SK Hynix are well placed to deal with the growing threat from Chinese chipmakers, both are faced with additional complications in the form of U.S. regulations. Export controls on chipmaking equipment were applied in 2022, with the aim of slowing China's technological progress. Both companies, based in South Korea, must now get licenses in order to install U.S.-built hardware in Chinese factories. The report points to this as a reason for the recent growth of Chinese firms like Yangtze Memory Technologies Co. (YMTC). The company told investors at a recent IPO preparation meeting that it aims to become the world's largest NAND flash producer by the end of 2027.

While both Samsung Electronics and SK Hynix say that they are working in consultation with the U.S. authorities, there's little doubt that this extra step has hampered the companies' ability to upgrade their factories to better meet the new AI memory demand.

It's impossible to overstate just how key Samsung and SK Hynix are to NAND supply. Samsung's Xian factory produces around 40% of the company's global output. It currently produces chips that have around 200 layers, but Samsung's plans aim to boost that to 286 layers for V9 NAND chips. For its part, SK Hynix's Dalian plant currently produces chips with 192 layers, with the company's aim for 240-layer chips reportedly confirmed by three people familiar with the plans.

Meanwhile, CXMT, China's premier chipmaker, is looking to move beyond DRAM production. A report from September 2026 noted that it was eyeing production of 3D NAND memory for use in solid-state storage (SSD) products. The country's largest DRAM producer, CXMT, posted $22.41 billion in revenue and $11.57 billion in net profit in the first half of 2026 after years of losing money. But despite this purple patch, the company is still much smaller than the likes of Samsung, SK Hynix, and Micron.

Original report follows:

Reports that Solidigm was considering building a 3D NAND fab in the U.S. came as a surprise last month, as no company has manufactured leading-edge NAND flash memory in America for years. However, the potential investment now appears to be part of a calculated move by Solidigm's parent, SK hynix, which is reportedly asking the U.S. government to authorize additional semiconductor manufacturing equipment shipments to its Dalian facility in China in exchange for a commitment to build a new NAND fab in the U.S., according to Reuters.

The Dalian fab is the world's only facility to produce 192-layer floating gate 3D NAND for Solidigm's data center-grade SSDs for AI, enterprise, and hyperscale data centers. Its manufacturing operations rely on equipment from major American suppliers, including Applied Materials, KLA, and Lam Research, whose exports to China require a license from the U.S. government. Although the U.S. authorities tend to authorize shipments of some tools to semiconductor facilities in the People's Republic that are operated by multinational companies like Samsung or SK hynix, they only want to keep the fabs running, as they are against expansions of capacity of fabs in China or introducing new manufacturing technologies to these facilities.

Solidigm has requested U.S. export licenses for additional tools, but the U.S. government has yet to authorize the shipments. Last December, the U.S. Commerce Department granted SK hynix a limited authorization for equipment deliveries to Dalian for 2026, but it has not issued a similar equipment export authorization for 2027, according to Reuters. In a bid to persuade the U.S. government to authorize shipments of necessary tools to its Dalian facility, SK hynix proposes to build a 3D NAND facility in America. This would fill an important gap in the Trump administration’s efforts to bring semiconductor manufacturing back to the U.S.

SK hynix's Solidigm subsidiary wants to install additional manufacturing equipment in the unused portions of its Dalian Mod B facility, which was completed in 2023. The company never fully equipped the building because of the memory market downturn at the time, so while some production tools are installed, substantial space remains unused and is available for additional tools. Given that Solidigm sells every single SSD it produces, unused capacity means lost revenue. Meanwhile, because the building was completed in 2023, installation of tools into that facility does not constitute a capacity expansion.

Additional NAND production in China could generate profits that Solidigm could use to finance its proposed American fab and support its operations until domestic manufacturing capacity becomes available. The company is also considering an initial public offering as early as 2027 to raise additional capital.

Solidigm has previously confirmed its commitment to further development of floating-gate 3D NAND technology. In an interview with Tom's Hardware at Computex 2026, Avi Shetty, who leads Solidigm's AI solutions and ecosystem business, said that the company intended to develop 5^th and 6^th Generation floating-gate NAND beyond its existing 192-layer technology. He also emphasized the importance of maximizing factory utilization and profitability. However, he did not disclose plans to expand manufacturing output at the company's Dalian facility, not to mention a new fab in the U.S.

Nonetheless, the new reports about SK hynix's intentions clearly indicate that the company not only intends to keep developing new generations of Solidigm's floating-gate NAND, but also to expand its production in China and the U.S.

Elon Musk has criticized memory makers for what he calls 'extortionate' pricing amid an unprecedented shortage of both conventional DRAM and high-bandwidth memory (HBM). Although Musk did not identify the companies he criticized, his remarks seem to be directed at Samsung Electronics and SK hynix, as he praised Micron for its more 'reasonable' approach at the same time. Interestingly, Micron also enjoys exceptionally high profitability: its latest quarterly gross margin reached 81%.

"Micron has been reasonable regarding future memory prices, while others have been extortionate, which is something today's customers will not forget," Musk wrote in a post on X. "Micron is making the smart move for long-term customer loyalty."

Musk did not provide specific details of said extortionate pricing or disclose terms offered by different memory suppliers (which tend to be confidential). Consequently, it is impossible to determine whether Samsung and SK hynix charge substantially more than does Micron for comparable products. Nevertheless, Musk's remarks suggest considerable frustration with the pricing policies of South Korean memory manufacturers.

Over the past several quarters, memory has transformed from an easy-to-obtain commodity to a strategic asset, and makers of 3D NAND and DRAM have certainly benefitted massively from this shift. Historically, memory makers have responded to strong demand and rising prices with aggressive capacity expansions, which eventually led to oversupply and falling prices. This time around, however, manufacturers have raised memory prices severalfold without comparable increases in production capacity. As a result, supply still lags behind demand and will continue to do so for years to come, which puts further upward pressure on memory prices.

What makes Musk's praise of Micron particularly interesting is the company's financial performance, which clearly suggests that the company is taking advantage of the situation in the market. In its fourth quarter of fiscal 2026, Micron reported revenue of $54.23 billion and a GAAP gross margin of 81%, up from 40% a year earlier. The company's cloud memory unit earned $16.283 billion, and its non-GAAP gross margin totaled 83%; its core data center storage business sold goods worth $18.002 billion with a 90% gross margin; while sales of the automotive and embedded units totaled $6.824 billion with gross margins reaching 84%.

Perhaps the most surprising part of Micron's last quarter report was its mobile and client revenue of $13.114 billion and non-GAAP gross margin of 90%, which means that Micron earned higher profit selling memory and storage for client devices than it did for selling memory solutions for data centers. Such results clearly indicate that even supposedly reasonable memory prices can generate extraordinary profits in the current market.

Memory manufacturers are increasingly shifting toward long-term supply agreements (LTAs) that guarantee future supply and provide customers with predictable prices of DRAM, HBM, and NAND. So far, Micron has signed 26 strategic customer agreements that cover more than 35% of its expected revenue through 2030. These contracts include $32 billion in customer financial commitments, most of which consist of cash deposits. The company acknowledges that its new agreements reflect higher prevailing memory prices, and it by no means is trying to sell memory at a discount.

Samsung has reportedly secured long-term contracts covering 75% – 80% of its planned memory output in 2027, according to South Korea's ⁠Korea Economic Daily (via @Jukan05). SK hynix is reportedly pursuing similar arrangements as AI infrastructure investments continue to absorb available memory capacity.

Market insiders and analysts expect memory supply shortages to persist through at least 2028, and that gives manufacturers considerable leverage in contract negotiations. Memory suppliers have little incentive to reduce prices and are eager to enjoy their position, but Musk's warning suggests that today’s pricing policies could influence customer relationships once supply and demand eventually return to balance.

SK hynix has detailed plans to reduce reliance on power-hungry CPU cores with an in-house core named a Hynix Transaction Processing Unit (H-TPU). Not to be confused with an AI accelerator, an H-TPU would assist with repetitive work handled by an SSD, which usually demands more cores on a controller as drives get faster. These new cores are placed in clusters and would handle routine I/O with a four-stage, in-order pipeline, while management is left to the traditional Arm CPU. The new, tiny cores are claimed to draw only about 2.5% of a general-purpose CPU core’s power, with just around 4% of its area. Now, the company plans to apply H-TPU across its portfolio of products, TheElec reports.

The company’s VP of system-on-chip (SoC) design, Koo In-jae, spoke at ISOCC 2026, the International SoC Design Conference, earlier this week, saying that SSD controller CPUs are at their limit on power and area. In the talk, titled “From SSD Controllers to AI Memory SoCs,” he said that PCIe bandwidth doubles every generation, and controller CPU clocks and control capability reportedly can’t keep up. SK hynix reportedly plans to apply H-TPU across its NAND products, including next-gen enterprise SSD controllers. That’s where the unending chase for IOPS makes the problem most evident.

Koo’s comments underline the issue of scaling, which is evident in the “more cores” solutions found in competitor products. Marvell’s PCIe 6.0 Bravera SC6 uses 12 Cortex-R82 cores in two six-core clusters with three Cortex-M7 cores and a secure Cortex-M3. Compare this to its PCIe 5.0 predecessor, the Bravera SC5, which lists 10 Cortex-R8 and Cortex-M7 cores plus a Cortex-M3 for security. Core counts have climbed with PCIe speeds out of necessity.

SK hynix’s answer is a core of its own design: the H-TPU, kept small and programmable. It comes with a dedicated compiler and other development tools for specialized code. It’s stated to use a four-stage pipeline with in-order, or sequential, execution. It is not superscalar, does not use out-of-order units, and should not be confused with a tensor processor for AI. It is designed to handle read and write command processing, manage metadata, and handle buffer control, all repetitive tasks.

Storage control requires more than 100 detailed functions, which is not ideal for a monolithic CPU. Instead, SK hynix broke those functions up and spread them across “dozens of small TPU clusters,” according to ZDNet Korea (translated). Each H-TPU therefore has a specialized job. The total number of H-TPUs is more than 100; the function count above is a separate figure. However we currently have no details on how many cores each cluster holds.

The main CPU still handles error recovery and exception handling, plus storage-policy management, so the H-TPU complements the CPU: offloading, not replacement. The design idles the cores a given I/O doesn’t need, which reportedly drop into a minimum-power mode. Neither report names the CPU core behind SK hynix’s 2.5% power and 4% area figures.

Splitting the workload this way is not a new idea. Phison’s CoXProcessor, which pairs Cortex-R5 cores with hardened macros to offload repetitive firmware at wire speed, has been in products for some time. The company’s E18 SSD controller uses two lower-clocked Cortex-R5 cores to supplement the three main ones. On the enterprise side, Phison’s X1 used two Cortex-R5 cores plus up to 32 “micro cores,” each dedicated to one or two tasks. H-TPU takes this approach to a larger scale.

While the talk itself is light on detail, we discovered multiple SK hynix patents that describe a similar split between small cores and a CPU. U.S. patent 11,675,537, first filed in Korea in November 2020, details a CPU-run control plane and an I/O plane of many small processors, sorted into four groups by job. A command passes through all four in order: host for ingestion, cache, map, and NVM to the NAND. The processors “configure a pipeline for the data I/O operation” this way, letting the CPU handle any exceptions. That pipeline runs across many cores and is unrelated to the four-stage pipeline inside each H-TPU.

In the patent’s example, each small core is around “200,000 logic gates” rather than the “seven million logic gates” of the CPU, or about 2.9% of the CPU’s gate count. These are not fixed elements, as “firmware may be driven in each of the TPUs,” making them more adaptable than the hardware circuits the patent calls “difficult to modify.” The patent spells out TPU as “Tensor Processing Units,” but, again, this should not be confused with AI accelerators. H-TPU shares that programmable approach, but the next step SK hynix described moves some routine jobs into fixed hardware.

This next step is hardware automation (HWA), with command processing, address lookup, and buffer copies moved to dedicated circuits. The CPU and H-TPUs still handle exceptions and key policy decisions. Moving to this framework is meant to keep completion times predictable, which is necessary with I/O, especially for today’s high-IOPS enterprise SSDs.

SK hynix has filed on fixed-hardware paths before, with a 2014 filing by its San Jose-based unit and, later, with U.S. patent 12,216,914, first filed in Korea in 2022. The latter describes a “write automation circuit” and says “a task without intelligent control can be handled or processed through the hardware layer,” while firmware keeps jobs such as garbage collection. The former went further, sending basic I/O commands down a path “completely implemented in hardware,” with anything it couldn’t handle being sent upstream.

The H-TPU itself is reportedly being used in “Storage Next,” Nvidia’s name for the joint AIN P project with SK hynix. Storage Next targets 512-byte or more limited access with NAND, which traditionally aims at higher operating sizes. SK hynix also plans to apply it to high-bandwidth flash (HBF), which the outlet said is due next year. HBF stacks NAND dies for AI inference, targeting high-bandwidth memory (HBM) levels of bandwidth but with far more capacity, with up to 512GB per stack versus 64GB for HBM4.

For HBF, AI inference reads outnumber writes around 300,000 to 1, with the AI compiler and runtime passing pre-analyzed dataflow to the HBF SoC. Proper buffer management and prefetching based on that dataflow are meant to hide the slow NAND latency behind compute. Size is important in HBF stacks, so a traditional multi-core Arm design is likely less practical.

H-TPU has yet to be proven in an actual enterprise SSD controller product, and no date has been given. The move from general-purpose CPU cores to specialized single-job cores and circuits matches the type of workload SSDs handle, and the demands on storage are only increasing as AI servers become memory-constrained.

SK hynix’s statements and patents support an evolution to H-TPU and beyond to HWA, with H-TPU itself headed for traditional NAND and next year’s HBF. SSD controller manufacturers must be willing to adapt, as simple scaling is suboptimal even at current PCIe levels, let alone the speeds promised for PCIe 7.0 and 8.0, the latter headed for final ratification in 2028.

Memory prices are at record highs due to demand from the AI sector and are not going to drop any time soon. In fact, the cost of manufacturing memory chips on a per-area basis can be higher than the price of silicon processed using TSMC's N2 and N3 fabrication technologies, which are used to make compute chips, according to an observation made by Kurnal Insights. While the comparison has merit, it has an important caveat.

Based on media leaks, Kurnal from Kurnal Insights considers that a 300-mm wafer processed using TSMC's N3 technology costs $20,000, which translates to approximately $0.283 per mm² when the wafer price is divided by its area. For TSMC's N2, the analyst assumes a considerably higher wafer price of $30,000, or around $0.424/mm². These calculations are based on unofficial information and do not account for unusable wafer edges, dicing, test structures, defects, or yield, so they should be viewed as nominal wafer-area prices rather than the actual price of usable silicon.

The calculation for DRAM works differently. Kurnal assumes a DRAM price of $1.50 per Gb and then multiplies it by the bit density of different generations. At 0.219 Gb/mm², 1y DRAM works out to $0.329/mm², whereas 1z DRAM with its 0.273 Gb/mm² density reaches $0.410/mm². Finally, 1b DRAM at 0.436 Gb/mm² produces a figure of $0.654/mm², considerably higher than the nominal $0.424/mm² calculated for an N2 wafer.

There is an important distinction here. The N2 and N3 numbers represent assumed prices charged by TSMC for processing a wafer, whereas the DRAM figures represent the potential selling value of the memory contained within a square millimeter of silicon, thus illustrating how much revenue a DRAM maker can theoretically get from a given die area at the assumed memory price.

Interestingly, Kurnal Insights' $1.50/Gb assumption is almost exactly in line with the current spot price of DDR5 eTT memory. According to DRAMeXchange, 16Gb DDR5 eTT chips carried a session-average price of $24.80 on September 21, equivalent to $1.55/Gb. At that price, 1b DRAM with a density of 0.436 Gb/mm² would be valued at approximately $0.676/mm², just 3% above Kurnal's $0.654/mm² estimate.

It goes without saying that producing DDR5 memory is considerably cheaper than making logic chips using TSMC's N3 process technology. However, with DRAM in short supply, memory makers are getting considerably more money for their silicon than they did historically.

There are a few important caveats that make the comparison somewhat less straightforward. The calculations do not account for packaging costs, with logic requiring more expensive techniques. Additionally, TSMC manufactures chips on a contract basis, and the actual price of a processed wafer depends on the volumes, customer, and other commercial terms. Thus, comparing estimated TSMC wafer prices with DRAM spot prices is not exactly an apples-to-apples comparison. Even TrendForce notes that DDR5 spot procurement remains limited and transactions are sporadic, which means spot prices do not necessarily reflect the prices at which Micron, Samsung, and SK hynix sell the bulk of their DRAM.

Therefore, contract DRAM prices would provide a considerably better basis for an economically meaningful comparison. However, we do not know contract prices, and while they are clearly higher than historical memory prices, they may not be as high as spot prices. To that end, we cannot state for sure that DRAM makers get more money for their wafers than TSMC does for its logic wafers.

Even as chipmakers race to build the most advanced chips inside the United States, experts are saying that their efforts are facing one monumental challenge: a massive shortage of skilled workers to run the fabs and factories. According to CNBC, global consulting firm McKinsey and the SEMI Foundation suggest the industry will have up to 157,000 positions that could remain unfilled by 2030.

“I’m concerned,” Samsung semiconductor division EVP Jon Taylor told CNBC in an interview. “We just don’t see that there’s enough technical people in the pipeline.” The McKinsey report says that only 3% of U.S. engineering graduates end up working in the semiconductor industry, and that 73% of chip companies are finding it hard to fill engineering roles. This is a huge contrast to other tech jobs, which saw record layoffs by June of this year, when over 40,000 positions were axed, ostensibly largely due to AI.

The massive demand for memory and storage chips driven by the AI boom, combined with Washington’s efforts to bring semiconductor manufacturing back to the United States, has led to the buildup of multiple fabs and facilities dedicated to it. TSMC was one of the first companies to kick off this building spree, when it started construction on its Arizona campus in 2021. The site started churning out chips last year, with the company committing another $100 billion in July 2026 to build four more 2nm fabs. Intel’s Ohio One plant, which was, at one point, America’s largest fab complex, is also underway, with the site expected to start production between 2030 and 2031.

The big three memory makers — Micron, Samsung, and SK hynix — are also planning or have recently completed major expansions in the U.S. Samsung is starting advanced semiconductor manufacturing in the U.S., with its Taylor, Texas, fab entering risk production this year. The fab is targeting an output of 50,000 wafer starts per month, and it is expected to create 3,500 jobs. “We’re hiring engineers, we’re hiring technicians, we’re hiring people in the supply chain,” Taylor told the publication. “Everybody wants and needs the same thing, and it’s a bit of a race against time right now as everything is starting to come online.”

Micron is also currently building its Boise, Idaho, memory chip fab, which began construction in 2022 and is projected to begin wafer production by 2027. The company has also formally broken ground on its $100-billion New York “megafab,” with aims to produce 40% of its global output within the U.S. by the 2040s. Aside from these massive manufacturing sites, it has also committed $10 billion toward new research labs in the U.S., to be built near the global Micron R&D center in Boise.

Finally, SK hynix also started construction of its first HBM plant in the U.S., with its West Lafayette, Indiana, campus dedicated to packaging these crucial components for AI data centers. There have also been rumors that the South Korean company is in talks with Intel to either lease space at its Ohio One factory or launch a joint venture alongside other AI hyperscalers to build memory chips in the U.S.

All these construction projects, plus the requisite supply chains, will necessitate thousands of workers. Local universities like Purdue University and Arizona State University are already investing millions of dollars to help prepare a capable workforce, with the former launching degrees in 2022 focused on semiconductors. Samsung and Intel are also investing in various programs, including internships and scholarships, to help secure a future workforce for the companies.

However, salary is one major concern listed by the SEMI Foundation. U.S. chip fabs typically pay $127,000 to $187,000, with senior staff getting $238,000 or more. While this is a more-than-competitive salary in the U.S., it’s dwarfed by the bonuses recently offered by Samsung and SK hynix in South Korea, which have reached hundreds of thousands of dollars. With the projected worker shortfall, we should expect the job offers from these semiconductor companies to catch up with their eastern counterparts if they want to secure and maintain talent here in the U.S.

South Korean memory chip manufacturer SK hynix is in talks with Intel to start manufacturing inside the U.S., according to Reuters. The company is reportedly considering multiple options, including leasing space at the under-construction Intel Ohio One site and forming a joint venture with Intel and other AI hyperscalers desperate for HBM.

This move could help alleviate the memory shortage. It would also complement the company’s expansion in Indiana, where it recently broke ground on an HBM packaging plant a few weeks after its historic $26.5-billion Nasdaq listing. It’s unclear yet if these talks are part of the results of the South Korean president’s visit to Silicon Valley in an effort to expedite negotiations between its top tech companies and their U.S. counterparts, but SK Group chairperson Chey Tae-won told reporters in July, “I think we need to build a factory in the United States. If possible, I believe we should build it.”

However, there are also concerns that Seoul might object to such investment. The South Korean government just unveiled a $520 billion investment plan to increase chipmaking capacity within its shores and keep the country competitive in the AI race; at the same time, it’s also in talks with the U.S. to finalize its $350 billion investment commitment to Washington to reduce tariffs on South Korean goods, $200 billion of which is still undecided on which projects it will be deployed on. Meanwhile, the Commerce Department has threatened to impose more tariffs on South Korean and Taiwanese tech companies if they fail to invest in U.S. manufacturing. This potentially puts SK hynix at a precarious position, especially as it balances the demands from the White House and the Blue House.

Neither company has confirmed these rumors, though. SK hynix told Reuters that it’s “reviewing various measures, including establishing additional production bases, to strengthen the competitiveness of its memory business,” but “no matters have been determined at this stage.” On the other hand, Intel called them speculation and declined to comment on the matter, only saying that it was continuing to invest in the Ohio project, which is expected to come online between 2030 and 2031.

High-bandwidth memory (HBM) is one of the key components of AI systems that is not currently assembled in the U.S., but this is going to change in 2029, when SK hynix initiates packaging of HBM memory modules at its facility in Indiana. This week, the company held a groundbreaking ceremony for its HBM production base in America and intends to start construction of the plant shortly.

SK hynix's HBM production site in West Lafayette, Indiana, will specialize in advanced packaging, testing, and R&D of HBM. The facility is set to cost the company around $4 billion, which highlights its advanced technology capabilities as well as vast capacity. The DRAM maker expects to open the cleanroom by October 2028 and begin volume production of next-generation HBM in the second half of 2029, which is about a year later than originally envisioned. Once commercial operations kick off, SK hynix expects the Indiana site to employ around 1,000 people.

Despite being described as an HBM production base, the Indiana site will not manufacture the DRAM wafers, but will package HBM stacks using DRAM wafers produced in South Korea and base dies produced in South Korea, Taiwan, or the U.S. Nonetheless, SK hynix intends to market the resulting devices as its first U.S.-made next-generation HBM products. Meanwhile, as custom HBM-class memory gains traction in the second half of the decade, assembling such stacks close to American customers may be particularly important both for SK hynix and its clients, as it enables SK hynix to shrink the feedback loop significantly.

In addition to building the advanced packaging and testing plant, SK hynix will also establish an Advanced Packaging R&D Testbed next to the manufacturing lines. The facility will enable SK hynix to work with customers, universities, and commercial partners on future packaging technologies, build prototypes, and quickly validate their performance and manufacturability in an actual production environment. In the era of customized HBM, such a facility could become a significant competitive advantage for SK hynix.

SK hynix also signed a memorandum of understanding with Purdue University to jointly research system integration and advanced packaging technologies, including HBM.

"The United States is the epicenter of AI innovation, bringing together premier customers, top-tier R&D capabilities, and partners and Indiana fab will become a gateway to deliver first Made in USA HBM products," said Kwak Noh-Jung, CEO of SK hynix. "We will expand our investments and collaboration in the U.S., grow together, and become the most trusted partner in shaping the future of AI in America."

OXMIQ Labs, a GPU IP company, revealed at Hot Chips 2026 that High Bandwidth Flash (HBF) cannot replace High Bandwidth Memory (HBM) across the vast majority of workloads. For some, HBF could emerge as a specialized memory tier for huge but relatively cold datasets. For others, HBF can do more harm than good.

When SanDisk unveiled its High-Bandwidth Flash (HBF) concept in early 2025, the technology pledged to equip AI accelerators with terabytes of relatively inexpensive memory and reduce the need for traditional High-Bandwidth Memory (HBM), a promise that raised a number of doubts from the very beginning.

The emerging HBF specification includes three performance grades. Grade 1 uses an 8-Hi 256GB NAND stack with an 8 GT/s UCIe interface and 384 GB/s bandwidth. Grade 2 uses a 512GB NAND stack with a 16 GT/s UCIe interface and supports 1.536 TB/s bandwidth. Grade 3 reaches 3.072 TB/s using 32 GT/s UCIe 2.0 while retaining the same 512 GB capacity.

Since HBF relies on 3D NAND, it supports read block sizes between 64 bytes and 4 kilobytes, 4KB writes, and 4KB page sizes. While HBF Grade 1 can barely compete against contemporary HBM, HBF Grade 3 can compete against HBM4E, though we have no idea when such memory will be available. However, the main feature of HBF is not necessarily performance per se, but 8 – 16 times more capacity than HBM at roughly the same cost.

Indeed, OXMIQ believes that HBF should be viewed as a high-capacity memory technology rather than inexpensive HBM. Memory economics depend not only on how many gigabytes an application needs to store, but also on how quickly those bytes must be delivered to the processor. As bandwidth demand rises, adding inexpensive but relatively slow HBF eventually becomes less economical than using HBM, according to estimates by OXMIQ.

Cheap memory =/= cheap tokens

OXMIQ demonstrated the trade-off by modeling a 72-GPU rack running the 1-trillion-parameter Kimi-K2 model at FP4. At cost and power parity, an HBM-only configuration provides 20.7 TB of memory and 1,584 TB/s of aggregate bandwidth. Replacing HBM with HBF increases rack capacity by 14 times to a whopping 294.9 TB, but reduces aggregate bandwidth to 922 TB/s. A hybrid configuration with HBM and HBF provides 89.3 TB and between 279 TB/s and 1,418 TB/s, depending on workload conditions. The difference between HBM and HBF bandwidth is the reason why HBF looks excellent when memory capacity limits the system. However, HBF eventually loses when bandwidth/throughput becomes the limiting factor.

In OXMIQ's model, an HBF-only configuration enables each GPU to hold its own Kimi-K2 instance and run 72 model instances per rack. Whereas an HBM-only configuration requires eight GPUs to hold each model instance (meaning compute performance gets wasted) and can therefore run only nine instances per rack. This makes HBF particularly attractive when memory capacity determines the number of GPUs required. However, as the number of simultaneous users and their token-generation rate increase, HBF's lower bandwidth becomes the bottleneck, while the HBM-based rack can make better use of its substantially higher memory bandwidth and ultimately deliver lower cost per token, according to OXMIQ's model.

As a result, HBF can dramatically reduce the number of GPUs needed simply to accommodate a very large model (i.e., enable one HBF-equipped GPU to do the capacity job of eight HBM-equipped GPUs). Nonetheless, if the objective is maximum inference throughput from a fully utilized rack, HBM may remain the better, more economical choice. At the end of the presentation, OXMIQ concludes: 'HBM for the rack, HBF for the box.'

Niche memory?

Although HBF does not benefit all AI workloads and may even harm the performance of many, there are applications that can benefit from a surplus of local memory.

Mixture-of-experts (MoE) models appear to be particularly suitable for HBF. OXMIQ's Kimi-K3 example has 1.56 TB of weights, of which 1.45 TB, or 93%, consists of MoE expert weights. Since only selected experts are activated for each token, this enormous pool is largely write-once and relatively infrequently read. OXMIQ proposes keeping such experts in HBF while placing the remaining, frequently accessed weights in HBM.

Additionally, more local capacity could also reduce communication between accelerators. Conventional expert parallelism distributes experts across GPUs and requires all-to-all communication at every layer. OXMIQ claims that inexpensive HBF capacity could allow considerably more experts to reside locally, reduce the number of expert-parallel shards, and reduce network traffic. In this case, HBF effectively trades memory capacity for interconnect bandwidth and power consumption.

Long-context inference is another potential use case. Sparse-attention models access only a small portion of their large KV cache during each decoding step, which allows the rest to remain in slower HBF memory. OXMIQ believes that HBF could store this large KV cache while the accelerator fetches only the data needed for each step from HBF to HBM.

The HBM-as-cache idea has a serious limitation. Intuitively, one would put popular experts in HBM and cold experts in HBF. Such a strategy works mainly at low batch sizes or when similar queries can be deliberately batched. As batch size rises and queries become more heterogeneous, however, expert popularity flattens, and the workload accesses a broader range of experts, according to OXMIQ. The working set can then outgrow the relatively small HBM cache, which results in more frequent expert transfers from HBF and reduces the performance benefit provided by HBM caching.

The hardest part

OXMIQ does not expect HBF to work simply as slower GPU memory. Instead, it proposes using HBF in place of host DRAM to store large amounts of less frequently accessed data, such as MoE experts and KV cache. Frequently used data would remain in HBM, while even colder data could still be kept in remote memory or SSDs. This certainly contradicts SanDisk's original vision for HBF: sitting next to AI accelerators. Furthermore, adding HBF support will be complicated on many levels.

The software side of HBF is particularly complicated. To achieve maximum bandwidth, HBF requires large transfers — 64 KB reads and 1 MB writes — and data is moved through DMA rather than the CPU/GPU cache hierarchy. When HBF and HBM are used together, software must also decide which data goes into each memory type and manage HBF's limited write endurance.

Meanwhile, current inference software is not ready for such a configuration. OXMIQ says vLLM would need dedicated HBF support to manage memory allocation and data placement, prefetch data before it is needed, and monitor flash endurance, which requires a major software overhaul. An effort like this has to be a joint effort between the HBF hardware vendors, AI accelerator vendors, and inference-framework developers.

At the lowest level, AMD, Nvidia, and other accelerator vendors would need to provide the hardware/driver/runtime mechanisms for efficiently moving data between HBF and HBM. Then vLLM developers, who work with vendors, would implement the higher-level memory allocator and policies that decide which experts/KV blocks live in HBM and which reside in HBF, when they should move, and how to hide HBF latency.

On the one hand, if AMD or Nvidia adopt HBF, they will provide its partners with everything needed to use it, and while this would take time before everything works as intended, this is a straightforward way to add HBF support to AI platforms. On the other hand, the biggest question is whether hardware vendors like AMD or Nvidia need HBF. As per OXMIQ, HBF's advantage is limited to select use cases, so it may not make sense for AMD or Nvidia to support it universally, especially keeping in mind that managing multi-tier memory hierarchy is hard.

SambaNova is perhaps the most obvious candidate to support HBF. Its SN40L already uses a three-tier hierarchy: SRAM => HBM => DDR, with up to 520MB of SRAM, 64GB HBM, and 1.5 TB of DDR. Conceptually, HBF could become another tier or replace some of that DDR capacity. Then again, this is merely speculation.

HBF remains a nascent technology

While we still have a lot to learn about how HBF works, OXMIQ's model suggests that HBF has a much weaker general-purpose value proposition than the original claim made in early 2025 suggested. It is not useless: it is a specialized solution whose strongest applications depend on particular workload characteristics.

The fundamental problem is that HBF solves memory capacity, while modern AI accelerators are frequently constrained by memory bandwidth. OXMIQ's simulation makes this rather obvious: HBF provides about 14X more memory capacity but only 0.6X the aggregate bandwidth of HBM. Once the workload becomes sufficiently bandwidth-intensive, the enormous capacity stops offsetting the bandwidth deficit.

While the hybrid HBM+HBF solution makes sense for some use cases, it is not a magic fix. When HBM is used as an expert cache, heterogeneous requests at larger batch sizes flatten expert popularity, cause the workload to touch more experts, and reduce cache efficiency dramatically.

For now, HBF has three particularly compelling use cases: reduce the number of GPUs required simply to fit huge models, store massive but infrequently accessed MoE expert pools, and keep large KV caches for sparse long-context inference. For MoE models, its large local capacity could also reduce expert parallelism and expensive all-to-all communication between GPUs. In all three cases, HBF makes sense because capacity requirements are enormous while bandwidth demand remains relatively low.

SK hynix doesn't expect hybrid bonding to be ready for HBM4E, Jaesik Lee, VP of package engineering at SK hynix America, said during a presentation at Hot Chips 2026 on August 23, pushing the industry's most anticipated memory packaging transition out to HBM5 at the earliest.

The problem, as he describes it, is that HBM cubes are capped at a total thickness of 775 microns — the standard thickness of a 300mm logic wafer — so every additional DRAM layer must come from thinner dies and narrower gaps. 16-Hi HBM4, now in customer qualification at 48GB per cube while 12-Hi is in mass production, thins its core dies to around 50 microns and halves the gap between them compared with 12-Hi. Lee's session also went into detail about the company's iHBM cooling architecture three months after its May unveiling. Attaching a constraint to it, Lee explains that the heat blocks can't be applied to any HBM generation already in design.

The 775-micron limit

The JEDEC HBM4 standard raised the package thickness ceiling from 720 microns, which held through HBM3E, to 775 microns, easing the pressures associated with adopting hybrid bonding. When a GPU package gets its cold plate attached, both the logic die and the memory stacks are ground back to expose bare silicon, Lee said, and because logic wafers are 775 microns thick, a memory cube that grew any taller would stand proud of the processor beside it. "That's the kind of limit that we can go up so far, because the logic wafer thickness is also 775 microns," Lee said.

Thinner dies leave the stack with proportionally more oxide, which conducts heat poorly compared with silicon, while pin speeds that have risen from 1 Gbps in early HBM to 8 Gbps in HBM4 concentrate more power in the same footprint. SK hynix's own figures put the thermal burden at 2.2 times higher across the HBM generations shown, while stack counts double every two generations.

The company's mass reflow-molded underfill (MR-MUF) process, which stacks all dies via pick-and-place and joins them in a single reflow, already trades away margin here: filling gaps that have shrunk by half while controlling warpage on sub-50-micron dies is, per Lee, the main manufacturing challenge of 16-Hi.

Hybrid bonding keeps slipping

Samsung publicly committed to hybrid bonding for HBM4 in May last year, with SK hynix holding the copper-to-copper technique as a backup behind advanced MR-MUF. The JEDEC thickness relaxation then removed the immediate need, and industry discussions now weigh a further move to 825 to 900 microns for 20-Hi stacks, which would push the copper-bonding crossover out again.

Back in March, it was claimed by industry sources that SK hynix placed its first mass-production hybrid bonding order, a single inline system pairing Applied Materials and Besi tools worth around 20 billion won ($15 million), and Counterpoint Research expects the technique to enter full-scale HBM production with HBM5 around 2029 to 2030.

Hybrid bonding remains at the research stage for stacks of 20 layers and above, per the deck's roadmap, and SK hynix is still deciding which product gets it first. Lee didn't name a target generation, but ruling out HBM4E leaves HBM5 as the earliest slot. The technique joins flattened copper pads and oxide surfaces at room temperature, then relies on copper's thermal expansion during a cure step to form the bond.

"This is a very simple process, but in reality it's really challenging," Lee said. "We are talking about 16 layers and 20 layers that we need to make the hybrid bonding, so it's very different from the one-layer stacking." Removing micro-bumps entirely lets core dies grow up to 24% thicker at 20-Hi, cuts thermal resistance by roughly 35% versus MR-MUF at that height, and takes bump pitch below 18 microns, per the deck, against the 30 microns where MR-MUF is today. At HBM4's bump pitch, conventional micro-bumps still work, and each time JEDEC has raised the thickness ceiling, MR-MUF has stayed viable for another generation.

iHBM

The iHBM concept embeds thermally conductive, electrically insulating blocks into the base die's die-to-die PHY region, the interface hotspot where power density peaks, for a claimed thermal resistance reduction of more than 30%.

Lee's slides benchmarked it directly against Samsung's Heat Path Block approach, which routes heat out of the stack through dedicated pillars, and Micron's base-die circuit redesign, which claims over 20% better energy efficiency. All three are vendor claims measured on different metrics, and the SK hynix and Samsung designs are both slated for HBM5, with neither expected in mass production before 2028. Because the blocks sit inside the package alongside the D2D PHY, they need optimization with the customer's design and can't be applied to generations already in design, Lee said, which makes iHBM a co-design effort. "It's a kind of good option that we can do, but this is not something that we can apply [to] the generation that we already [have] in design."

During Q&A, Tanj Bennett of SemiAnalysis argued that stacking taller dilutes the silicon's own throughput. DRAM operating at the cell level delivers on the order of 20 TB/s per square centimeter; a 20-Hi stack tops out around 4 TB/s, and HBM takes far more manufacturing capacity than equivalent DDR5 or LPDDR. "As you get to 20 high, the average speed of that memory is slower than DDR5," Bennett said. "Why is it better to be using the height of the HBM stack instead of intelligently placing cheaper memory around it?"

Lee answered that training workloads demand both bandwidth and capacity, then added that inference may split the difference, keeping the KV cache in high-bandwidth memory while offloading to LPDDR. That split already exists in products like Nvidia's Vera Rubin platform, which pools LPDDR5X with HBM4 over NVLink-C2C for exactly this purpose, and the High Bandwidth Flash spec that SK hynix co-developed with Sandisk extends the tiering idea to NAND.

"That's a kind of question that we need to also look at in the future," Lee said of the tiered approach. SK hynix holds around 70% of Nvidia's HBM orders for the Vera Rubin generation, according to reporting from January, and all of it will be stacked with MR-MUF. Which product moves off it first, Lee says, is a decision that the company hasn't made.

Full SK hynix Hot Chips 2026 presentation

Nvidia has told some of its largest customers that the prices of servers containing its AI chips will rise by more than 15% in many cases, Bloomberg reported on Saturday. The increases will take effect on Grace Blackwell and Vera Rubin systems shipping early next year, according to people familiar with the matter, who commented on communications that have not yet been made public. The size of each increase will depend on the chip generation and the memory configuration involved. Companies that build servers under contract for large data center operators, including Microsoft, Google, and Oracle, have recently notified their customers of the forthcoming increases, the people told Bloomberg.

This is another example of the so-called "RAMageddon" that's gripping the DRAM market, with contract prices having risen at record rates this year. Analysts projected that conventional DRAM contract prices would climb 58% to 63% quarter-over-quarter in Q2 2026, following a Q1 surge of 90% to 95%, as suppliers reallocated capacity toward HBM and server products. SK hynix said in October last year that it had already sold out its entire 2026 memory production capacity, and Samsung and SK hynix raised 2026 HBM3E supply prices by close to 20% before the year began.

AI systems carry enormous memory loadouts, with Nvidia's Rubin GPU shipping with up to 288GB of HBM4 per package, and the NVL72 rack-scale system combines 72 of those GPUs, putting more than 20TB of HBM in a single rack before accounting for the LPDDR attached to its Vera CPUs. With HBM production consuming roughly four times the wafer area of equivalent conventional DRAM, memory has become one of the largest line items in an AI server's bill of materials, and it's continuing to rise at a stratospheric pace.

Ironically, the supply crunch that's now inflating Nvidia's systems is the same one its demand helped to create. The three major memory makers spent this and last year shifting advanced nodes and new capacity toward HBM and high-capacity server DRAM, starving commodity markets in the process. Consumer DDR5 pricing has more than doubled since late 2025 as a result, with a mainstream 32GB DDR5-6000 kit selling for around $392 in August against $110 to $140 a year earlier, according to our RAM price tracker.

Nvidia has already passed rising costs through to consumers, raising prices on GeForce graphics cards earlier this month. The Bloomberg report indicates the same unrelenting pressure has now reached the top of the Nvidia stack, where hyperscalers as well as PC builders will be absorbing the increase. A 15% rise on rack-scale systems that sell for several million dollars each adds hundreds of thousands of dollars per rack across deployments that run to thousands of racks.

Nvidia runs a gross margin of roughly 75% non-GAAP, among the highest in the semiconductor industry, and the reported hikes indicate the company intends to pass memory cost inflation on to customers rather than absorb it, which it can more than afford to do. Meanwhile, supply of its accelerators from TSMC still can't meet demand, which limits buyers' immediate leverage.

Whether the increases push hyperscalers further toward AMD's accelerators or their own custom silicon will depend on how quickly those alternatives can absorb displaced demand, and all of them draw HBM from the same three constrained suppliers.

After posting record profits amid high memory prices, SK hynix ran into a dispute with employees over profit sharing and wage increases, which threatened to escalate into collective action by the company's union. This week, SK hynix management and the labor union reached a preliminary 2026 wage and collective bargaining agreement that significantly changes how the company's profit-sharing bonuses will be distributed, reports Maeil Business citing Yonhap. The good news is that no strikes are planned at the memory maker.

The tentative labor package reportedly calls for a 6.3% wage increase and an increase in welfare points provided by the company. In addition, under the proposed arrangement, employees will receive 40% of their performance-based profit distribution in cash, while the remaining 60% will come in the form of SK hynix shares. The proposal changes SK hynix's 2025 profit-sharing scheme, which allocated 10% of the previous year's operating profit to employee profit-sharing program, but the bonus was to be paid complete in cash: employees received 80% in cash immediately and remaining 20% over the next two years.

The union argued that stock-based bonuses expose employees to potential losses if SK hynix shares decline and could create tax complications, as income tax may be calculated using the share price when the stock is awarded. Specifically, the workers argued that performance bonuses normally paid in cash should not be converted into assets that carry investment risk. Yet, the SK hynix management and union have agreed to remove the 10% ceiling, potentially providing more money to employees, maintain the mechanism for 10 years, and pay the bonuses in cash and stock.

If SK hynix meets current market expectations and earns 25 trillion won ($17.897 billion) in operating profit this year, the profit-sharing pool would amount to 2.5 trillion won ($1.79 billion) based on the 10% formula. SK hynix reportedly has approximately 35,000 employees, so on average every employee will get 70 million won, or $50,120 ($20,048 in cash and $30,072 in stock). Yet, actual compensation will differ depending on an employee's position and individual performance assessment.

On August 4, before the fifth round of negotiations, an SK hynix union told members that if management did not present a revised proposal, it would be difficult to settle the dispute through negotiations alone and the union would have to take necessary action, which was obviously a way to threaten the management with a strike. Yet, the parties have come to terms.

The dispute comes as Samsung Electronics has faced similar labor action over compensations.

SK hynix has resumed investments in its fab in Dalian, China, which is operated by its Solidigm subsidiary, and plans to boost its output by 50% already in 2027, reports Sedaily. Coincidentally, the company is mulling listing some of Solidigm's shares on NASDAQ to raise capital, but to retain control over its North America-based subsidiary, according to The Korea Herald.

After SK hynix acquired Intel's 3D NAND and SSD business in 2021 and formed its Solidigm subsidiary shortly after, it suspended any expansions of Solidigm's capacity in China partly due to the memory market downturn in 2022 – 2023 and partly due to U.S. export controls that curb exports of advanced fab tools to China. However, as demand for solid-state storage is setting records in general and demand for Solidigm's high-capacity SSDs is exceptionally strong, SK hynix is reconsidering its capacity plans for the Dalian fab just in time for Solidigm's initial public offering.

Following a four-year pause, Solidigm has reportedly resumed investment in its Dalian facility in China this year. The company has completed construction of the second phase of the fab and is preparing to start installing production equipment as early as November, the report claims. The facility is expected to begin mass production of floating gate 3D NAND flash in the first half of 2027, if the report is accurate.

The second phase of Solidigm's fab in Dalian is reportedly designed for a wafer output capacity of around 50,000 wafer starts per month (WSPM). Combined with approximately 100,000 WSPM at the existing first phase of the facility, the new phase would boost Solidigm's NAND production capacity in Dalian by roughly 50%, to around 150,000 WSPM.

Late last year, the U.S. government granted SK hynix and Samsung annual licenses to ship semiconductor production equipment that contains technologies developed in America to their Chinese fabs through 2026, which replaced their previous open-ended Validated End User (VEU) exemptions. As a result, both companies can now upgrade their fabs in the People's Republic and even use new process technologies there.

Solidigm, for example, intends to start making floating gate 3D QLC NAND memory with over 200 active layers at its Dalian facility in the second half of 2026, which was made possible by the timely tool upgrades. The additional capacity will further increase bit output of the Dalian campus, which in turn will enable Solidigm to produce its 245TB-class SSDs due to be introduced in the coming months in decent quantities, sometimes in 2027.

Solidigm, which controls roughly a quarter of the data center-grade SSD market, is a crown jewel in SK hynix's portfolio as it makes unique products that are sold at a premium and are in high demand. Listing Solidigm on NASDAQ would enable SK hynix to gain capital (up to $7 billion, if unofficial reports are correct), but retain control over the precious asset. The money that SK hynix will raise should be roughly enough to expand Solidigm's capacity and increase output of premium data center-grade solid-state drives.

It should be noted that SK hynix did not officially confirm the Solidigm IPO plan last week, as its regulatory filing on August 5 said that Solidigm was considering various ways to improve its competitiveness, but the final decision is yet to be made.

Sandisk and SK hynix on Tuesday formally introduced the High Bandwidth Flash (HBF) specification, their jointly developed storage technology that promises to bring together the non-volatility of 3D NAND and the performance of High Bandwidth Memory (HBM), which will be handy for AI inference systems. The specification was released through the Open Compute Project (OCP), so it will be an open standard rather than a proprietary interface.

The initial specification defines HBF packages with capacities of up to 512GB using either 8-Hi or 16-Hi NAND die stacks, though these will not be standard 3D NAND stacks, but rather specialized devices with a fast interface. In fact, Sandisk once called them HBF core dies rather than 3D NAND die stacks.

Performance of HBF is divided into three bandwidth grades ranging from approximately 0.4 TB/s to 3.0 TB/s (though we are not sure whether this figure describes the full HBF subsystem or per-package bandwidth). Such a huge performance range implies that Sandisk and SK hynix expect HBF to have a multi-year roadmap featuring multiple implementations and generations of HBF. It is noteworthy that the most capable implementation of HBF (3 TB/s) is set to beat the memory bandwidth of a single HBM4 memory stack (2 TB/s), though it will be unlikely to beat HBM4 when it comes to latency.

Interestingly, SK hynix claims that HBF uses the Universal Chiplet Interconnect Express (UCIe) standard to simplify integration with heterogeneous computing platforms, whereas Sandisk claims that HBF is set to adopt the 'xPU-HBF' interface, which could be its definition of UCIe implemented by companies like Broadcom or Marvell.

In addition to capacity and performance targets, the specification establishes electrical and interface characteristics, packaging and reliability guidelines for stacked HBF devices, as well as software I/O requirements. For now, these specifications are not officially published by the OCP.

Extracting 400 GB/s of bandwidth from a single 512GB HBF package is not a trivial task. To enable such a package, Sandisk once planned to use 16 HBF core dies that feature many, many arrays that can be accessed concurrently using dedicated read/write paths. Meanwhile, it is possible to reach over 400 GB/s of bandwidth per package using a single UCIe interface that runs at up to 64 GT/s and features 64 lanes. Yet, this means that the HBF base die will be a fairly complex piece of silicon.

Sandisk and SK hynix position HBF as a new memory tier for AI inference workloads by combining near-memory bandwidth with the higher capacity and non-volatility of NAND flash. The technology is aimed at workloads that require substantially larger memory pools close to compute than HBM alone can economically provide. For example, while the maximum capacity of an HBM4 stack is 64GB, an HBF stack can provide up to 512GB. Even at a lower bandwidth, such memory can be useful for inference workloads.

Arguably the biggest question about HBF is who is going to adopt the technology? Since Sandisk and SK hynix announced plans to collaborate on defining the HBF specification in 2025, only Google and Tenstorrent have expressed interest in participating in the HBF consortium. Meanwhile, AMD, Broadcom, Intel, Nvidia, Marvell, Micron, Qualcomm, Samsung, and Western Digital have so far expressed no interest in HBF.

SK hynix reported second-quarter revenue of 79.32 trillion won and operating profit of 60.54 trillion won on Wednesday, the latter up 557% year over year at a record 76% operating margin, and used the same Seoul earnings call to lift its 2026 capital spending guidance to the high 40 trillion won range as AI server demand keeps outrunning what the company can produce. Third-quarter DRAM bit shipments are guided up around 10% sequentially, following a quarter in which DRAM average selling prices rose roughly 30%, and NAND prices rose in the mid-50% range.

SK priced 177.9 million American depositary receipts at $149 each earlier this month, raising $26.51 billion in the largest share sale by a non-U.S. company on record, with the SEC filing earmarking proceeds for Korean manufacturing facilities and equipment, including EUV scanners.

Wednesday's capex number is roughly the same size and funds an accelerated mass production schedule at the M15X fab in Cheongju, the Yongin Phase 1 cleanroom that opens in early 2027, and the previously announced P&T7 advanced packaging plant and M17 NAND base, which SK hynix said will be built in phases according to customer demand. Cash and short-term investments hit 88 trillion won at the quarter's end, up 33.6 trillion won in three months, against interest-bearing debt of 18.6 trillion won and a debt-to-equity ratio of 7%.

CEO Kwak Noh-jung called 2027 the worst year of the shortage on the day of the Nasdaq listing and put the end of the crunch beyond 2030. Full-year DRAM demand is growing at a mid-20% rate by the company's own estimate, against bit shipments guided up around 10% next quarter. None of the capacity now being funded will produce wafers before 2027.

Operating profit landed below the 64.1 trillion won that brokerages surveyed by Yonhap Infomax had modeled. Executives attributed the softer blended DRAM ASP to product mix and to high-value shipments pushed into the second half, and said the gap should close as HBM4 and 1c-node conventional DRAM ramp up. HBM4 entered mass production during the quarter, and HBM4E samples have shipped, with volume production targeted for 2027.

Triggered by global selloffs, SK hynix closed down around 10% in Seoul on Wednesday, and Samsung Electronics fell 5%, with the KOSPI ending the session 6% lower and below 6,000 for the first time since April 14. The index touched 5,262 at one point, down almost 13%, taking its five-session decline to 17% and cutting a year-to-date gain that had reached 116% in June to 34%. Over the past month, SK hynix has lost 47% of its value and Samsung 37%. The KOSPI fell 10.84% on Tuesday and triggered a marketwide circuit breaker after SK hynix's American depositary receipts dropped below the $149 price at which they listed on Nasdaq on July 10.

Weaker shareholder-return expectations compounded the earnings miss, with SK hynix telling analysts only that additional returns remain under evaluation and would be disclosed within the year. Josh Gilbert, eToro's lead analyst for Asia-Pacific and the Middle East, told Bloomberg that "expectations had simply moved ahead of what even another record quarter could deliver."

CXMT closed its Shanghai debut up 466% on Monday after raising 57.92 billion yuan for DRAM wafer lines, and a report last week put China at low-volume production of domestic immersion DUV scanners running to around five units this year. TrendForce still has conventional DRAM contract prices rising 13% to 18% in the third quarter, with NAND up 10% to 15%.

One of the common misconceptions in today's memory market is that once memory modules based on chips from CXMT enter the consumer market, there will be cheaper alternatives to memory sticks running DRAM from the Big Three. While availability of CXMT-powered modules certainly impacts average selling prices, these products are not cheaper than those based on ICs from Micron, Samsung, and SK hynix even in China, as noticed by @harukaze5719.

A 64GB DDR5-5600 RDIMM based on memory from Samsung or SK hynix costs 18,595 CNY ($2,745) at JD.com, whereas a module featuring the same capacity and specification, but using DRAMs from CXMT is priced at 18,999 CNY ($2,805), according to observations by @harukaze5719. It is noteworthy that a Samsung 64GB DDR5-5600 RDIMM made by Samsung and sold by Samsung costs $2,425 at Amazon.com in the U.S.

While the $60 difference seems significant, it is really just 2.2%, which can be considered negligible at these sky-high prices. Nonetheless, many expect CXMT-based memory modules to be cheaper than those carrying chips from Micron, Samsung, or SK hynix, so observing that they are even a bit more expensive than offerings with ICs from renowned manufacturers may be a bit surprising.

Indeed, because CXMT produces memory chips using an outdated fabrication technology, its DRAM ICs consume more power than those made using the latest manufacturing processes, have lower performance potential, and mediocre overclockability. Furthermore, the Chinese government heavily subsidizes both ChangXin Memory Technologies and Yangtze Memory Technologies (YMTC), which enables both to sell their memory at lower prices although their actual costs may be higher compared to those of the Big Three.

As a result, it is reasonable to expect CXMT to charge less for its chips compared to chips from renowned producers. Truth to be told, we do not know CXMT's quotes, they may be as high as those from other manufacturers and the only reason why module producers buy them is that they are the only chips available. Furthermore, companies tend to price products based on what the market will bear, not strictly on production cost or their characteristics. In fact, as everyone is capacity constrained these days, there is little incentive for CXMT to price its DRAMs significantly below those from renowned makers. However, while CXMT may indeed charge less for chips (e.g., because the Chinese government issues an appropriate directive), this lowers costs for module makers, but has a limited effect on retail prices of actual DIMMs or RDIMMs.

Whether potential savings reach end customers depends on market competition, supply-demand conditions, and the pricing strategies of module makers, distributors, and retailers. Furthermore, when prominent companies like Apple, Dell, or Corsair use a memory chip SKU, this one must pass rigorous validation processes and is usually tested in-house, or by contract manufacturers, which adds to costs and somewhat erases the price difference between suppliers.

As a result, CXMT memory chips may make the lives of hardware makers easier, but are not expected to impact the retail prices you pay.

Samsung and SK Hynix, South Korean memory giants, are set to announce major deals involving “very large sums” with leading U.S. tech companies, according to a July 24 Bloomberg report, citing comments from the country's presidential policy chief Kim Yong-beom. According to the report, Kim did not disclose the financial details of the deal but said the announcements would likely cover strategic partnerships, memorandums of understanding, and long-term supply deals on memory chips.

The deals are set to be announced during South Korean President Lee Jae Myung’s visit to Silicon Valley for the high-profile San Francisco AI submit — beginning today, Friday July 24 — which is bringing together industry leaders, such as Samsung Chief Lee Jae-yong, SK groups chairman Chey Tae-won, Nvidia CEO Jensen Huang, as well as the CEOs of Open AI, Anthropic, and Broadcom among others.

South Korea announced an $880 billion investment plan last month — backed by SK Hynix, Naver, and Samsung — aimed at strengthening the country's AI leadership through aggressive chip production expansions, data center buildouts, and physical AI. Kim said the South Korean President’s visit and involvement in the summit will serve as a catalyst to seal several long-running negotiations between the country's top tech entities and their U.S. counterparts, while also turning a significant portion of last month's planned investment into concrete projects.

The president is set to hold separate meetings with Huang, OpenAI's Sam Altman, Anthropic’s Dario Amodei and Broadcom Inc.'s Hock Tan, all U.S. companies. The U.S. has also urged Samsung and SK Hynix to expand their chip production in the country, but Kim stated that there had been no formal requests from Washington. According to Kim, much of South Korea's domestic expansion is driven by strong demand from U.S. companies, which accounted for 80% – 90% of underlying orders.

The head of the SK Group, which owns SK hynix, said in a press briefing that memory semiconductor prices are “abnormally high,” and that the industry must take steps to increase supply and help lower prices. The Chosun Daily writes that SK Group Chairman Chey Tae-won delivered this statement during a press briefing at an industry forum, where he also noted that the group is looking at building a memory chip plant in the U.S. to increase production.

“Memory prices are currently at an abnormally high level. While AI companies can absorb increased costs through investments, PC and smartphone manufacturers have no choice but to pass rising semiconductor costs onto product prices,” Chey told the media. “Since most customers for these products are individuals, there are limits to how much prices can be raised. To prevent 'chipflation'—where rising chip prices drive up finished product costs—supply must be expanded.”

Aside from expanding supply and easing memory prices for consumer products, extremely high memory prices brought about by limited supply could negatively impact the big three companies. That’s because the high margins could lead to the entry of new players or give smaller manufacturers the opportunity to grow their presence and challenge the established firms. We’re already seeing this, as some Chinese brands have ditched them for domestically produced CXMT and YMTC chips. While this could be driven by Beijing, even major multinational brands like Corsair and Lenovo have started sourcing from these companies just to get chips. Even Apple is asking permission from Washington to buy memory chips from CXMT. Aside from that, he also cited Elon Musk’s interest in building his own fab as a potential threat to existing memory semiconductor companies.

This isn’t a problem at the moment as there is more than enough demand to go around for incumbent memory and storage chip manufacturers and new entrants. In fact, memory companies can use this as a defense against price-fixing lawsuits, with the massive AI demand and the higher margins it offers standing as a plausible reason why memory chip companies focused on HBM production and reduced DRAM output. But before the AI boom, the memory industry was actually suffering from one of the worst memory downturns to hit the industry for over a decade. So, if and when the memory shortage is over and the memory industry resumes its boom-and-bust cycle, more manufacturers jockeying to find customers in a tight market would make it that much harder for these companies to survive and thrive.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

SK hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based in-memory computing (IMC) system-on-chip (SoC) for AI edge devices. The device is designed to accelerate neural network inference in lightweight AI models while consuming a fraction of the power that higher-end GPUs or NPUs would. To a large degree, the SoC is a proof-of-concept chip, as its performance would peak at around 2.54 TOPS in a theoretical best-case scenario, which is 16X below Microsoft's Copilot+ requirements.

A DWC-optimized IMC architecture

Memristor-based in-memory computing (IMC) accelerates neural networks by performing analog computations directly inside memory arrays, which reduces data movement and power consumption. However, depthwise convolution (DWC) — a core operation in lightweight networks such as MobileNet — performs independent per-channel filtering with limited data reuse and therefore maps poorly onto conventional crossbar arrays. To address this limitation, researchers from SK hynix, TetraMem, and USC developed an SoC that features both conventional IMC crossbars and a memristor-based IMC architecture specifically optimized for DWC.

The jointly developed SoC is based on an embedded RISC-V processor that schedules workloads and features 10 neural processing units (NPUs). One NPU out of 10 is dedicated to depthwise convolution, while the remaining nine execute pointwise and dense operations. Nine out of 10 NPU include a 256 × 256 memristor crossbar that performs the analog vector-matrix multiplication (VMM), 256 8-bit DACs that convert digital activations into analog voltages, 256 8-bit ADCs that convert the analog outputs back into digital values, and additional peripheral circuitry for reading, writing, programming, and controlling the crossbar.

The DWC-optimized NPU replaces its conventional array with eight specialized 252 × 28 zig-zag crossbar blocks, but retains DACs and ADCs. SK hynix developed and fabricated the memristor devices and integrated the resistive switching cells on top of the 65 nm CMOS circuitry using its back-end process.

That DWC-optimized NPU is the key feature of the whole SoC. To accelerate depthwise convolution, TetraMem replaced the straight selection lines used in conventional 1T1R crossbars with a zig-zag topology. As a result, the NPU contains eight 252 × 28 crossbar blocks whose diagonal selection lines activate 252 memory cells across 28 columns, which enables 28 independent 3 × 3 convolutions to run in parallel while using 100% of the array for weight storage. The remaining nine NPUs retain conventional 1T1R crossbars for 1×1 pointwise and dense layers and preserve the throughput and energy efficiency of traditional in-memory computing.

Great efficiency, low performance overall

To demonstrate the architecture, the researchers deployed a customized MobileNetV1Small neural network for the Visual Wake Words benchmark. The network contains approximately 36,000 parameters; all depthwise layers were mapped to the dedicated NPU, and pointwise layers were mapped to the remaining NPUs.

Because the memristor-based IMC hardware natively performs unsigned analog vector-matrix multiplication, inputs and weights are quantized to unsigned 8-bit values before execution. Since each memristor device can be programmed with only slightly more than 2 bits of effective precision, the design uses a two-subarray compensation technique that boosts effective weight precision to roughly 4 bits.

Conceptually, the approach is somewhat analogous to Nvidia's NVFP4 philosophy, in that both seek to achieve higher effective precision from low-precision hardware. However, the implementations are fundamentally different: NVFP4 relies on a digital floating-point representation and scaling factors, whereas the memristor SoC improves precision by compensating for analog programming errors using two programmed subarrays.

When it comes to accuracy, the SoC achieved an end-to-end inference accuracy of 80.36%, which matches the corresponding 4-bit software model. As for performance, the SoC delivers a peak throughput of 0.254 TOPS per NPU and reaches an energy efficiency of 21.3 TOPS/W at 100 MHz and 11.9 TOPS/W at 400 MHz. According to the authors, this compares favorably with published SRAM-based compute-in-memory accelerators despite being manufactured on an older 65 nm process. The SoC also exceeds Nvidia's A100 INT8 energy efficiency by an order of magnitude, the joint paper claims. Yet, these claims are largely unsubstantiated.

First up, the MobileNet demonstration does not even use all 10 NPUs. It uses one dedicated DWC NPU, five standard NPUs for pointwise layers, and leaves four standard NPUs idle. The demonstration thereby does not reveal total SoC throughput (TOPS), sustained throughput running a real network, and throughput with all 10 NPUs simultaneously saturated. In fact, the paper does not even reveal whether all 10 NPUs can be used at the same time. To that end, the 2.54 TOPS figure we mentioned earlier in the story is highly theoretical.

Validated approach

SK hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based IMC SoC featuring a novel depthwise convolution accelerator that improves crossbar utilization for lightweight AI workloads. The partners have managed to fabricate it using an outdated 65nm process technology and make it work, achieving a 21.3 TOPS/W energy efficiency and inference accuracy comparable to a 4-bit software model despite the fact that memristors can be programmed with a circa 2-bit accuracy. While the architecture validates that the approach works, the paper does not disclose the full performance of the SoC, and it is not clear whether the chip's 10 NPUs can be saturated at all.

SK hynix has completed the largest-ever foreign company IPO in U.S. history, raising $26.5 billion in its Nasdaq debut today, July 10. The South Korean memory giant sold 177.9 million American depositary receipts (ADRs) — a U.S.-listed stand-in for a foreign share — at $149 apiece, each representing a tenth of a Seoul-listed share. The offering was more than seven times oversubscribed and drew demand from more than 500 investment firms, according to Financial Times. Temporary Nasdaq trading is underway under the ticker SKHYV before regular-way trading begins as SKHY on Monday, July 13.

The offering was led by Bank of America, Citigroup, Goldman Sachs, and JPMorgan, with nine additional firms rounding out a 13-bank syndicate. Anchor demand came from heavyweight institutions including Baillie Gifford, Coatue Management, and Situational Awareness Partners, which together signaled interest in as much as $7 billion of stock, according to people familiar with the matter cited by Financial Times.

SK hynix is the world's leading maker of high-bandwidth memory (HBM), the vertically stacked DRAM that has become critical infrastructure for AI accelerators. The company has said it will steer the proceeds toward boosting its AI-memory manufacturing capacity. Confirmed build-outs include the first-phase fab at the massive Yongin semiconductor cluster, a new P&T7 advanced-packaging line in Cheongju, and EUV lithography equipment slated for delivery by the end of next year. Separately, SK hynix is constructing its first U.S. production site, a $4 billion advanced-packaging plant in West Lafayette, Indiana, targeted for completion around 2028. The facility is eligible for up to $458 million in CHIPS Act grants and up to $570 million in federal loans.

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SK hynix is seeing sensational growth thanks to the ongoing AI boom. The company is reportedly on track to post over 200 trillion won ($133 billion) in operating profit this year, a record-breaking figure that would see SK hynix employees earn around $400,000 each in bonuses. The company’s Seoul-listed stock is up roughly 220% year-to-date and has climbed more than sixfold over the past year.

In late June, SK hynix briefly surpassed Samsung as South Korea's most valuable company, closing at around 2,080 trillion won (about $1.35 trillion), a meteoric rise for a company that almost declared bankruptcy in 2001 and, more recently, recorded an annual operating loss of 7.73 trillion won in 2023. That rise doesn't seem like it will be slowing down any time soon. SK hynix has said its entire 2026 output of HBM, DRAM, and NAND is already sold out, with the crunch expected to extend into 2027.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

South Korean President Lee Jae-myung announced a ₩1,350 trillion (roughly $880 billion) 10-year public-private plan for semiconductors, AI data centers, and robotics on June 29. At the televised address in Seoul, he was flanked by Samsung Executive Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won.

The ₩1,350 trillion total combines a $520 billion semiconductor program with AI data center and robotics spending, most of it corporate capital expenditure rather than direct state funding. Samsung's Device Solutions division booked ₩53.7 trillion in first-quarter operating profit and expects 2026 to out-earn its entire prior semiconductor history. Samsung and SK hynix have pulled fab completion dates forward by as much as 12 years, while the transmission lines and water pipelines that those fabs depend on remain years behind.

Gigawatts of power deficit

The Yongin Semiconductor National Industrial Complex, the Samsung and SK hynix megacluster in Gyeonggi Province, is estimated to require 15 to 16 GW at full operation, close to 25% of total Seoul-metropolitan power demand, against local supply of about 1.9 GW, according to a National Assembly Research Service report. As of a January briefing, however, about 6 GW of the roughly 15 GW the complex needs had no finalized supply plan, with Samsung reportedly needing 9 GW (6 GW secured) and SK hynix 6 GW (3 GW secured).

Power in South Korea is generated on the coasts, from nuclear and liquefied natural gas (LNG) on the east coast and renewables in the southwestern Honam region, while the fabs sit inland, near Seoul. Closing that distance falls to state utility KEPCO, which is pursuing a ₩37 trillion, roughly 1,153-km 345 kV network to move east-coast and Honam power to Yongin, targeted for 2036. KEPCO's track record on long-distance lines is problematic, though; its losses from delays on the Bukdangjin-Sintangjeong line reached ₩1.17 trillion ($810 million), and that single project took 22 years to complete, with site selection alone running past a decade.

The east-coast link that's supposed to carry about 8 GW toward the capital region has its own history of local opposition, too. The Donghaean-Dongseoul high-voltage direct current line, a 280-km run from Uljin to Hanam requiring 436 towers, has faced repeated delays, and Hanam's 2024 rejection of a KEPCO substation expansion threatened the plan outright. Meanwhile, SK hynix pulled the completion of its fourth Yongin fab forward by 12 years, from 2045 to 2033, as announced in the recent $712.5 billion SK hynix commitment, meaning fabs are arriving faster than the power lines that feed them.

KEPCO and the government plan six LNG plants inside the Yongin complex, starting at about 3 GW and scaling toward 10 GW, to bridge the supply gap until the transmission network is finished. Both Samsung and SK hynix hold RE100 commitments to reach 100% renewable electricity by 2050, and the ruling Democratic Party's own carbon-neutrality committee has demanded the LNG plan be cancelled.

Water shortages

Aside from power, a large memory fab consumes upwards of 100,000 tons of water per day, and the Yongin national complex is projected to need around 800,000 tons per day once fully built. The plan to supply this runs in phases: roughly 200,000 tons per day from about 2031, drawn from Paldang Dam surplus and treated wastewater, followed by new intake facilities and pipelines to reach 600,000 tons per day by 2034. However, SK hynix's accelerated fourth fab is now due in 2033, a year before the integrated pipeline that's being built to serve it.

Local water disputes have already delayed the buildout, with objections from Yeoju City and Hanam City stalling pipeline permits, and one groundbreaking was cancelled outright. The friction is worse for the new southwestern cluster near Gwangju, where water may prove harder to secure than power, because the Yeongsan and Seomjin river basins hold only about half the water of the Han basin that supplies Yongin. Meanwhile, existing Seomjin and Juam dam supply contracts are already fully allocated, and the four planned southwestern fabs are estimated to need around 430,000 m³ per day of industrial water. Government projections put the Yeongsan basin at an annual shortfall of roughly 219 million m³ by 2030, before any of the fabs draw a single drop.

Financed by the memory boom

Samsung reported preliminary second-quarter 2026 operating profit of ₩89.4 trillion ($58.4 billion) on ₩171 trillion in revenue on July 7, a roughly 19-fold year-on-year jump and a record for any tech company. Its Device Solutions chip division booked ₩53.7 trillion of the company's ₩57.2 trillion first-quarter operating profit, and DS president Kim Yong-kwan told a July 3 town hall that 2026 chip profit will exceed the cumulative total the division has earned across roughly 40 years in the business. SK hynix, meanwhile, posted a record ₩47.21 trillion operating profit for 2025, overtook Samsung as South Korea's most valuable listed company in June, and filed to raise about $29 billion in a Nasdaq listing whose proceeds are earmarked for Yongin, Cheongju packaging, and EUV tools.

Those numbers rest on contract prices that have run sharply higher through 2026, with commodity DRAM up around 90% in the first quarter and 50% to 60% in the second, as memory makers tilted wafer capacity toward HBM. The same dynamic underpins the government's confidence and its exposure. Bank of America has argued that fears of a memory-cycle peak are premature, noting the industrial cluster won't produce meaningful output until 2033 at the earliest. Morgan Stanley cautioned — also on July 7 — that the memory industry is nearing a peak in its rate of change, while stressing that this doesn't indicate a downturn. A plan financed by a price surge inherits the risk that the surge doesn't last until the fabs it funds come online.

The plan is ultimately the flagship of a president who took office nine months ago, in a country that removed and jailed his predecessor. Yoon Suk Yeol declared martial law in December 2024, was impeached within days, and was removed by the Constitutional Court the following April. A snap election last June brought Lee Jae-myung to office, and in February this year, Yoon was sentenced to life in prison for insurrection. Industrial policy has held across the turnover, with the Semiconductor Special Act passing the National Assembly with bipartisan support in May, but its dedicated ₩2 trillion account doesn't begin operating until 2027.

South Korea caps the workweek at 52 hours, and a proposed exemption for chip R&D staff was cut from the Semiconductor Special Act before passage. Industry and the conservative opposition backed the carve-out, citing TSMC's three-shift operations and longer hours at Chinese competitors, while the ruling party and a coalition of labor organizations opposed it as corporate favoritism.

A stopgap now lets firms run R&D staff up to 64 hours per week for limited periods with labor-ministry approval. Samsung's foundry holds about 7% of the contract chipmaking market against TSMC's 72%, and SK hynix supplies most of the HBM feeding Nvidia's AI accelerators, so the plan directs its capital toward memory and leaves Korea's weaker logic position largely untouched. Lee's single five-year term ends in 2030, three years before the plan's fabs are due to reach meaningful output.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

South Korean President Lee Jae Myung on Monday, June 29, announced an 800 trillion won ($520 billion) public-private investment plan alongside Samsung Electronics and SK Hynix to expand the country's chipmaking capacity, a move the government framed as essential to keeping South Korea competitive in the global artificial intelligence race. Lee unveiled the plan in a televised state address at his office in Seoul, flanked by Samsung Electronics Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won, the leaders of the world's two largest memory chipmakers.

"Right now is truly a decisive moment, as the landscape of the global economy is being reshaped," Lee said in televised remarks. "Major countries, including the U.S. and China, are engaged in all-out competition with massive stakes." He added that only through cooperation between the private and public sectors could South Korea hope to triumph. Industry Minister Kim Jung-kwan said the plan would let the country rapidly expand production by sharply shortening the timeline from licensing to construction.

The centerpiece of the partnership is the construction of four production facilities, with Samsung and SK Hynix each building two. According to the government, the new plants will be built in the southwestern part of the country, near the city of Gwangju, a mostly rural area far from the existing semiconductor base south of Seoul, where both companies operate major clusters. Samsung will also build packaging facilities for high-bandwidth memory (HBM) chips in Chungcheong as demand for the advanced components soars.

"HBM, which is indispensable for the training and inference of AI models, requires cutting-edge technology for stacking semiconductor chips," the Samsung chairman said. "We will focus our investment on HBM fabs, which require main-fab-level processes, alongside existing semiconductor back-end fabs in the Chungcheong region, including Cheonan and Onyang."

One detail the government did not provide was the split between public and private money, as the project is a combined public-private commitment rather than a government spending program. While it is not immediately clear how much of the 800 trillion won would come from the state versus the two chipmakers, the disclosed line items are comparatively modest.

Industry Minister Kim Jung-kwan said the government and industry would jointly invest more than 30 trillion won over 15 years across the semiconductor value chain, while President Lee said Gwangju and South Jeolla province would contribute a further 5 trillion to 20 trillion won. Kim put another 81 trillion won toward the Chungcheong packaging hub, though he did not say how much of that is public.

The balance of the headline number is widely expected to be company capital expenditure, with the state's role concentrated in subsidies, faster permitting, and infrastructure. Kim said the government would streamline approvals and bring fab construction forward by up to 12 years, from the mid-2040s to the mid-2030s.

The plan also absorbs and accelerates projects already underway. The government said it would help Samsung and SK Hynix speed up construction of their existing capital-region clusters, with SK Group pulling forward the ramp of its Yongin memory site from 2045 to 2033, part of a stated goal to double the country's memory output within five years. SK Hynix supplies the bulk of the HBM that Nvidia depends on for its AI accelerators, the very strain this expansion is meant to relieve. While semiconductors are the focus of the investment, with the priority being a decisive lead in memory chips, the companies will also work on AI robots, physical AI, and AI data centers.

The investment partnership appears to be the latest piece of a broader strategy. SK Hynix had already committed $15 billion to new semiconductor facilities in February, a figure that now reads as an early piece of the larger national framework. Earlier iterations of the country's cluster plan had pegged long-term investment at around $471 billion, stretching to 2047, so the new figure represents a substantial expansion as AI demand projections have climbed. The fabs are targeted for completion in the mid-2030s.

The announcement caps an extraordinary stretch for both firms. SK Hynix overtook Samsung in June to become South Korea's most valuable listed company for the first time in more than 25 years, lifted by its commanding lead in HBM, while Samsung's chip division alone booked 53.7 trillion won in first-quarter operating profit as AI-driven memory shortages are expected to strain the companies' capacity past 2027.

The scale of the investments also invites inevitable comparison. At roughly $520 billion, South Korea’s plan dwarfs the United States' CHIPS Act, which provided about $52 billion in direct subsidies, by a factor of ten. Although the comparison is imperfect, since the U.S. figure is a government subsidy while the Korean number appears to be mostly private investment that the state is coordinating.

The strategic logic is the same on both sides of the Pacific: secure domestic capacity for the chips that underpin AI, at a moment when the U.S., China, Japan and the EU are all pursuing their own semiconductor industrial strategies. For Seoul, the specific prize is memory, the segment where its two companies already hold a commanding global position, with the goal being to extend that lead rather than merely defend it.

Samsung, SK hynix, and Micron were sued on June 25th in the U.S. District Court for the Northern District of California, where 17 plaintiffs accuse the three memory makers of illegally coordinating to restrict DRAM supply and inflate prices that the complaint says have risen roughly 700% over four years. The class action, filed as Garciaguirre v. Samsung Electronics and assigned to Judge Noel Wise, invokes Section 1 of the Sherman Act and targets companies that together hold around 90% of the global DRAM market. Samsung and SK hynix have pleaded guilty to criminal DRAM price fixing once before, with the latter paying a $185 million fine in April 2005.

The complaint argues that the three companies used a coordinated shift toward high-bandwidth memory (HBM), the stacked DRAM that feeds AI accelerators, as a cover to curtail production of older DDR3 and DDR4 modules. That contraction in commodity DRAM, the plaintiffs argue, pushed prices to record highs while no rival could step in: building a new DRAM fab costs tens of billions and takes years, leaving the incumbents free to cut output without fear of being undercut.

The named plaintiffs include 14 individuals and three small PC businesses, among them Troy's Computers and Florida repair outfit My Florida PC, and they cite Apple's recent iPad and Mac price increases as evidence of the squeeze. They’re seeking class status, an injunction, and treble damages as a result.

However, this case revisits a precedent that was already established in the same courthouse. A 2018 class action brought by law firm Hagens Berman made similar claims about parallel production cuts, and the district court dismissed it in 2020. The Ninth Circuit upheld that dismissal in 2022, ruling the trio's conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by an illegal agreement.

It was held at the time that the plaintiffs’ eight “plus factors” didn’t clear Section 1’s threshold, which demands evidence of an actual agreement rather than the conscious parallelism common in a three-supplier market. The new complaint leans on the pivot to HBM as the additional evidence that this earlier lawsuit lacked.

The three memory makers have publicly stated they’re operating independently while redirecting capacity to HBM, and senior executives have warned the shortage could run for years. Investment bank Jefferies expects DRAM prices to rise another 40% to 50% in the third quarter and a further 30% to 40% in the fourth, with no meaningful relief before 2028. The allegations remain unproven, and the defendants have not yet responded in court.

Solidigm is arguably one of the most mysterious storage companies in the industry today. The company is a wholly owned subsidiary of SK hynix, yet unlike its parent company, which produces charge-trap flash memory, it uses floating-gate 3D NAND memory that it develops and manufactures internally at a dedicated fab in Dalian, China.

Solidigm originates from Intel's Non-Volatile Memory Solutions Group (NSG), the company's NAND and SSD business unit, which used to have a unique technology strategy that differed from that of other flash and drive producers. To that end, it is not surprising that Solidigm also has a unique positioning as it only offers data center drives, most of which are based on floating-gate memory and proprietary in-house designed controllers. Furthermore, Solidigm is a fully vertically integrated company.

At Computex 2026, we sat down with Avi Shetty, who is vice president of AI ecosystem, Solutions & Market Enablement at Solidigm. Before his current position at Solidigm, he spent 14.5 years at Intel's storage division, so he has deep knowledge both about technology and the market. During our conversation, we discussed how Solidigm keeps evolving, including floating-gate NAND memory, advanced packaging technologies, next-generation SSDs, liquid-cooled SSDs, and more.

Anton Shilov: Could you introduce yourself to our readers and describe what do you do at Solidigm?

Avi Shetty: My name is Avi Shetty. I work at Solidigm, where I help lead AI solutions and ecosystem initiatives. My team works with global platform providers, software ISVs, and ODMs to ensure Solidigm solutions are validated, benchmarked, and included in reference designs at both the device and cluster levels, enabling customers to fully utilize our products.

A part of SK hynix that acts independently

Anton Shilov: You were previously a part of Intel. How is the integration going? Are you now fully integrated part of SK hynix, or do you operate independently?

Avi Shetty: Let me provide some background. While Solidigm was established in December 2021, our history goes back decades. Many of us came from Intel's Non-Volatile Memory Solutions Group (NSG), which developed Intel’s NAND SSDs for both client and data center markets.

In 2021, SK hynix acquired Intel’s NAND and SSD business and established Solidigm. Since December 2021, we have operated as a wholly owned U.S. subsidiary of SK hynix, headquartered in Rancho Cordova, California.

Anton Shilov: So, you are part of SK hynix, but still maintain a degree of independence?

Avi Shetty: Absolutely. We operate as an independent subsidiary of SK hynix. Our strategy is focused entirely on enterprise SSDs. Every bit of [floating gate] NAND [at our fab in Dalian, China] we produce goes into enterprise storage solutions.

This is one of the ways we differentiate ourselves from competitors such as Samsung and Micron, which also serve mobile and client markets. We made a deliberate decision to focus exclusively on enterprise storage and AI.

We are also fully vertically integrated. We manufacture our own NAND, develop our own controllers, write our own firmware, and design our own SSDs. While we work with manufacturing partners to build products, we control the entire technology stack.

I also believe we are the only company with access to two different NAND architectures. Through SK hynix we have access to charge trap flash (CTF) technology, and we continue to develop floating gate NAND technology for our high-density QLC SSD products.

Anton Shilov: What is Solidigm's current share of the enterprise SSD market?

Avi Shetty: Approximately 24%. That is enterprise SSDs only. We do not participate in any other NAND markets. As of the first quarter of 2025, plus or minus a few percentage points, our measured enterprise SSD market share is approximately 24%. We evaluate market-share data quarterly and semiannually, and that is the latest figure we’ve publicly discussed.

Anton Shilov: How much of your business today is concentrated in high-capacity SSDs versus higher-performance products?

Avi Shetty: High-density SSDs now represent a significant portion of our business. Because Solidigm is privately held, we do not publicly disclose that breakdown. We report our financial metrics through our parent company, SK hynix.

What I can tell you is that both our 61TB-class and 122TB-class products became customer favorites almost immediately after launch. Demand for high-density storage has been extremely strong.

Anton Shilov: I assume you also work directly with hyperscalers?

Avi Shetty: We work with a broad range of customers globally. That includes U.S. cloud service providers, Chinese cloud service providers, OEMs around the world, NeoCloud providers, software ISVs, and channel partners. We maintain customer support, engineering, and sales organizations globally. Our business spans the Americas, EMEA, China, and the rest of Asia-Pacific.

Anton Shilov: Which customer segment represents the largest opportunity for growth right now? Traditional cloud providers or something else?

Avi Shetty: We intentionally maintain a diversified customer base.

What is interesting is how quickly new segments emerge. For example, the NeoCloud market has existed for some time, but AI-focused infrastructure providers such as CoreWeave, Lambda, Crusoe, and Nebius have become much more important over the last two years.

Before the AI boom, these companies represented only a small portion of demand. Today, they are becoming a meaningful part of the market.

As AI infrastructure continues to expand, Solidigm is adapting both its customer strategy and product portfolio to support these emerging deployments while continuing to serve our traditional customers.

Floating gate NAND in 2026

CTF NAND used by major memory makers has approached 276 - 286 active layers, whereas Solidigm's floating gate flash is still at 192 layers, meaning that the company is somewhat behind some of its rivals in terms of active layers as of mid-2026. It is set to catch up with its next generation that will have over 200 layers, but only in the second half of this year. However, floating gate NAND memory still has a number of advantages over CTF, particularly for applications that Solidigm targets.

Floating gate uses a conductive polysilicon island to store charge, which provides excellent cell isolation — charge stays well-contained and is less likely to spread to or interfere with neighboring cells — and this is particularly important for 3D QLC NAND with very high layer counts. In addition, Solidigm claims that floating gate gives a strong voltage threshold window and better cell isolation, which enables the company to keep scaling QLC more while maintaining good reliability.

Anton Shilov: Are you still producing floating gate NAND, and do you intend to continue?

Avi Shetty: Absolutely. We introduced our first QLC foating gate NAND product in 2018, and today we are on our fourth generation of QLC NAND.

Our flagship high-capacity product currently ships with 192-layer floating gate NAND technology and powers our 122TB SSD.

Anton Shilov: Haven't you also announced a larger drive?

Avi Shetty: We have announced a higher-capacity product and expect it to become available later this year.

Anton Shilov: The 256TB-class drive?

Avi Shetty: Correct. Approximately 245TB usable capacity.

Anton Shilov: So you are going to have a roughly 245TB SSD available this year?

Avi Shetty: Correct.

Anton Shilov: What advantages does Floating-Gate NAND provide?

Avi Shetty: Floating gate NAND gives us scalability. We have consistently been first in the industry to push storage density in standard form factors. We were the first to introduce a 30TB SSD, then a 60TB SSD, and later a 122TB SSD.

We have been shipping the 122TB drive for nearly five quarters. We launched it in the fourth quarter of 2024, and it has since become our flagship product. It is probably our most popular product of 2025.

The reason customers like the 122TB drive is efficiency. When you look at AI data centers, customers want low power consumption, scalability, and performance. While this particular product is a PCIe Gen4 solution, our roadmap continues to increase both density and bandwidth. You will see future products based on PCIe Gen5 and PCIe Gen6.

The real attraction of the 122TB SSD is scale. In a 1U server, you can install 24 of these drives and get nearly 3PB of storage in a single rack unit.

If you look at the AI data pipeline — from training to archiving — the first and last stages require massive datasets. That is where these high-capacity SSDs are being deployed today.

Now we are also seeing growing demand from inference deployments. Inference can run in core data centers or in edge and back-office environments. Those deployments require storage that can efficiently feed GPUs and support workloads such as context storage and KV cache management. High-density SSDs help provide the capacity required for those applications.

Next-generation SSDs: PCIe Gen6 drives with liquid cooling

Anton Shilov: You mentioned PCIe Gen5 and Gen6 [next-generation drives]. I assume you are referring both to next PCIe generations and future NAND generations?

Avi Shetty: Both.

We maintain separate technology and product roadmaps. Earlier, I mentioned that our current QLC NAND is our 4^th Generation technology based on 192 layers. We will continue investing in future NAND generations as well.

On the product side, we are talking about PCIe generations. We currently ship both PCIe Gen4 and PCIe Gen5 SSDs. All of our TLC products are PCIe Gen5 today, while our QLC lineup currently remains PCIe Gen4.

Future QLC products will move to PCIe Gen5, and eventually, we will introduce PCIe Gen6 SSDs as platform vendors such as AMD, Intel, and Nvidia adopt PCIe Gen6 in their systems.

Anton Shilov: You mentioned PCIe Gen6 SSDs. You have not shipped one yet, correct?

Avi Shetty: Correct. PCIe Gen6 products are part of our future roadmap.

Anton Shilov: How close are they?

Avi Shetty: We are not making product announcements at Computex, but you will hear more from us soon.

Anton Shilov: At the moment there is really only one platform that can take advantage of them anyway. Well, two, if you consider Nvidia Vera.

Avi Shetty: That is part of the equation. When we evaluate our roadmap, we consider demand, platform readiness, and overall value to customers.

For example, we have what we call a refresh philosophy. We may introduce a PCIe Gen4 refresh or a PCIe Gen5 refresh that lowers cost or improves efficiency rather than immediately moving to a new PCIe generation.

The question is whether customers gain more value from Gen6 today or from a more mature, lower-cost Gen5 product. Those are the kinds of decisions our planning teams evaluate.

What I can say is that Solidigm maintains a full roadmap covering PCIe Gen4, Gen5, and future Gen6 SSDs across all major form factors, including U.2, E1.S, E3.S, and other EDSFF variants. Our portfolio spans capacities from 2TB all the way to 122TB.

Anton Shilov: Launching an all-new product early still gives you time to validate products with platform vendors.

Avi Shetty: Absolutely. We already work closely with platform providers to validate prototypes long before products are launched. Our engineering teams participate in interoperability events and PCI-SIG workshops to ensure products are ready when platforms become available.

Anton Shilov: That is actually interesting because PCIe Gen6 interoperability workshops have been delayed multiple times. Back in 2024, people expected the ecosystem to move much faster and interoperability workshops to start in 2024, with the list of compatible products emerging in 2025.

Avi Shetty: That is true. A lot depends on platform readiness and ecosystem scaling. PCIe Gen6 by itself is not enough. This is my personal opinion, but to fully benefit from Gen6 storage performance, the industry must also address cooling. That is one reason we invested heavily in liquid-cooled storage.

Last year, we introduced what we believe was the world's first liquid-cooled storage solution for Nvidia environments. It used E1.S PCIe Gen5 SSDs with direct liquid cooling. Historically, liquid cooling was focused on CPUs and GPUs. We extended it to storage by allowing coolant to flow through a cold plate attached to the SSD. The cold plate removes heat directly from the drive. To fully exploit PCIe Gen6 performance, the ecosystem must develop those kinds of technologies as well.

Anton Shilov: So you believe PCIe Gen6 SSDs will require liquid cooling?

Avi Shetty: At least in high-performance AI environments, particularly Nvidia-based deployments, we believe liquid cooling will be necessary.

Next-generation SSDs: PLC NAND

Anton Shilov: Will future NAND generations include both TLC and QLC? And what about PLC?

Avi Shetty: Never say never. We demonstrated PLC technology using floating gate NAND at the Flash Memory Summit several years ago. However, this business requires factory optimization and maintaining a manageable number of SKUs to maximize utilization and profitability.

That said, there absolutely will be opportunities for PLC. We have not announced any specific products or timelines, but there is active PLC development underway inside Solidigm.

Anton Shilov: That is interesting. However, PLC by itself only increases capacity by about 20% compared to QLC and at the same time requires significantly more sophisticated controllers and error correction.

Avi Shetty: That is true. However, those same concerns existed during every previous transition: from SLC to MLC, MLC to TLC, and TLC to QLC.

We were the first company to commercialize QLC NAND. Initially, many competitors questioned its value. Today, the industry increasingly recognizes the total-cost-of-ownership advantages that QLC provides, and multiple vendors now offer QLC products. I think the same process will occur with PLC.

It is also important to consider the broader market. Roughly 80% of storage capacity worldwide is still deployed on hard drives. PLC does not necessarily need to replace QLC on a one-to-one basis. Instead, it can create new opportunities where the advantages of solid-state storage — lower power consumption, higher density, smaller physical footprint, and lower total cost of ownership — become compelling.

You will likely see future solution development involving software partners that help address some of the limitations you are describing.

Anton Shilov: Do you expect retention characteristics to become a major challenge with PLC NAND?

Avi Shetty: Of course. PLC is a new technology, and retention characteristics will differ from what we see with QLC today.

The same is true across all NAND types. SLC, MLC, TLC, QLC, and eventually PLC all have different retention characteristics based on the underlying technology. The existence of those challenges does not mean we stop exploring future solutions. We will continue investing in that area.

Advanced packaging for NAND

Anton Shilov: As I mentioned, PLC only increases capacity by about 20%. Advanced packaging may ultimately have a much larger impact on SSD capacity. Could you discuss where packaging technology stands today and where it is headed?

Avi Shetty: Absolutely. Let me use our current products as an example. The 122TB SSD represents a significant packaging achievement. It is a U.2 drive with 48 NAND packages. Each package contains a 22-die stack. Each die is a 1.33Tb QLC device. Those 22-die stacks are what enable us to reach 122TB in a standard form factor.

Packaging technology remains one of our core investments. We continue developing technologies that allow us to place more dies into each package and deliver higher capacities to customers.

Anton Shilov: What about increasing the number of dies per package?

Avi Shetty: That is one of the primary ways to increase density. You can either increase die capacity or increase the number of dies per package. We intend to pursue both approaches.

Anton Shilov: How many dies per package do you think remain practical?

Avi Shetty: Today we are at 22. Future products will go beyond that, although I cannot discuss specific numbers.

Anton Shilov: What did previous generations use?

Avi Shetty: Depending on capacity requirements, previous products used 4-, 8-, or 16-die stacks. Of course, we are talking about a single NAND package in each case.

Storage-Class Memory, Optane, and Nvidia's Storage Next

Anton Shilov: What about storage-class memory?

Avi Shetty: Like Optane?

Anton Shilov: Not necessarily Optane itself, but something similar — something faster than NAND flash, yet capable of offering significantly higher density than DRAM at a lower cost.

Avi Shetty: Understood. Let me frame it from the perspective of the problem we are trying to solve. If you are asking whether Solidigm is developing a storage-class memory technology similar to Optane, then the answer today is no.

What we are focused on is addressing the requirements emerging from Nvidia's Storage Next initiative. The fundamental challenge is bandwidth. HBM is extremely fast, but it is also expensive and difficult to scale economically. As AI systems continue to grow, the industry needs additional memory and storage tiers that provide greater capacity at lower cost. That creates demand for NAND-based solutions that remain non-volatile while delivering improved latency and bandwidth characteristics.

We have not made any public announcements regarding storage-class memory technologies, but we continuously evaluate future technologies and architectural approaches.

Anton Shilov: So you are exploring concepts that could potentially bridge the gap between traditional NAND and memory?

Avi Shetty: We are evaluating a wide range of technologies that could help us continue delivering leadership products to our customers. When and if we have something to announce, we will do so publicly. At this point, however, we have nothing to disclose.

Anton Shilov: So storage-class memory is not currently a product category that Solidigm is actively pursuing?

Avi Shetty: If you are specifically referring to something similar to Optane, then no.

Optane was based on a fundamentally different technology. It was not NAND. It relied on a phase-change-memory-derived architecture and represented a completely different storage medium. We are not pursuing that type of technology today. What we are investing in is future NAND technology.

Anton Shilov: You think that future NAND technologies could eventually move closer to that space?

Avi Shetty: Exactly. Future NAND innovations could help narrow the gap between HBM, DRAM, and the next storage tier. That’s certainly one of the directions the industry is evaluating as AI systems continue to demand larger memory pools and greater bandwidth.

SK hynix filed a securities registration statement with South Korea's Financial Supervisory Service and the U.S. SEC on Wednesday to raise up to 45.45 trillion won ($29.43 billion) through an American depositary receipt listing on the Nasdaq Global Select Market scheduled for July 10th — and the company said the whole lot would go toward investments in factories and equipment.

The offering covers 17.79 million newly issued common shares and would rank among the largest ADR sales ever completed. SK hynix earmarked the proceeds for its first fab in the Yongin cluster, an advanced packaging plant in Cheongju, and chipmaking equipment that includes EUV scanners.

None of the funded projects will produce memory in time to ease the shortage that’s still driving up prices. SK hynix holds about 57% of the HBM market and 32% of global DRAM, and chairman Chey Tae-won has said repeatedly that AI demand will keep supply tight until 2030.

The filing names three target projects that SK has already committed to and is now financing via public markets. The first fab in the Yongin Semiconductor Cluster, designated Y1, carries a 31 trillion won ($21.5 billion) commitment for its initial phase and is due for completion around February 2027, with equipment installation to follow in the second quarter. The Cheongju P&T7 advanced packaging plant, a 19 trillion won ($12.9 billion) site dedicated to HBM assembly and testing, broke ground in April and should be completed at the end of 2027. EUV lithography is needed in both, and SK hynix placed a record $7.9 billion order with ASML in March covering roughly 30 scanners through 2027.

10 ADRs will represent one common share, with the final per-ADR price to be set through bookbuilding shortly before the July 10th debut, and SK hynix said the total raise could change from the 45.45 trillion won ceiling. BofA Securities, Citigroup, Goldman Sachs, and JP Morgan are managing the sale, and the regulatory review is expected to conclude by July 3rd, with the new shares registering on the Korea Exchange on July 29th.

Both the Yongin fab and the Cheongju packaging plant reach volume output in 2027, near the back end of that window. The company confirmed the ADR plan in early June alongside a pledge to double wafer capacity within five years, a timeline Chey acknowledged would do little to shorten the squeeze. DRAM contract prices have run higher through 2026 as the three memory makers tilt wafer capacity toward HBM, which consumes around three times the silicon per gigabyte of standard DDR5.

Just two days ago, SK hynix passed Samsung Electronics to become South Korea's most valuable listed company, ending a 26-year run at the top. Its Korea-listed shares rose 5.5% in after-hours trading following the disclosure.

SK hynix overtook Samsung Electronics on Monday to become South Korea's most valuable listed company, the first time Samsung has surrendered the top spot on the KOSPI index since November 2000, according to Reuters. SK hynix shares closed up 5.6% to lift its market capitalization to 2,080.4 trillion won ($1.35 trillion), edging past Samsung's 2,066.7 trillion won excluding preferred shares, after a rally of more than 340% this year built almost entirely on demand for the high-bandwidth memory it supplies to Nvidia and other AI chip buyers. The company held 61% of the global HBM market in 2025, against 17% for Samsung and 21% for Micron.

SK hynix is one of the few pure-play memory makers, while Samsung spans smartphones, displays, contract chipmaking, and home appliances, among many other markets. Investors value the focus on pure-play memory higher because HBM carries the industry's fattest margins and ties suppliers to specific AI accelerators, unlike commodity DRAM that buyers can swap between vendors.

SK hynix built its lead by continuing to invest in HBM through the 2023 downturn, when a memory price collapse pushed it to a 7.73 trillion won annual operating loss. Samsung, by contrast, reportedly hit yield and qualification delays on its HBM3E chips that slowed major Nvidia orders, the proximate reason for a 61% share against a 17% one.

Samsung's remaining stronghold is conventional DRAM, but even that margin is shrinking. Bank of America estimates put SK hynix's monthly DRAM output at roughly 589,000 wafers this year against Samsung's 691,000. SK hynix is projected to expand output by about 38% between 2025 and 2028, compared with 17.5% at Samsung, which would cut the production gap to under 10% by 2028 from around 23% in 2025. The capacity both companies are pouring into HBM is not going into the commodity chips behind the memory shortage they've warned could run past 2027, and SK hynix has pledged to double its memory wafer output within five years.

Samsung, meanwhile, disputes the ranking, telling Reuters that its market cap should include preferred shares, which would lift its value to 2,246.4 trillion won. The gap also reflects the HBM3 and HBM3E generations rather than what comes next. Nvidia CEO Jensen Huang confirmed earlier this month that Samsung, SK hynix, and Micron all passed HBM4 certification for the Vera Rubin platform, and Samsung shipped the industry's first 12-layer HBM4E samples on May 29th.

SK Group Chairman Chey Tae-won, who pushed through the original Hynix acquisition despite internal opposition, explained the strategy in a book published in January. "What I really wanted to accomplish when we acquired Hynix was to transform it from a commodity memory producer into a mainstream semiconductor company whose products are indispensable," Chey said.

The Bank of Korea has named performance bonuses at Samsung Electronics and SK hynix as a risk to the country's inflationary stability, warning in a price-stability report on June 17th that payouts worth several hundred thousand dollars per worker could push wages higher across the wider economy. The central bank found that special pay in the IT sector increased by 60.6% year over year in the first quarter, while wage growth elsewhere ran at just 2.1%, a gap wide enough that two chipmakers are now featured in national monetary policy. The bank held its benchmark rate at 2.50% in May and projects full-year inflation of 2.7%, above its 2% target.

SK hynix agreed last September to set aside 10% of its operating profit for worker bonuses, and Samsung committed 10.5% of its semiconductor operating profit after its union threatened an 18-day strike in May. These figures mean that a memory worker on a base salary of 80 million won ($52,400) stands to collect roughly 626 million won ($410,000) this year, while SK hynix staff could receive more than 700 million won ($454,851) if the company reaches 250 trillion won in annual profit. SK workers could see close to $900,000 next year on top of this year's haul.

In its price-stability report, the Bank of Korea modeled how concentrated payouts move prices. When the share of firms paying top-10% bonuses rises, consumer prices climb 0.05 percentage points roughly five months later, a lag effect that broad, even wage increases don’t produce.

Governor Shin Hyun-song has said that consumer prices should stay on a high upward path, with second-half headline inflation near 3%. The bonuses have already spilled into other areas, with labor groups citing them in next year's minimum wage talks, and card spending has risen fastest in the Gyeonggi Province districts around the two firms' fabs, where luxury sales have surged.

The payouts can of course be traced back directly to the AI-driven memory supercycle that has sent DRAM and NAND contract prices climbing through 2025 and 2026. HBM demand for AI accelerators has handed Samsung and SK hynix record operating profits, with profit-linked bonus deals converting that windfall for the companies into bags of cash for workers in the companies’ microchip divisions.

Senior South Korean policymaker Kim Yong-beom spooked markets last month when he floated the idea of a “national dividend” in a Facebook post, writing that gains from the AI infrastructure era were built on an industrial foundation the entire nation accumulated over half a century. Seoul officials later said it had no such plans, however.

Intel has appointed Seok-Hee Lee, the former chief executive of memory maker SK hynix and battery maker SK On, as executive vice president of Intel Foundry, handing the semiconductor veteran control of advanced packaging, system integration, and all back-end technology development and manufacturing. Lee reports directly to CEO Lip-Bu Tan, and his arrival comes with a structural change at the foundry: Intel is splitting advanced packaging out as a dedicated business, with Naga Chandrasekaran narrowing his focus to front-end work on the Intel 18A and 14A nodes. Longtime executive Navid Shahriari is retiring after 37 years, the company announced.

Lee spent roughly a decade at Intel earlier in his career before holding leadership roles across the Korean chip industry, including the top job at SK hynix, one of the world's two largest suppliers of high-bandwidth memory. Tan credited Lee with "deep expertise in leading complex, high-scale technology and manufacturing organizations," and said the hire would help Intel "tightly couple leading-edge logic, memory, networking, and other components" for foundry customers.

Putting a former memory chief over packaging aligns with where Intel's back-end ambitions are. HBM stacks sit alongside logic dies inside the same package on every modern AI accelerator, and it’s joining those two components together that Lee now oversees. Last month, it was reported that SK hynix was testing Intel's EMIB packaging for HBM integration, sending both companies' shares higher.

Tan named EMIB-T and HBI as the technologies Intel intends to ramp to high volume under Lee. EMIB-T adds through-silicon vias to Intel's embedded bridge for higher power delivery and HBM4-class bandwidth, and is rolling out in production fabs this year. Intel has positioned the EMIB family against TSMC's CoWoS, whose lines have been oversubscribed for more than two years, and is reportedly in talks with Google and Amazon to package their custom AI chips.

It goes without saying, then, that the stakes for the unit Lee’s inheriting are huge. Intel Foundry lost $10.3 billion on $17.8 billion of revenue in 2025, and CFO David Zinsner has said packaging revenue could exceed $1 billion at gross margins near 40%, with prepaid hyperscaler commitments reaching into the billions. Korean trade press, including the Seoul Economic Daily, has spun Lee's appointment around Intel's difficulty securing yields on its proprietary back-end processes, the kind of high-volume manufacturing problem he managed for decades in memory.

The hire follows Intel's April recruitment of Samsung foundry veteran Shawn Han. Lee resigned from SK On on May 28th, citing health reasons, according to Korean outlets, only to return to the industry three weeks later.

Wired has identified SK Telecom as the South Korean telecom company whose access to Anthropic's Claude Mythos model the White House ordered revoked over alleged ties to China, days before the Trump administration imposed the export controls that pulled Anthropic's most advanced AI models offline.

SK Telecom, South Korea's largest wireless carrier, was among roughly 150 organizations added to Anthropic's Project Glasswing in early June, the program through which Anthropic distributes Mythos for vulnerability detection. The White House asked Anthropic to revoke the carrier's access shortly after that expansion, and the company complied immediately. No export controls were threatened at that point, according to Wired.

SK Telecom’s footprint in China is minimal, generating roughly $1.9 million in Chinese revenue in 2024 and employing seven people in the country, according to its annual report. The national-security concern attaches instead to its parent, SK Group, whose affiliates hold extensive interests in Chinese semiconductors, energy, and other sectors.

Despite that relatively small footprint, the carrier has a deeper history within the country, having formed a wireless joint venture called UNISK with state-owned China Unicom in 2004. It then invested $1 billion in China Unicom convertible bonds in 2006 that converted into a roughly 6.6% stak, which was sold in 2009 for $1.3 billion. SK Telecom has kept a residual interest since then, listing a UNISK investment worth roughly $17 million in its 2025 filing with the U.S. Securities and Exchange Commission.

SK hynix belongs to the same SK Group, and it received Mythos access in the same expansion, as did Samsung. The two rank among the largest suppliers of the memory and logic silicon that underpins AI hardware, and both joined Anthropic's funding round as strategic investors.

The export controls followed a separate dispute, however, when Amazon, Anthropic's largest investor with a cumulative stake of about $13 billion, flagged a guardrail bypass in Fable 5 to the White House after researchers prompted the model to read a codebase and fix its flaws, turning it into a vulnerability-discovery tool. Amazon CEO Andy Jassy reportedly raised the findings with administration officials directly, which then led to the Commerce Department’s order on June 12 barring all foreign nationals — including immigrants inside the U.S. — from accessing Fable 5 and the underlying Mythos 5.

Rather than filter users by nationality, Anthropic disabled both models for everyone. The company said the demonstration it reviewed surfaced only a small number of previously known, minor vulnerabilities, and that banning a capability common to other frontier models would halt deployments across the industry.

About 100 cybersecurity professionals, including former Facebook security chief Alex Stamos and Luta Security's Katie Moussouris, signed an open letter arguing that while Mythos-class models are “quite good” at finding and weaponizing software flaws, they “are not uniquely good,” calling for the controls to be lifted.

Mythos 5 and Fable 5 remain offline as Anthropic and the White House continue negotiations over restoring access. Anthropic opened a Seoul office on June 17 and signed a memorandum of understanding with South Korea's Ministry of Science and ICT (Information and Communication Technology), naming SK Telecom among its local partners. SK Telecom has denied the allegations, telling a Korean newspaper that the anonymous claims in foreign media “lack verified facts,” and that it has no ties to China.

Nvidia and SK hynix have inked a multi-year collaboration agreement under which the companies will co-develop next-generation memory technologies for Nvidia's upcoming platforms, and SK hynix will supply them to Nvidia. The deal is designed to ensure that Nvidia will get the memory it needs from a prominent supplier and will guarantee that SK hynix will be able to sell its output in a predictable manner.

The key part of the agreement is indeed the co-development of advanced memory products designed for Nvidia's future platforms. Currently, Nvidia uses HBM, LPDDR5X, DDR5, and 3D NAND memory in various systems, so going forward, SK hynix will develop its new memory with Nvidia in mind. The joint press release says nothing about customization of memory for Nvidia, and while we cannot exclude such a possibility, it looks like the companies will continue to co-develop industry-standard solutions, but will ensure that they are compatible with Nvidia's processors.

In addition, the agreement is intended to address the increasingly long lead times and massive capital expenditures required for the production of advanced types of memory. The two companies will coordinate roadmaps over multiple years. Nvidia will gain greater visibility into future memory availability, while SK hynix secures a guaranteed role in Nvidia's next-generation platforms (i.e., guaranteed demand).

The initial part of the cooperation covers memory destined for NVIDIA Vera Rubin AI systems (HBM4, LPDDR5X, 3D NAND), standalone Vera processors (LPDDR5X), RTX Spark-powered personal computers (LPDDR5X, 3D NAND), and Jetson Thor robotic computing systems (LPDDR5X, 3D NAND).

The deal also extends to semiconductor research and design. SK hynix is deploying Nvidia's CUDA-X libraries to speed up complex chip development workloads, such as technology computer-aided design (TCAD) and computational lithography (CuLitho). In addition, the memory maker is adopting Nvidia PhysicsNeMo to accelerate proprietary simulation software as well as AI-driven physics models used during semiconductor development. In addition, the companies see an opportunity to expand these capabilities into general electronic design automation (EDA) and simulation ecosystems and potentially create tighter relationships within the industry.

Last but not least, SK hynix is creating digital twins of its semiconductor fabs using Nvidia Omniverse and OpenUSD technologies. These virtual facilities enable engineers to model production lines, test changes, and optimize operations before making adjustments in real fabs. The company also plans to use Nvidia's cuOpt and Metropolis platforms to improve the movement of autonomous robots and other factory equipment. In the future, SK hynix aims to connect these digital twins with existing manufacturing software and AI systems and enable them to analyze fab data, automate routine tasks, and help make production decisions.

A coalition of nine US trade associations has urged the Trump administration to take immediate action on what it describes as an emerging memory chip shortage driven by the explosive growth of AI data centers. In a June 3 letter sent to US Commerce Secretary Howard Lutnick and Treasury Secretary Scott Bessent shared with Tom's Hardware, the organizations — representing telecommunications providers, automakers, medical device manufacturers, and major retailers — warned that AI infrastructure deployments are consuming an outsized share of global memory production, creating supply constraints and price increases that could ripple across large segments of the US economy.

The coalition warned that the AI data center expansion, which has consumed an unprecedented share of global memory capacity, has led to a memory chip shortage that could lead to higher prices for consumer electronics, increased costs for broadband and telecommunications infrastructure, disruptions to automobile and medical device production, and delays affecting federal contractors attempting to fulfill government procurement obligations. The letter argues that these risks are emerging despite billions of dollars of US investment intended to strengthen domestic semiconductor supply chains.

The signatories acknowledged AI's importance but argue it shouldn't come at the expense of the rest of the economy. "While recent developments in AI offer the promise of generational technological advances and are important for US tech leadership, we must also ensure other key industries are not negatively impacted by this disruption in the marketplace," the coalition said.

The organizations are asking the administration to work directly with memory suppliers and major chip buyers to address the imbalance. Their recommendations include accelerating expansion of memory manufacturing capacity in the United States and allied nations, using trade agreements to strengthen supply-chain resilience, ensuring adequate memory supply for non-AI industries, leveraging CHIPS Act programs where possible, and reducing regulatory barriers that may slow capacity growth.

"We urge the Administration to work with memory chipmakers and chip buyers to assess steps that can be taken to address this imbalance in the memory market and protect against harm to consumers, workers, and businesses of all sizes," the letter states.

The warning arrives as memory manufacturers increasingly prioritize high-bandwidth memory (HBM), the specialized memory used in AI accelerators from companies such as Nvidia and AMD. Demand for HBM has surged over the past two years as hyperscalers race to deploy larger AI clusters, prompting memory suppliers to devote an increasing share of their production capacity to AI-oriented products.

Samsung and SK Hynix — which together with Micron control over 95% of global DRAM production — have been diverting wafer capacity toward high-margin HBM for AI accelerators, starving the commodity DRAM and NAND markets in the process. Both companies warned in April that significant shortages will continue through at least 2027. IDC, meanwhile, has already revised its 2026 PC market forecast downward by up to 9% as a direct consequence of memory scarcity and rising prices.

Industry analysts have repeatedly warned for months that AI demand is reshaping the economics of the memory market. While memory shortages have historically been cyclical, the coalition argues that AI infrastructure spending is creating a structural shift large enough to affect industries far removed from data centers. The letter marks the first coordinated, multi-industry push for federal intervention. Whether the administration will respond — and how — remains to be seen.

South Korean media has noted a surge in spending on luxury goods following big bonus payouts to semiconductor workers. For example, the Chosun Daily (machine translation) reports that luxury consumption in southern Gyeonggi Province, where the nation’s 'Semiconductor Belt' is located, has rocketed. In one local department store, some luxury goods category sales are up nearly 150%. The flood of cash and spending shows that towns in Gyeonggi Province are now enjoying their own 'Gangnam Style.'

The Korean news source provides some interesting stats showing the rapid increase in conspicuous consumption since the fab workers at Samsung and SK hynix earned their envy-inducing bonuses. At a department store/mall called Shinsegae South City, located in Yongin, Gyeonggi Province, luxury jewelry sales in May were up 146.3%, it says. Moreover, luxury watch sales rose 85.3%.

Chosun Daily also shared some retail stats for the Lotte Department Store Dongtan Branch (also in Gyeonggi Province). It says that from Jan 1 to May 27, 2026, luxury sales were up 40% compared to the same period last year. A breakdown of these figures shows customers didn’t just target luxury brands but big-ticket home appliances (a category up 30%). A statement from this department store shows they are aware of the economic driving force behind the spending on luxury goods. "Sales of high-end goods such as luxury and home appliances have increased due to the boom in semiconductor companies, the creation of advanced industrial clusters, and the move-in of new large apartment complexes," said a store statement.

It was a similar story at The Hyundai Department Store, Pangyo Branch (also in Gyeonggi Province). Here, luxury goods sales were up 46.1% in May. That compares with an increase observed across all Hyundai Department Store stores nationwide of about 32%. High-end watches and jewelry (66%) and high-end clothing brands (36.9%) were major contributors to the sales boom.

With locals snapping up luxury goods like kids picking up candy, the semiconductor boom in South Korea looks like it will be highly beneficial to mostly European brands like Chanel, Hermès, Prada, Gucci, Rolex, Cartier, etc.

Recent reports suggest the good times are rolling at SK hynix, where workers are tipped to receive bonuses of up to $900,000 next year, on top of $447,000 this year. It's good to see the huge influx of RAM and NAND cash not just going to Samjeon Nix (Samsung Electronics, SK hynix) corporate accounts, or one or two billionaires, but that the good times are being shared with those at the coal face.

SK hynix will double its memory wafer capacity within five years, SK Group chairman Chey Tae-won told reporters at Computex in Taipei on June 2nd, while repeating his forecast that the AI-driven shortage gripping the memory market will run until 2030. As reported by Bloomberg, Chey declined to put an exact dollar figure on the expansion, saying instead that the company's 2026 spending would climb well above the 30.2 trillion won (roughly $20 billion) it spent in 2025, and confirmed SK hynix has filed to list American depositary receipts in New York this year.

On its own timeline, the pledge will do little to shorten the squeeze. Chey put the lead time for a greenfield fab at more than five years, placing fresh output near the tail end of the shortage window that he’s predicting. This new stance is also a significant departure from his March comments at Nvidia’s GTC conference, where he said a new fab wasn’t planned and that capacity couldn’t be added on demand.

Chey also said the cost of the buildout is difficult to pin down because prices for land, equipment, and electricity keep moving, which is likely why no figure accompanied the announcement. With the company's existing lines already saturated, customers have offered to buy SK hynix's EUV scanners and prefund fab lines as available capacity has fallen to near zero. "Until 2030, there's still some shortage," Chey told reporters

Ultimately, it’s HBM that’s driving the massive gap between wafer supply and demand. HBM consumes far more wafers per bit than standard DRAM and carries the industry's highest margins, so capacity keeps tilting toward them. SK hynix holds about 57% of the HBM market and 32% of global DRAM, and Chey has said he wants the company to become a major HBM supplier for Nvidia's Vera Rubin platform and is seeking more manufacturing partnerships in Taiwan beyond TSMC.

But buyers aren’t waiting on new fabs for relief. TrendForce projected DRAM contract prices to rise 63% in the second quarter after climbing roughly 95% in the first, and DDR4 spot pricing ran up around 2,200% over 12 months before a recent decline. Even with capacity doubling, outlooks across the next five years are unchanged, and the market is likely to stay tight for the rest of the decade as things currently stand with AI demand.

Thousands of SK hynix employees fled their factory stations earlier today as a fire broke out in a room where fluorine gas was used. Yonhap News reports that seven of the workers have been hospitalized, five are being treated for eye irritation, and two are under observation (machine translation). At the time of writing, a cleanup operation appears to be continuing at SK hynix’s Cheongju 4th campus, with all 3,600 employees evacuated. A company official told Yonhap, “There are no issues with equipment operation, so there will be no production disruption.”

Reports indicate that the fire began at around 10.23 am Korean time today. An unintentional fire is probably not a great thing anywhere in an advanced semiconductor fab, even in the burgers and cigars wing. However, in “the gas room on the 6th floor connecting the M15 and M15X factories at SK Hynix's Cheongju 4th campus,” it could have been a particularly nasty incident. This room includes equipment/canisters/pipelines holding highly toxic fluorine gas.

According to the Korean news source, the fire in the gas room was extinguished immediately by sprinklers, but fluorine escaped into the room at a concentration estimated to be 5 ppm. This is where the seven hospitalized workers had been situated.

Fluorine gas is used in various industrial processes, but it is a highly reactive gas that can cause spontaneous combustion or explosions if it comes into contact with common materials. It is also quite deadly to humans. Wikipedia states that “significant irritation of the eyes and respiratory system as well as liver and kidney damage occur above 25 ppm… The eyes and nose are seriously damaged at 100 ppm… and inhalation of 1,000 ppm fluorine will cause death in minutes.”

Official insists there will be “no production disruption”

With the immense demand and pressure on memory-making titans like SK hynix, some may be concerned that a facility like Cheongju closing even for a few hours could impact supplies, schedules, pricing, and more. However, an official insisted, “There are no issues with equipment operation, so there will be no production disruption.” It was also suggested that the fire/leak occurred in the gas pipeline, but that fact had yet to be determined.

At the time of writing, there may still be environmental purification and repair work to do. If and when that’s completed, operatives will begin safety inspections, including air quality measurements. After the all-clear, “we plan to return the employees,” the official told Yonhap. We’ve linked to the latest report on this incident available at the source.

SK hynix announced iHBM today, a memory heat management technology designed to enhance AI system performance. The thermal packaging solution improves heat dissipation by integrating ICEs (integrated cooling elements) directly into the HBM package. SK hynix says the result is an over 30% reduction in thermal resistance, “ensuring stable operating characteristics even in high-temperature and high-load environments.”

The iHBM architecture embeds non-conductive silicon cooling elements directly into the Die-to-Die Physical Layer (D2D PHY), the critical, high-speed connection interface between the HBM base die and the AI processor, which is prone to high temperature spikes as a result of extreme data traffic. By placing cooling elements in this layer, SK hynix mitigates the severe thermal throttling that cripples AI system performance during heavy computational workloads.

The company believes that structurally preventing thermal throttling will enable next-generation memory layers (targeted for future generations like HBM5) to scale to higher stack heights and sustain maximum data transfer speeds under the heavy computational loads of AI data centers.

“iHBM is the optimal solution for minimizing heat generation developed by combining memory design capabilities and advanced packaging technology,” said SK hynix Vice President Lee Kang-wook. “We will proactively provide the value customers need in the AI environment and further solidify our leadership in AI memory.”

SK hynix plans to apply iHBM technology from next-generation products, such as HBM5, to meet the thermal management requirements of high-performance computing (HPC), AI data centers, and other ultra-high-density and ultra-high-bandwidth environments, thereby improving overall system stability and efficiency.

Heat management is one of the biggest challenges facing HBM (High-Bandwidth Memory) technology. Unlike conventional memory, HBM achieves massive bandwidth by vertically stacking multiple DRAM dies, dramatically shortening the distance data must travel and enabling far higher transfer speeds with better power efficiency.

To minimize latency and feed AI processors fast enough to avoid bottlenecks, HBM is placed extremely close to the GPU or AI accelerator on the same package, connected through a high-speed silicon interposer. However, this dense arrangement also creates severe thermal problems.

The Die-to-Die Physical Layer (D2D PHY) — the ultra-high-speed interface linking the processor and HBM stacks — continuously moves terabytes of data per second. As thousands of signaling lanes and billions of transistors switch at extremely high frequencies, switching losses, leakage current, and electrical resistance generate substantial heat.

The problem is compounded by the processor itself, which already produces enormous amounts of heat. With the HBM stacks packed tightly around the processor, heat accumulates rapidly in a very small area. When temperatures exceed safe limits, the system automatically reduces clock speeds and voltages through thermal throttling to prevent physical damage, lowering overall performance.

SK hynix's new iHBM approach attempts to tackle the problem at the structural level. Unlike conventional HBM cooling designs that primarily dissipate heat indirectly through the core die and surrounding package structures, the company's iHBM architecture instead places Integrated Cooling Elements (ICEs) directly around the D2D PHY region — the exact zone where thermal concentration is most severe. This approach creates a dedicated dissipation path at the source, reducing overall thermal resistance by 30% and allowing the chip to maintain stable operation under the high-temperature, high-pressure conditions that dense AI workloads demand.

SK hynix says the technology can be manufactured at scale using its existing Wafer Level Packaging (WLP) process, which is built on its Mass Reflow Molded Underfill (MR-MUF) packaging technology already used in commercial HBM products. The design is also architecturally compatible with existing System-in-Package configurations, meaning customers can integrate the new thermal capability without major redesigns.

Samsung and SK Hynix employees are reportedly rejecting overseas training programs in favor of bonuses while seeing their matchmaking grades rise on online dating sites. According to the Korean Media outlet Chosun, discussions on Samsung Electronics’ internal bulletin board indicate that employees are considering choosing potential bonuses over hard-earned, typically coveted training programs. The sentiments come amid projections that the company plans to distribute “record-high” performance bonuses due to profit surges from the AI-driven semiconductor boom, with the company’s policies restricting eligibility.

According to the report, Samsung Electronics has exempted employees currently undergoing overseas training from bonus eligibility. This stance is reportedly seeing a number of employees terminating their training to return to their roles. Samsung runs a highly sought-after training program that provides employees around their 7th year at the company with financial and operational support to pursue postgraduate degrees at prestigious institutions both in and outside Korea. For example, in addition to their annual salaries, the company provides employees pursuing an MBA in the US with 500 million Korean won (~$333,000) in tuition and living expenses over two years. The support varies across institutions and countries.

The program is typically highly competitive, with only 1 in 70 applicants succeeding. Now, following projections that the electronics giant could distribute an average of 600 million (~$400,000)won in bonuses to employees in the semiconductor division, interest in the training programs has dropped. Reports suggest that even those currently undergoing training are considering halting midway to be eligible for performance bonuses, as these are likely to outweigh the financial benefits of the training program.

According to the Chosun report, sources from Samsung Electronics stated, “There have been inquiries to the HR team about whether trainees can withdraw mid-program and if they must repay previously received company support.” indicating that despite potential repayment obligations, some employees are willing to return regardless.

These reports are coming even as Samsung Electronics employees are planning industrial action to compel the company to extend continuous performance bonuses to employees outside the semiconductor division. The company says only employees in the semiconductor division will receive ongoing bonuses, while others in other divisions will receive a one-time payment. The strike is scheduled for the 21st of May.

At Samsung’s competitor, SK Hynix, similar reports of employees abandoning training in favor of bonuses are emerging. Despite the fact that SK Hynix takes a softer stance by offering partial bonuses to training beneficiaries, anonymous posts on its internal board reportedly include comments like, “If next year’s bonus reaches 700 million Korean won (~$466,000), not abandoning the training might make me a sudden pauper overnight” and “Seeing the projected bonuses for next and the following year, I want to cut off the hand that applied for the training.”

These comments follow projections of even bigger bonuses in the coming years, as SK Hynix paid out 140 million Korean won (~$93,000) in performance bonuses early this year, which, unlike at Samsung, was distributed across the entire company. Analysts predict a dip in the popularity of overseas training programs at Samsung Electronics and SK Hynix over the next few years, as the appeal of performance bonuses grows. SK hynix bonuses are tipped to hit $477,000 this year and as much as $900,000 next year.

Beyond strikes, life-changing decisions, and financial gain, these massive performance bonuses stemming from AI-driven profit surges are influencing quite unexpected areas of life in South Korea. Reports from Chosun indicate that SK Hynix employees are ranking higher on matchmaking companies’ eligibility scales due to bonuses and increased income, with employees reportedly being flooded with blind-date offers.

"In the past, if we matched a partner for an SK hynix employee at about a B+ grade, now it's unconditionally 'A-grade.' As the overwhelming bonus system has become known, we're seeing a trend where female members are seeking out SK hynix employees first,” said Son Dong-gyu, CEO of the matchmaking company Bien Aller.

However, on the flip side, because bonuses are paid in direct proportion to days worked, there has been an uptick in aversion to taking extended leave, such as parental leave, as these are reportedly perceived as forfeiting income. These reports all underscore the massive influence of the AI boom on almost every aspect of humanity.

A senior South Korean policymaker has proposed redistributing tax revenue generated by the country's AI semiconductor boom to ordinary citizens as a “dividend,” rattling stock markets on the same day that Samsung's union bonus talks showed no sign of resolution, according to Bloomberg.

Kim Yong-beom, presidential chief of staff for policy, floated the idea of a "national dividend" in a Facebook post late Monday, writing that gains from the AI infrastructure era were built on an industrial foundation the entire nation accumulated over half a century. The benchmark Kospi index fell as much as 5.1% before recovering to close down 2.3% after Kim clarified he was referring to excess tax revenue rather than a new windfall levy on corporate profits. A government official confirmed to the outlet that the government is not considering any such plans, and that the comments were Kim's personal opinion.

The post came during the final stretch of government-mediated talks between Samsung and its largest labor union. Negotiations entered a second day on Tuesday at the National Labor Relations Commission in Sejong after 11 hours of talks on Monday produced no agreement, the Korea Herald reported.

The union is demanding 15% of operating profit as performance bonuses, removal of the existing payout cap, and a 7% base pay increase. Samsung management has reportedly offered terms exceeding rival SK hynix's 10% profit-sharing, but the union rejected those proposals because it wants the ratio institutionalized as a permanent system.

Samsung is forecast to post roughly 330 trillion won ($220 billion) in operating profit this year, while SK hynix is projected at 239 trillion won. If the two companies hit those marks, their combined corporate tax bill alone could exceed 100 trillion won, which would surpass the roughly 100 trillion won the Korean government estimated for total national corporate tax collection in 2026, per KB Securities analyst Lim Jae-kyun.

The union has set May 21st as the start of an 18-day general strike running through June 7th if talks collapse. Seoul Economic Daily reported earlier today that the negotiations were heading toward failure, with the Korea Herald noting that the Labor Relations Commission left open the possibility of extending mediation past its scheduled close if necessary.

A one-day walkout in April cut Samsung's contract foundry output by 58% on the affected night shift, and analysts have estimated that an 18-day stoppage could cost $6.9 billion to $11.7 billion in direct production losses.

The government does have a rarely used nuclear option: Under Article 76 of South Korea's labor law, the labor minister can issue an emergency arbitration order suspending strike activity for 30 days. The mechanism has been invoked only four times since 1969, and the Labor Ministry said Tuesday it has not begun reviewing the option.

Share prices of both Intel and SK hynix have surged following a ZDNet Korea report claiming that SK is conducting R&D with Intel on 2.5D packaging using Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology, with the intention of integrating high-bandwidth memory (HBM) and logic semiconductors. Citing unnamed industry sources, ZDNet Korea reports that the company is also evaluating the materials and components required for production.

SK hynix shares have hit an all-time intraday high of $1,320 (1,946,000 Korean Won) on the Korea Exchange, climbing as much as 14.5% and pushing the company's market cap past $900 billion. Likewise, Intel's share price is up nearly 14% at the time of publication, marking a rise of 229% in the last six months, and 91% in the last month alone.

EMIB connects multiple semiconductor dies using small silicon bridges embedded directly in the package substrate, rather than relying on the large silicon interposer that underpins TSMC's Chip-on-Wafer-on-Substrate (CoWoS) platform. The approach is less expensive per package and avoids some of CoWoS's thermal complexity, though the two technologies target different segments of the market.

Intel Foundry has been actively marketing EMIB and its next-gen variant, EMIB-T, to external customers. Intel CFO Dave Zinsner told the Morgan Stanley TMT conference in March that the foundry division is "close to closing some deals that are in the billions per year in terms of revenue" on advanced packaging alone. EMIB-T, which adds through-silicon vias to the bridge for HBM4 compatibility and higher bandwidth, is expected to enter production fab rollout this year.

TSMC's CoWoS lines, meanwhile, have been massively oversubscribed for more than two years. Nvidia alone is expected to account for roughly 60% of global CoWoS demand this year, with Broadcom and AMD absorbing another 26%. That leaves limited capacity for custom ASIC vendors and smaller AI chip developers, creating an opening for alternative packaging providers.

Intel has already confirmed that some customer designs originally scoped for CoWoS have been ported to EMIB or Foveros, with reports last month that Google and Amazon are among the hyperscalers showing interest in Intel Foundry's advanced packaging capabilities, no doubt at least driven in part by limited access to CoWoS.

SK hynix is already building its own 2.5D packaging facilities independently of Intel. The company recently broke ground on a $3.87 billion advanced packaging plant in West Lafayette, Indiana, which is expected to begin operations in 2028, and approved a ₩19 trillion ($12.9 billion) packaging and test facility in Cheongju, South Korea, in January. If the Intel EMIB partnership materializes, it would give SK hynix an additional packaging pathway alongside its own in-house facilities and its longstanding reliance on TSMC's CoWoS.

Neither SK nor Intel has confirmed the rumors.

Major tech companies have begun offering to directly invest in SK hynix's new chip production lines and bankroll purchases of advanced manufacturing equipment, Reuters has reported, in what sources described as an unprecedented escalation of efforts to secure memory supply during a global shortage. SK is weighing the proposals cautiously, concerned that accepting could leave it beholden to individual buyers.

The offers go well beyond standard long-term supply agreements. Some customers have proposed funding dedicated memory production lines at SK hynix's facilities, according to people familiar with the discussions who spoke to Reuters, while others have offered to cover the cost of ASML EUV lithography machines, which are used to pattern circuits on silicon wafers and individually cost hundreds of millions of dollars.

Arrangements where customers fund dedicated production capacity are common in logic chipmaking, but they have no precedent in the memory industry, where DRAM and NAND have historically been produced speculatively and sold into an open market.

One proposal targeted the first phase of SK hynix's upcoming Yongin DRAM fab in South Korea. SK told Reuters that it’s “comprehensively reviewing various approaches and structural alternatives that differ from conventional long-term agreements," but declined to delve into the specifics. The company, now Asia's third most valuable by market cap behind TSMC and Samsung, has seen its share price rise 154% this year.

"Regardless of the type of offer, available capacity is essentially zero right now," said another source to Reuters. "There isn't even a small portion that can be designated for a specific customer."

The proposals are especially striking given the shift in the supply dynamic. As recently as February, Samsung and SK hynix were moving in opposite directions, shortening contract terms and adopting post-settlement pricing mechanisms that allowed them to capture rising spot prices. Customers are now attempting to bypass that pricing power by co-investing in the production infrastructure itself

SK hynix and its rivals, Samsung and Micron, have all acknowledged holding discussions with customers about multi-year supply deals, but those being considered by SK are entirely different. Among the mechanisms under consideration are price-band agreements that would set annual floor and ceiling prices, eliminating the quarterly negotiations that have historically defined memory pricing. Separate discussions have reportedly involved prepayment structures requiring customers to put up 30% to 40% of the contract value in cash upfront.

Samsung told Reuters that its recently signed long-term agreements with customers are "binding," though it didn’t elaborate. Suppliers are also being careful about how they distribute limited capacity, with one source telling Reuters they want to avoid the appearance of favoring specific customers during the AI buildout.

SK Group chairman Chey Tae-won said in March that he expects the memory shortage to persist through 2030, and both Samsung and SK hynix warned investors last month that supply constraints would continue through at least 2027. One source told Reuters that chipmakers don't want to "pick a horse" in the AI race and end up backing the wrong one.

The AI chip supercycle is generating such extraordinary profits at South Korea's two largest memory manufacturers that individual employee bonuses at SK hynix could average roughly 700 million won ($477,000) this year, and almost $900,000 next year, according to Korea JoongAng Daily. Samsung Electronics' labor union, meanwhile, has threatened a general strike from May 21st to June 7th after rejecting management's compensation offer.

SK hynix agreed last September to remove its previous bonus cap and allocate 10% of annual operating profit directly to employees as performance-based payouts. With analyst forecasts of some 250 trillion won ($169 billion) in operating profit for 2026, the resulting bonus pool of 25 trillion won would be split among roughly 35,000 workers. It’s understood that the company already paid profit-sharing bonuses averaging about 140 million won (roughly $95,000) per employee in February.

At Samsung, things aren’t looking quite so rosy, as disputes rage on surrounding what percentage of earnings should flow to workers. The company’s union is pushing for 15% of operating profit, which market analysts project will reach roughly 298 trillion won ($202 billion) this year. At that level, the semiconductor division alone would owe approximately 580 million won (~$396,000) per employee across its 77,000-person workforce.

Samsung management countered with a 10% allocation matching SK’s framework, but that proposal was rejected, with the union instead opting to plan a large rally at the company’s Pyeongtaek fab scheduled for April 23rd. Samsung Electronics asked a court last Thursday to block what it called “illegal activities” during a strike. Union chairman Choi Seung-ho says that roughly 200 employees have left for SK hynix over the last four months, according to the Korea Herald.

The scale of these payouts marks a huge reversal of what we’ve seen in recent years. In 2024, Samsung paid no performance bonuses at all after the chip unit posted operating losses throughout 2023’s memory downturn, while SK’s own bonus rate collapsed during the same period. The turnaround has obviously been driven almost entirely by surging demand for HBM and other AI-oriented memory products.

This potential windfall for SK and Samsung employees has sparked unusual public backlash in South Korea, with posts on the anonymous workplace forum Blind arguing that companies benefiting from state infrastructure spending and the K-Chips Act’s 20% tax credits should share their profits more broadly. The combined tax benefits received by both companies over the last two years total an estimated 20 trillion won, which is roughly $13.6 billion.

Looking ahead, the potential bonuses could climb higher still, with investment bank Macquarie having forecasted SK’s operating profit at 447 trillion won ($304.5 billion) for next year, which would push average employee bonuses beyond 1 billion won under the existing 10% profit-sharing agreement.

SK hynix disclosed in a regulatory filing on Tuesday that it will purchase 11.9 trillion won ($7.9 billion) worth of EUV lithography equipment from ASML by the end of 2027, as reported by Bloomberg. The deal is the largest single EUV order ever publicly disclosed by an ASML customer, and it runs through December 2027. SK hynix said the tools are intended for mass production of next-gen products as the company races to expand capacity for AI-driven memory demand.

Bernstein analyst David Dao estimates that the order covers approximately 30 new EUV machines over two years, slightly above his prior forecast of 26. The scanners will be deployed across two facilities: SK hynix's M15X plant in Cheongju, which is focused on producing HBM chips, and the new Yongin Semiconductor Cluster, which will handle advanced DRAM. Ryu Young-ho, a senior analyst at NH Investment & Securities, told Reuters that the equipment is expected to serve both HBM and advanced DRAM production.

SK hynix accelerated the Yongin timeline earlier this year, moving the first cleanroom opening from May to February 2027. The company committed a total of 31 trillion won ($21.5 billion) to the Yongin Phase 1 fab, which will eventually house two building shells and six cleanrooms. M15X, meanwhile, began deploying wafers in February after its first clean room opened in October of last year.

ING analyst Marc Hesselink noted in a client note that the order contains a "pull-in element" designed to lock down ASML equipment supply ahead of competitors. SK hynix is likely to increase spending on the less advanced DUV lithography machines separately, where lead times are shorter at three to six months, Hesselink added.

ASML, which announced plans to cut some 1,700 managerial roles back in January, reported a €38.8 billion order backlog at the end of 2025. Samsung and TSMC are also major buyers of EUV equipment, and all three major memory makers are expanding capacity as AI infrastructure buildout continues to strain global DRAM and HBM supply.

SK hynix currently holds more than 60% of the global HBM market and is a primary supplier to Nvidia, but Samsung is ramping its own EUV-based HBM production aggressively. SK hynix announced a separate $13 billion advanced packaging facility in Cheongju earlier this year to handle the downstream assembly of HBM chips produced at M15X.

QatarEnergy has not restarted helium production at its Ras Laffan complex — one of the largest concentrations of helium production infrastructure globally — nine days after Iranian drone strikes forced the facility offline. The ensuing disruption to supply has sparked concerns for South Korea's chip industry, Nikkei reports.

The facility went offline on March 2 following drone strikes, removing approximately 30% of global helium supply from the market. QatarEnergy declared force majeure on existing contracts on March 4, freeing it from supply obligations to customers, and industry outlet Gasworld reported on March 7 that no imminent restart is planned.

Helium consultant Phil Kornbluth, speaking at a Gasworld webinar on March 4, said that if the outage extends beyond roughly two weeks, industrial gas distributors could be forced to relocate cryogenic equipment and revalidate supplier relationships, a process that could stretch over months regardless of when Qatari output resumes.

South Korea is among the most exposed countries, which, according to the Korea International Trade Association, imported 64.7% of its helium from Qatar in 2025. The country relies heavily on helium imports to cool silicon wafers during fabrication and is understood to have no viable substitute.

The country's Ministry of Trade, Industry and Resources has reportedly launched an investigation into supply and demand for 14 semiconductor materials and equipment types with high dependence on Middle Eastern sources, Nikkei reported on Wednesday. Bromine, which is used in circuit formation, is another big concern, with South Korea sourcing 90% of its imports from Israel, also party to the ongoing conflict in Iran.

South Korean memory giant SK hynix has since said it had diversified supplies for helium and secured sufficient inventory. Meanwhile, TSMC said that it doesn’t currently anticipate a notable impact following Ras Laffan going offline, but that it’s monitoring the situation. South Korea and Taiwan each account for 18% of global semiconductor production capacity, according to Boston Consulting Group and the Semiconductor Industry Association.

The situation echoes a 2022 shortage of helium and neon, which was triggered by Russia's invasion of Ukraine. That event prompted South Korea to pursue supply diversification and domestic production of those gases, which are used in lithography to transfer circuit patterns onto wafers

Typical NAND chips present in SSDs have steadily evolved in speed and capacity over time, with contemporary server-grade units capable of reaching 28 GB/s per unit. Somehow, that's still not enough for the AI world. In turn, SK Hynix and SanDisk have jointly announced HBF, or High Bandwidth Flash, for the inference servers of tomorrow.

The official press release is exceedingly light on details, but it mentions that HBF is specifically poised to act as a layer between HBM DRAM and flash SSDs. Given that a stack of current-gen HBM3E is good for around 1.2 TB/s, we can hypothesize that HCF chips could be gunning for speeds of at least 10 GB/s each, if not more, for combined speeds in the hundreds of GB/s. After all, going to the trouble of creating an entirely new standard wouldn't make much sense otherwise.

Power efficiency is apparently a concern for the standard-bearers, a pretty understandable notion in this day and age, where datacenters have massive wattage needs. A high-end Micron 9650 SSD pulls 25 W at full tilt, a figure that gets really ugly really fast when you think in exabyte-scale deployments with tens of thousands of drives.

There are no specifics on how this new HBF is meant to interact with systems, but the vague wording of "supporting layer" could mean it would be analogous to an on-SSD cache, but much bigger. It could also be a really fast block storage device a la Optane that applications and/or operating systems would have to be tweaked to use efficiently.

The announcement offers no target date, but it mentions that "demand of complex memory solutions, including HBF, will pick up around 2030", so that's as a good estimate as any for a production release date. The standard will be under the purview of the Open Compute Project. The companies are targeting HBF at inference servers, given that the outputs that bots users produce needs to be stored somewhere, and that storage need is projected to grow exponentially.

Memory pricing cycles are nothing new, but the way it’s being sold is changing. Over the past several months, Samsung and SK hynix have begun moving away from long-term, fixed-price supply contracts, replacing them with shorter agreements and post-settlement pricing mechanisms that allow prices to be adjusted after delivery. Micron is also understood to be following a similar path.

According to reporting cited by DigiTimes, these newer contracts are appearing at the same time as the sharp upswing in DRAM and NAND pricing we’ve been watching unfold with relentless escalation, driven primarily by AI infrastructure demand and constrained supply at advanced nodes. Memory makers are expected to make over $551 billion in revenue in 2026.

Where buyers once locked in prices for six to 12 months at a time with limited scope for renegotiation, suppliers are now favoring contracts measured in quarters or even months, with pricing that’s particularly exposed to market movements, which shifts the risk back onto buyers.

Post-settlement pricing reflects supplier confidence

Under traditional agreements, DRAM and NAND prices are set at the time of signing. Even if spot prices move sharply, quarter renegotiation typically adjusts pricing within a narrow band of roughly 10%. These arrangements gave the market’s largest buyers cost predictability and insulated them from short-term instability.

Post-settlement pricing does the opposite. While products are delivered at the agreed price during the contract term, the final payment is adjusted at the end of the term to reflect prevailing market prices. If prices rise materially — as with DRAM in recent months — customers pay the difference. On the other hand, suppliers absorb the loss if prices fall.

Now, according to industry sources cited by Digitimes, Samsung, SK hynix, and Micron have all signed such contracts, primarily with large North American technology companies. One source noted that, for major customers, securing memory supply has become a higher priority than locking in price certainty, even if that means paying more later. This is nothing more than fundamental supply and demand dynamics that were bound to come into play given the state of the market in recent months.

It’s important to note that these post-settlement pricing arrangements only work if suppliers are confident that prices will remain elevated, because why would they push for them otherwise? The willingness of all the big three memory makers to adopt post-settlement pricing, unfortunately, suggests they are.

Contract lengths shrink alongside price flexibility

Pricing is not all that's changing — contract durations are also getting shorter. Memory buyers, particularly hyperscalers, are understood to have pushed for longer-term agreements to guarantee supply as demand for high-capacity memory accelerates while supply tightens. Suppliers are obviously starting to push back against those terms, opting instead for contracts lasting mere months. DigiTimes, citing Korean-language publication ET News, gave the example of a North American data center operator failing to secure a two-year supply deal from one memory vendor, subsequently sourcing capacity from another supplier under a shorter contract that included post-settlement pricing.

These supplier-favoring terms are expected to persist at least through the second half of the year, when the pace of memory price increases is projected by some analysts to plateau somewhat. Even then, few expect a return to the long, fixed-price contracts that dominated during the initial post-pandemic years, and who's to say that pricing will start to slow down in any case?

The current state of the memory market is without precedent, strangled tighter and tighter with each passing day by the unrelenting demands of an out-of-control AI bubble. While we have seen some levelling off in recent weeks, it’s borderline impossible to make any meaningful predictions in good faith about where memory pricing may or may not be even next month; we can forget about where it might be six months or more from now because there’s simply no telling.

Operating margins now at 40-50%

Recent analysis from ZDNet shows just how favorable this market has become for suppliers. It projects that Samsung and SK hynix could post NAND operating margins of 40-50% for the first half of 2026, levels that would have seemed implausible during the oversupply conditions we saw in 2022 and early 2023. Those margins are predicated not just on higher prices, but disciplined supply management and a willingness to walk away from unfavorable contracts.

ZDNet notes that the industry expects that NAND products will reach record profitability for the first time since 2017, adding that its margins are estimated to have climbed into the 20% range in Q4 2025. NAND prices are expected to rise in stages across Q1 and Q2 of this year, with conservative capital spending continuing to tighten supply and contribute to what is becoming a chronic shortage.

Not all buyers are feeling the effects of this equally, though. Apple is one company that, according to TF International Securities analyst Ming-Chi Kuo, has shifted its memory price negotiations from a six-monthly to quarterly cadence. He expects LPDDR prices to rise in Apple’s first fiscal quarter of 2026, with further increases likely in the following quarter. NAND price increases are expected to be more modest.

Kuo also notes that many smartphone brands are struggling to secure sufficient memory supply even when they’re willing to pay higher prices. Some Chinese vendors have reportedly delayed product launches or reduced hardware specifications as a result. But Apple’s position is different: While higher memory costs could pressure gross margins in the near term, Kuo suggests the iPhone maker is willing to absorb those costs to protect shipment volumes, adding that Apple is considering keeping its starting prices for its planned iPhone 18 lineup largely unchanged.

All these factors together demonstrate that there’s a structural shift taking place in how memory is allocated and sold. The balance of power has moved firmly back toward suppliers, and that’s causing contract terms to adjust accordingly.

This doesn’t mean that prices will rise indefinitely. Memory remains a cyclical, capital-intensive industry, and periods of high profitability tend to attract overinvestment. But the current contract changes suggest that suppliers are prioritizing margin discipline and pricing flexibility over volume stability, and will continue to do so in at least the medium term.

The artificial intelligence supercycle is reshaping the semiconductor and electronics industries, as the scale of the AI infrastructure buildout strains the entire supply chain. While developers of AI accelerators like Nvidia are cashing in on the AI boom, it's memory makers that will earn the most cash, according to estimates from TrendForce. Arguably, this is a result of the different business models and expansion strategies memory makers use compared to foundries, in addition to the behavior of the commodity market.

Demand outstrips supply

The company projects that while global foundry revenue is expected to total $218.7 billion, 3D NAND and DRAM revenue will reach $551.6 billion, which means that the total market for memory is more than twice as large as contract chip production. TrendForce attributes this to structural market changes caused by AI buildouts. The latter creates elevated demand for specific types of memory, creating shortages of all types of memory, and therefore affecting prices across the industry. As a consequence, while the AI industry does not need low-capacity commodity memory devices, they also become substantially more expensive amid tight supply. This creates the perfect conditions for memory makers to capitalize upon.

Indeed, the spot price of a 16 Gb DDR5 chip at DRAMeXchange was $38 on average, with a daily high of $53 and a daily low of $25. By contrast, the very same chip used to cost $4.75 on average just one year ago ($3.70 session low, $6.60 session high). Similar changes occurred to the prices of 3D NAND memory in recent quarters.

Fundamental differences

Just like some other analyst firms, TrendForce calls the AI megatrend a 'supercycle,' indicating its overwhelming ubiquity, which affects multiple industries, and its potential length.

There were two periods in the last few decades when revenue of memory makers grew significantly year-over-year for two years in a row: in 2017 – 2018, when hyperscalers built their vast data centers (+62% in 2017 and +27% in 2018), and in 2020 – 2021, when people increased purchases of PCs amid the COVID-19 pandemic. In both cases, memory makers increased capacity to meet demand and maintain their market share, which caused sharp drops in revenue back in 2019 and 2022.

The foundry industry — which is much more capital-intensive than the 3D NAND or DRAM industries — uses fabs that are harder and longer to build, and only suffered a year-over-year revenue decline in 2023.

The situation today is vastly different. On the one hand, leading developers of frontier AI models need the most powerful clusters to train their models, therefore creating demand for leading-edge hardware with expensive HBM3E memory and plenty of storage. On the other hand, these companies and their clients need more powerful inference systems to use those models. Therefore, demand for CPUs, AI accelerators, memory, and storage does not decline over time. Meanwhile, buyers like cloud service providers (CSPs) tend to be less sensitive to price increases, which is why 3D NAND and DRAM suppliers are expected to raise average selling prices more aggressively than in the past cycles.

Foundry vs. Commodity

3D NAND and DRAM are commodities, so their prices behave like prices of commodities, almost immediately reacting to tightening supply, increasing demand, or sentiment among buyers. While large PC makers purchase their memory at prices agreed upon every six months, a significant portion of memory is sold on the spot market.

This dynamic is reflected in TrendForce's projections that show memory revenue growth accelerating after the downturn of 2022 – 2023, including an expected 80% increase in 2024, followed by 46% growth in 2025, and a projected 134% surge in 2026.

By contrast, foundries tend to operate under long-term agreements that smooth price fluctuations, which prevents sharp swings that characterize memory markets. Even during periods of strong demand, foundry pricing adjustments occur gradually, which means slower revenue growth compared to memory vendors.

TrendForce models that following a 19% year-over-year revenue increase in 2024, the foundry market grew 25% in 2025 and will grow another 25% this year.

As a result, boosted by the AI supercycle and not constrained by long-term agreements, memory vendors will earn more than two times more this year alone compared to producers of logic, which have to adhere to their long-term contracts.

The biggest question

With HBM4 memory devices using four times more silicon than typical DRAM ICs, it is obvious that memory makers cannot meet all the demand that exists because of insufficient capacity, which results in price adjustments. However, the biggest question is how significantly current commodity 3D NAND and DRAM prices are influenced by insufficient supply, and how significantly they are influenced by typical commodity memory market behavior that dictates that customers buy more memory when it is getting more expensive, as it may get even more expensive in the future?