TSMC has reportedly told customers to prepare for price increases across its advanced chipmaking portfolio, extending the hikes beyond the newer 3nm process to include 7nm and even legacy products. According to a June 23rd Culpium report, the increases would affect the bulk of TSMC’s wafer revenue and could raise costs for major chip designers, including Apple, Nvidia, AMD, Qualcomm, Broadcom, and MediaTek.

The exact size of the increases remains unclear, as figures would reportedly vary by customer, node, and product category, but generally appear to fall in the 5% to 10% range. TSMC price increases have reportedly already started rolling out in some cases, while other customers have been told to build the higher cost structure into future purchase orders.

The company declined to discuss specific pricing with Culpium. “TSMC does not comment on pricing. Our pricing strategy is strategic, not opportunistic,” the company said in a statement to the publication. “We will continue to work closely with customers and sell our value to them.” Although the company had earlier said it would refrain from raising prices.

Earlier reports from Taiwanese media had mainly pointed to increases at TSMC’s 3nm node, one of its most advanced processes currently used for premium smartphones, PC, and AI chips, with price pressure also expected at the newest 2nm-class production. However, Culpium reports that TSMC has informed clients that “all advanced nodes” will become more expensive, meaning the hikes would extend beyond 3nm and 2nm to include older but still advanced processes such as 5nm and 7nm.

3nm alone accounted for 25% of TSMC’s wafer revenue in the first quarter of 2026, while the company’s full advanced-node portfolio — defined by TSMC as 7nm and more advanced technologies — accounted for 74% of wafer revenue. Therefore, the hikes would span nearly three-quarters of the company’s wafer business.

The inclusion of 7nm is especially notable because the node is no longer TSMC’s flagship technology. However, it's not exactly surprising as 7nm remains heavily used across processors, accelerators, networking silicon, and other high-performance chips. Many products remain on older, more advanced nodes because they offer better cost, yield, and maturity than the newest processes, especially when a design does not require the density or efficiency gains of 3nm or 2nm.

The client notices follow weeks of public comments from TSMC executives suggesting that higher prices were at least under consideration. At the company’s annual shareholders’ meeting in Hsinchu on June 4, CEO C.C. Wei said customers remained positive on the AI demand outlook, while also acknowledging cost pressures and the widening gap between chip demand and available manufacturing capacity. CFO Wendell Huang also said earlier that TSMC did not rule out price increases as inflation, overseas expansion, and advanced manufacturing costs continue to rise.

The timing of the price increases reflects TSMC’s strong negotiating position. The company remains the dominant manufacturer of leading-edge logic chips, and its most advanced capacity is in high demand among AI accelerator vendors, smartphone chip designers, and custom ASIC developers. With customers competing for access to the same manufacturing lines, TSMC has more room to pass on rising costs than it would in a weaker cycle.

The move also comes as TSMC benefits from a surge in AI-related demand. In its first-quarter results, the company reported $35.9 billion in revenue and a 66.2% gross margin, both supported by strong demand for high-performance computing and advanced-node production. TSMC has also raised its 2026 revenue growth target to more than 30%, with capital spending expected to remain elevated as the company expands capacity in Taiwan, the U.S., Japan, and Germany. The company’s Arizona manufacturing capacity has been sold out through 2027 since early 2025.

The reported increases are still far smaller than the recent price spikes seen in the memory market, where AI-driven demand for HBM and other high-end memory products has allowed suppliers to push through much steeper increases. Conversely, TSMC does not need memory-style pricing to meaningfully improve its margins. Because advanced nodes account for most of its wafer revenue, even a mid-single-digit increase across that base could add billions of dollars in annual revenue if demand remains strong.

For chip designers, the immediate impact is a higher manufacturing bill. For consumers, the effect is less direct but still important. A 5% to 10% wafer price increase does not automatically translate into a 5% to 10% increase in the price of a GPU, CPU, smartphone, or laptop, since the wafer is only one part of the final product cost. However, when combined with higher memory prices, packaging constraints, AI demand, and rising manufacturing costs, it creates another reason for device makers and component vendors to raise prices or protect margins by cutting costs elsewhere.

An interesting conversation on X has unearthed the existence of a rare ASML-focused Special Edition Monopoly board. Two chipmaking and engineering enthusiasts appear to have clinched a deal where one hands over an ASML Lego kit, a scale model of the world’s first High-NA EUV machine. In the no-cash deal, the other party will receive an ASML Special Edition Monopoly board. It appears that the deal is done, barring any regulatory hurdles and no one changing their minds, but it did pique our interest in the history of the board.

While we’ve seen and reported on the ASML chip tool Lego sets previously, this is the first time the firm’s special edition Monopoly set has blipped on our radar. It is possible this obscurity is due to this board game edition coming out way back in 2007, when the pioneering Dutch semiconductor company’s profile wasn’t quite as high as it is now. With the semiconductor segment becoming all the more important in recent years, driving the current AI boom, cutting-edge chip tool firms like ASML have risen to great prominence.

ASML’s special edition merchandise is also in high demand in the 2020s. Thankfully, we can learn a little more about the provenance of the headlining Monopoly board as it is featured in the board game’s Wiki. As previously mentioned, it was produced in 2007. Specifically, it was prepared for the Christmas period at the end of that year “as a gift to ASML employees and their families this holiday season.” From that ‘publisher’s description, it sounds like quite a few employees will have received one of these games, but it is still obviously an attractive collector’s item.

Sadly, the Wiki imagery doesn’t clearly show what the playing ‘tokens’ are (that’s Hasbro’s official term for the little metal playing pieces). The normal game has tokens like a boot, a dog, and a car, but we can’t quite make out the detail on this. Instead of streets and avenues, the ASML Monopoly board appears to have technologies and machines. Furthermore, the traditional stations are replaced by ASML campuses. Elsewhere on the board, special spaces include Corporate Tax and Press Release, where you must pick up a card. Regular Monopoly features such as Go, Water Works, Go To Jail, and the Electric Company remain.

Other non-consumer-facing semiconductor brands like TSMC and SK hynix have released successful sellout merchandise and memorabilia in recent years. Some items are easier for non-employees to get a hold of than others. For example, it is easy for anyone to find resellers of TSMC-related merchandise on Taiwan’s Shopee marketplace.

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer at a 50nm contacted poly pitch, the tightest pitch demonstrated to date for complementary 2D devices and one that lands within range of leading-edge silicon.

The trio presented the work this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, using a single EUV exposure to print channel lengths as short as 28nm. Imec reported that 94% of the integrated transistors switched correctly, with an on/off current ratio above 100,000. The n-channel devices use molybdenum disulfide (MoS₂), while the p-channel devices use tungsten diselenide (WSe₂) or tungsten disulfide (WS₂).

2D transition metal dichalcogenides have been studied for more than a decade — imec has been fabricating MoS₂ test transistors since the late 2010s — so while it’s not a new material breakthrough, the result is a solid milestone in terms of integration and scaling. What’s changed with this work is that both transistor polarities were built together on a standard 300mm process flow, rather than as isolated single devices patterned with coarser lithography.

The demonstrated transistors reached active widths down to 75nm and an equivalent oxide thickness near 2nm. Both polarities turned fully off at zero gate voltage, and imec said the WSe₂ p-channel devices performed close to the best lab-scale results reported so far, narrowing the gap on the historically weaker p-type side of 2D CMOS. For perspective on the pitch, 50nm is tighter than the 54nm contacted gate pitch of Intel's 10nm-class node.

Building the transistor upside down

Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, partly because the metal pins the semiconductor's Fermi level and raises the Schottky barrier that carriers must cross. Lab devices have compensated by keeping large contact areas, which in turn blocks the pitch scaling that makes the transistors worth pursuing in the first place.

To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.

"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.

EUV resolution, not High-NA

The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.

Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS₂. University groups have pushed monolayer MoS₂ transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.

2D channels

2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.

Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node, N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.

And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.

The race is on to build the massive chip packages that power the future of AI, with some technologies being developed to produce a single chip that houses a monstrous 58 chips in one unit. But the future pathway to those sorts of massive chips isn't entirely agreed upon yet, as learned at TSMC's recent European Technology Symposium that we attended.

Although panel-level packaging technologies are set to enable much larger chip packages, they will not provide, at least initially, the same interconnection densities as today's wafer-level packaging technologies like CoWoS, according to Kevin Zhang, TSMC’s senior vice president of business development and global sales and deputy co-COO.

"The geometry complexity panel-based process has to deal with is nowhere near the wafer level technology capability," Zhang said. "CoPoS, I would say it is one way to basically using panel-based process to continue driving the interposer scaling."

One of the common misconceptions in the semiconductor industry is that panel-based chip packaging technologies will replace existing wafer-based technologies like CoWoS as they promise to enable considerably larger package sizes — think 310mm×310mm, up from existing 120mm×150mm — at lower costs. This is not the case, though, according to TSMC.

"That is an option on the table," Zhang said. "But remember, if you look at our CoWoS roadmap, we still have a lot of runway left with wafer-level technologies. We can scale CoWoS all the way to 14X using wafer-level processes, and we also have wafer-level integration. […] You can integrate 58 large reticle-sized dies together. So, there is still plenty of room for us to continue advancing wafer-level integration. At the same time, our team always wants to make sure we evaluate all future options. Obviously, one of those options is panel-based packaging."

But panel-level packaging cannot leverage the tools currently used for wafer-level packaging, as essentially technologies like CoWoS use the same lithography, etching, deposition, and other tools that were previously used to make logic chips. By contrast, panel-level integration tools are considerably less advanced.

 "From technology point of view, wafer-level-based process is far more advanced than panel," Zhang said. "I am not talking about just TSMC, I am talking about the industry as a whole. Wafer-level processing is where the most advanced manufacturing technology exists today. To move to panel-based manufacturing, the industry needs to improve panel processes rapidly so they can eventually offer a better next-generation solution relative to wafer-level technology."

In fact, the main advantage that panels have over wafers is indeed larger package size: currently, TSMC can use 120mm×150mm substrates, next-generation CoWoS technologies will enable 150mm×250mm substrates, but even substrates the size of a hardcover book look pale compared to the initial 310mm×310mm panels. Furthermore, future packages can get to 515mm×510mm or even 750mm×620mm, which is larger than a wafer. When asked specifically whether CoPoS will complement CoWoS rather than replace it, Zhang essentially answered positively.

 "I think that may be a way to look at it because it depends on the specific product configuration," Zhang said. "At some of the product will continue to get optimum benefit by leveraging wafer-level processing capability. Our goal is to offer our customer all the options they would need in order to find the optimum solution for their next-generation product. CoWoS today [has a lot of] scaling room for us to continue to drive this technology forward. But at the same time, we are looking at a fan-out-based process, some use the word CoPoS, as another alternative path going forward."

TSMC is currently expected to complete its first CoPoS pilot line this June. The gap between pilot and meaningful production is often around two or three years, so a reasonable expectation for high-volume manufacturing (HVM) using CoPoS would be 2028 – 2029. However, keeping in mind that CoPoS uses new tools and since the peculiarities of these tools are unknown, it is more reasonable to expect the first CoPoS-based products in 2029 or 2030, with more meaningful volumes sometime in the first half of the next decade. At the end of the day, CoWoS existed for years before explosive adoption, so CoPoS will likely repeat this pattern.

Four Republican members of Congress have urged the U.S. International Trade Commission to block imports of foreign-made chips found to infringe U.S. patents in a case centered on TSMC, according to a recent letter to ITC Chair Amy Karpel obtained by Axios. The investigation concerns chips fabricated on TSMC's 7nm and smaller process nodes, names Apple, Qualcomm, and Broadcom among the respondents, and an initial ruling is due this month. Representative Ryan Zinke (R-Mont.) and Senators Tim Sheehy (R-Mont.), Roger Marshall (R-Kan.), and Bernie Moreno (R-Ohio) argued in the letter that strategically important companies shouldn’t receive special treatment.

The ITC began investigation 337-TA-1443 in late March based on a complaint filed that February by Longitude Licensing and Marlin Semiconductor, two Dublin-registered subsidiaries of patent licensing firm IPValue Management, which San Francisco private equity firm Vector Capital has owned since 2014.

The five asserted U.S. patents came from United Microelectronics Corporation, TSMC's Taiwanese foundry rival, in 2021. The complainants seek a limited exclusion order and cease and desist orders covering non-x86 semiconductor devices made on TSMC's 7nm and smaller nodes, along with downstream products containing them, a scope that takes in the silicon behind current AI accelerators, smartphones, and PCs. The Federal Register notice lists TSMC, Apple, Broadcom, Qualcomm, Lenovo, Motorola, and OnePlus entities as respondents.

TSMC confirmed in its latest annual report that a companion lawsuit in the Eastern District of Texas was stayed in April last year, pending the ITC's outcome, which the company said it can’t determine. An evidentiary hearing took place in February, and the full Commission decision is expected in October, according to Quinn Emanuel LLP, which is representing TSMC and Qualcomm in the investigation.

The Republicans’ letter answers an earlier push from Arizona Democrats, including Senators Ruben Gallego and Mark Kelly, along with Representative Greg Stanton, who warned the ITC that an order made against TSMC could disrupt semiconductor production, AI development, and defense systems. TSMC has committed roughly $165 billion to its Arizona manufacturing site, and North America was responsible for generating 75% of the company’s revenue last year.

The case is the most serious import-ban threat against TSMC silicon since GlobalFoundries sought to bar U.S. imports of TSMC-made Nvidia and Apple chips over node-related patents in August 2019. TSMC countersued, and both companies dropped all litigation within two months under a 10-year cross-license.

Longitude and Marlin manufacture nothing, so TSMC has no infringement counterclaims to trade, and a license fee is the complainants' ultimate goal. Any exclusion order the Commission issues in October would still face a 60-day presidential review before taking effect.

When we referred to TSMC just several years ago, we called it 'the world's largest foundry,' implying that Intel was still the world's largest producer of advanced logic chips. However, having spent nearly $240 billion on capacity expansion over the last 10 years, TSMC now has nine sites with dozens of 300-mm fabs, many of which can process orders of magnitude more wafers using EUV-based process technologies than Intel*, which makes TSMC the world's largest maker of advanced logic chips.

Being the world's largest maker of advanced AI processors requires TSMC to stay ahead of its rivals, Intel and Samsung Foundry, both in terms of process technologies and, perhaps, even more importantly, in terms of production capacity.

Therefore, TSMC has kicked off the most aggressive manufacturing expansion in its history as the company races to meet explosive demand for AI processors, logic chips made on leading-edge nodes, and advanced packaging.

During TSMC's Tech Symposium 2026 manufacturing presentations, the company revealed that in 2025 – 2026, it effectively doubled its historical construction pace, building or converting nine fab phases annually, up from an average of four phases per year. The company is simultaneously building or ramping new fabs in Taiwan, the U.S., Japan, and Germany. In addition, it introduces new ways to improve the productivity of existing facilities.

N2 ramp: Six-figure amounts of wafers per-month by 2029

The central part of TSMC's expansion plan is its N2 process technology. At present, the company is ramping up production of chips using N2 at two sites: Fab 20 phase 1 and phase 2 in Hsinchu near TSMC's global R&D center, and Fab 22 phase 1 in Kaohsiung. Ramping a leading-edge node at three facilities simultaneously is highly uncommon for foundries. The company also plans to ramp up production at Fab 22 phase 2 shortly and Fab 22 phase 3 by the end of the year. Eventually, Fab 22 phase 4 will come online as well. As a result, TSMC aims to start mass production on its N2 process technology at five facilities in the first year, which is at an unprecedented scale.

As a result of such an aggressive ramp, TSMC expects its N2 wafer-out capacity to be 45% higher than that of N3B in the first year. Reports from 2023 – 2024 indicate that TSMC ramped its N3B production at two or three phases of Fab 18 in 2023 and reached a capacity of around 60,000 wafer starts per month by the end of that year. If the reports are accurate, then TSMC expects its N2 capacity to reach around 90,000 wafer starts per month (WSPM) by the end of the year. This exceeds the fully ramped capacity of Intel's 18A-capable Fab 52, which is believed to be at around 40,000 WSPM.

What is even more impressive is that TSMC intends to increase its N2/A16-capable capacity by 70% every year through 2028, which means hundreds of thousands of WSPM in 2029.

In addition to reaching vast capacity, ramping up five fab phases simultaneously enables TSMC to mitigate risks. If one fab phase experiences a contamination issue, tool failure, or yield issues, the entire N2 supply chain will not collapse. The same applies to ramping up production at two sites located in different parts of the country: an earthquake or utility failure can interrupt production or even cause yield loss at one of them, but it will not affect another. Such risk mitigation is critically important when customers like Apple, AMD, Nvidia, or Qualcomm, which demand a continuous supply. There is potentially another bonus with ramping up these fab phases in parallel rather than in serial, so read on.

N2 ramp: One Team and the Super Manufacturing Platform

Such an unusual ramp strategy seems to be enabled by two programs at TSMC: the "One Team" collaboration between R&D and fab operations, and the Super Manufacturing Platform (SMP) that enables multiple fabs (or rather fab phases) to work as one, which likely has similarities to Intel's "Copy Exactly." TSMC hasn't shared many details about the One Team and SMP, though we can make some educated guesses.

The One Team is a global manufacturing knowledge-transfer system that links R&D, process integration, equipment management, and high-volume manufacturing expertise during technology development and ramp-up. To speed up feedback loops, TSMC likely inserts manufacturing teams relatively early in node development so that R&D teams adjust their work to what is possible at fabs. As a result, yield learning, process optimization, and tool productivity improvements can be done quickly at one fab and then transferred to others. TSMC says that One Team enabled a 20% faster technology transfer compared to N3, without disclosing the time it typically takes to transfer technology from one fab to another.

In addition, all of TSMC's GigaFab sites now rely on its Super Manufacturing Platform (SMP), which is essentially a centralized manufacturing-control system that makes multiple fabs operate as one giant synchronized fab with standard process recipes, tool configurations, metrology, and yield management flows. This should enable TSMC to transfer production between fabs more easily, ramp new nodes faster, introduce yield fixes globally instead of locally, and reduce customer requalification work when production of chips is moved from one fab to another.

Moreover, since every fab phase generates its own tool behavior data, defect density data, process window statistics, and yield learning information, multiple simultaneous ramps may actually accelerate yield/defects learning when SMP and One Team are in place. In turn, it may speed up ramping of fab phases.

A 70% CAGR in N2/A16 capacity in the coming years is an extraordinarily aggressive ramp for leading-edge manufacturing. Without something like TSMC's' One Team structure and SMP, coordinating that scale of expansion across multiple Fab 22 phases, Fab 20, and eventually Fab 21 phase 3 in Arizona would be barely possible both from organizational (operational control) and from economic (yield learning, process window, etc.) points of view.

TSMC also noted that despite the significantly higher complexity associated with gate-all-around (GAA) nanosheet transistors, N2 is achieving a better yield learning curve than N3, which again can be attributed to the innovative approaches that the company uses.

Beyond N2: A14, A13, and A12

TSMC's N2/N2P/N2X/N2U/A16 production will largely be concentrated at Fab 20 phase 1 and 2, Fab 22 phases 1, 2, 3, 4, and, to some degree, Fab 21 phase 3. However, for nodes beyond 2nm-class (A16 is essentially N2P with a backside power delivery network), such as A14, A13, and A12, TSMC will build Fab 21 phase 3 and then the all-new Fab 25 site in central Taiwan with at least four phases.

A14 is set to start high-volume production in late 2028, so there is a good chance that TSMC will ramp it at both Fab 20 phase 3 and Fab 25 phase 1. However, given the company's aggressive approach to capacity expansion, TSMC might well surprise us once again. Also, we do not yet know how TSMC plans to upgrade N2/A16-capable fabs to subsequent nodes, if at all.

Expansion beyond N2

The expansion is not limited to the N2 production node and subsequent technologies. TSMC is continuing to grow combined N3 and N5 capacity at a 25% compound annual growth rate (CAGR) from 2022 through 2027. To address immediate demand, the company is converting some N5 capacity into N3 production, which is not particularly expensive, since N3 reuses 85% - 90% of the tools used for N5. Furthermore, as much of TSMC's N3 and N5 capacities are concentrated at Fab 18 (four phases N5, four phases N3), converting some of the N5 capacity to N3 is relatively easy from a logistical perspective.

AI is here to help (to build more AI processors)

Alongside the conversion of N5 to N3 capacity, TSMC also heavily uses AI to improve the performance of each tool, and the whole fab in particular. Essentially, TSMC uses AI to build more AI processors, which seems to be a paradox, but it is becoming popularized as AI becomes embedded within workflows.

One of the things that greatly slows down cycle times of modern fabs is batch processing of wafers in various chambers, something that is an inevitable part of some 5,000 steps. Essentially, 25 wafers ‘wait’ in a (perhaps in a CVD chamber) for a lithography tool to process them individually.

Atsuyoshi Koike of Rapidus thinks differently and believes that a single-wafer processing across all steps can significantly speed up cycle time, but at the cost of tool efficiency. TSMC does not seem to plan to use single-wafer processing (despite its purchasing power, it can likely persuade fab tool makers to produce appropriate tools), but it can certainly optimize the ways in which it uses existing tools to boost the productivity of its existing fabs.

TSMC revealed at its recent Technology Summit that it uses intelligent scheduling systems that incorporate 'state-of-the-art linear programming and heuristic algorithms' to optimize equipment efficiency, though it did not reveal what exactly is done and what is achieved. TSMC further revealed that it uses generative AI algorithms to identify optimal parameters that 'challenge the physical limits of equipment' while maintaining wafer quality. In parallel, the company analyzes tool logs using big-data analytics and text-mining systems to dynamically adjust key parameters, minimize tool idle time, and maximize output.

AI systems are also used for real-time chamber condition analysis to determine optimal chamber-cleaning timing and avoid unnecessary maintenance that could reduce machine uptime and available capacity. In addition, TSMC disclosed that AI-assisted comparison and fine-tuning of large volumes of machine verification parameters reduced the time required to validate new tools and reach high-volume manufacturing by more than 20%, which helps to ramp up new fab modules faster.

TSMC also said it achieved more flexible allocation and higher combined N3 and N5 capacity at Fab 18 in Tainan by increasing equipment commonality and integrating 'cross-technologies planning,' which essentially means that the company re-uses as many tools as possible.

Expansion beyond Taiwan

Outside of Taiwan, TSMC continues to broaden its geographic footprint. In Arizona, Fab 21 phase 1 is already producing chips using N4 technology (with capacity increasing by 1.8X this year alone), while Fab 21 phase 2 is on track to start N3 production in Q3 2027. Fab 21 phase 3 targets N2 sometime later this decade, as the company continues to construct shells both for phase 3 and phase 4. The company also reaffirmed plans for an advanced packaging facility, an R&D center, and additional land acquisitions to support future expansion.

In Japan, the company’s Kumamoto Fab 23 phase 1 is already producing 28nm and 22nm chips, while Fab 23 phase 2 underwent a major strategic shift. Originally planned for 7nm-class production, the facility will instead manufacture using technologies down to N3 3nm to address stronger-than-expected local demand and onshoring intentions of local chip designers.

Meanwhile, Fab 23 in Dresden, Germany, which is under construction, is aimed at automotive and industrial applications with legacy planar transistors and FinFET-based 28nm, 22nm, N16, and N12 production nodes.

Advanced Packaging

AI itself is now one of the main drivers behind the company's unprecedented capacity growth. TSMC disclosed that wafer shipments for AI accelerators are expected to rise 11X between 2022 and 2026. The company also highlighted the rapid growth of extremely large dies exceeding 500 mm^2, as shipments of those devices are projected to increase 6X over the same period. Such products typically require lots of wafer capacity (wafer starts) and advanced packaging technologies, since many of these designs use HBM3E memory.

Advanced packaging has therefore become just as important as wafer fabrication itself. TSMC said its CoWoS capacity will grow at an 80% CAGR between 2022 and 2027, while SoIC capacity will expand at a 90% CAGR during the same timeframe. TSMC also said it has improved development-to-HVM transition times by 30% for CoWoS and by 75% for SoIC compared to earlier generations.

TSMC currently operates 11 advanced packaging facilities in Taiwan (AP1 in Hsinchu, AP2A/AP2B/AP2C and AP8 in Tainan, AP3 in Longtan, AP5 in Taichung, AP6A/AP6B/AP6C in Zhunan, and AP7 in Chiayi). According to a recent DigiTimes report, the company is simultaneously expanding multiple advanced packaging campuses, including AP5, AP6, AP7, and AP8.

The AP7 site in Chiayi will reportedly become TSMC's largest advanced packaging campus using SoIC to support major customers like Nvidia, which plans to use 3D packaging technologies for its next-generation Feynman GPUs. AP8 — converted from a former Innolux LCD fab — is expected to exceed 40,000 wafers per month of CoWoS capacity by late 2026.

While CoWoS is the de facto standard for AI processors, SoIC is set to become much more widely used in the coming years. As a result, the company is also rapidly expanding its SoIC production capacity. DigiTimes claims that AP6 in Zhunan could approach 10,000 SoIC wafers per month, whereas AP7B may add approximately 12,000 wafers per month. Future AP7 phases are expected to support both SoIC and CoPoS technologies, though CoPoS is a part of TSMC's roadmap in the 2030s.

Advanced packaging now requires tight ecosystem integration that includes HBM suppliers, substrate vendors, OSAT partners, testing companies, materials providers, and toolmakers, with which TSMC works to standardize those tools. The very emergence of such an ecosystem emphasizes the increasing role of TSMC in the burgeoning AI industry.

An all-encompassing roadmap

After investing nearly $240 billion into capacity expansion over the last decade, TSMC has evolved from the world’s largest foundry into the world's largest producer of advanced logic chips, producing the lion's share of AI processors today.

To support the explosive AI demand and to stay ahead of Intel and Samsung Electronics, TSMC has doubled its historical fab construction pace to nine fab phases annually in 2025 – 2026 while simultaneously expanding in Taiwan, Arizona, Japan, and Germany. The company's N2 ramp is unprecedented as the company preps to ramp five fab phases within the node's first year, and N2/A16 capacity is projected to grow at a 70% CAGR through 2028.

TSMC said this aggressive expansion is enabled by its One Team organizational structure and Super Manufacturing Platform (SMP), which synchronizes manufacturing, yield learning, and process control across multiple fabs. The company is also implementing various AI-driven manufacturing optimizations, including intelligent scheduling systems, generative AI process tuning, and real-time tool analytics to improve throughput, reduce cycle times, and accelerate tool qualification.

At the same time, TSMC is rapidly expanding advanced packaging capacities. The company intends to increase CoWoS and SoIC capacities at 80% and 90% CAGR, respectively, through 2027, as demand for both technologies is expected to grow as chiplet-based designs and HBM memory are technologies of choice for AI accelerators.

*TSMC's wafer processing revenue for 2025 was $103,708.5 billion, thus representing around 84% of consolidated revenue of $122.4 billion. EUV-based N3 and N5 process technologies accounted for 60% of TSMC's wafer revenue in 2025, thus earning around $62,225 billion. Intel Foundry earned $17.826 billion in 2025, $307 million came from external customers that mainly ordered advanced packaging. It is estimated that process technologies that use EUV account for more than 10% but less than 20% of Intel's wafer revenue.

Intel does not disclose a revenue split similar to TSMC's (wafer fabrication vs. packaging/testing vs. other) in its official filings, so its wafer processing revenue is hard to estimate, especially given the fact that some of its silicon is made at TSMC and is packaged internally. Nonetheless, even 20% of Intel Foundry's 2025 revenue is $3.565 billion, which is over 17 times less than TSMC earns on its EUV-based nodes.

TSMC CEO C.C. Wei has told company shareholders that it still won’t be able to completely address the production demands for AI chips in the years to come. Even though the company has opened multiple fabs across the world, including the one in Arizona, the insatiable demand for the most advanced processors means that there still isn’t enough production capacity to go around for all customers. Bloomberg reports that the additional capacity that is expected to go online in the U.S. is still not enough to feed the increasing demand from hyperscalers.

“It will be a long time before we can meet customer demand,” C.C. Wei said. Despite that, TSMC is still forecasting a 30% increase in sales this year. It’s also not taking advantage of the supply bottleneck, with Wei adding that the company will avoid sudden price hikes similar to the memory and storage chip market industry’s experience to ensure business stability.

Hyperscaler buildouts are expected to hit $725 billion just this year. And unless the AI bubble bursts, demand is only expected to go up every year. TSMC has been building many new fabs in Taiwan, the U.S., and other parts of the world. But building these manufacturing plants would take years, and it seems that semiconductor manufacturing demand would outpace supply if the current AI infrastructure build-out continues.

TSMC Arizona’s manufacturing capacity has been sold out through 2027 since early 2025, showing the massive demand for the company’s output. The company is continually expanding this site, too, with its Taiwan headquarters authorizing a $20 billion capital injection last month to continue the development of Fab 21 phase 2. It’s expected that this would allow the company to start mass producing 3nm chips in Arizona in 2027, which is about a year earlier than the original 2028 launch date. There have also been reports of additional fabs and other units, bringing the total Arizona site to 12 fabs, 4 packaging facilities, and an R&D center.

These production shortages mean that TSMC can expect that their expansion plans will have customers once they’re completed. However, this is also an opportunity for Intel, which is trying to win customers for its 18A and 14A processes. Both Apple and Nvidia are reportedly considering Intel for some of their 2028 chip production, and sources say that the former has already reached a preliminary agreement with Team Blue.

The lack of availability has also led Elon Musk into semiconductor manufacturing. Even though building chips is a totally different beast when compared to building electric cars and even rocket ships, it seems that the billionaire founder is ready to take on the challenge with Terafab. It seems that he’s pretty serious, too, with his team already in talks with various suppliers and that they’re willing to pay a premium to ensure priority.

TSMC employees are openly discussing forming a union and staging a strike after rumors spread that the company plans to cut performance bonuses by approximately 15%, according to a DigiTimes report published today. The rumored haircut comes despite TSMC posting a record first-quarter net profit of NT$572.5 billion ($17.9 billion), a 58% year-over-year increase driven by surging AI chip demand. Workers say the company's historical practice of returning roughly 13% of retained earnings as employee bonuses has been cut, even as profits climb, and they’re pointing to Samsung’s recent union deal as a template for action.

TSMC responded by saying it expects employee profit-sharing bonuses to grow faster in 2026 than in 2025, and that it is "fully aware of its growing corporate social responsibility in Taiwan," Digitimes reported.

The most likely explanation for the rumored cut, according to analysts cited by South Korean and Taiwanese media, is TSMC’s capex program. The company is spending $52 billion to $56 billion annually while constructing 12 new fabs across the U.S., Japan, Germany, and Taiwan to secure its lead in 2nm and 1.4nm manufacturing. That outlay appears to be tightening the cash available for employee compensation.

Based on 2025 earnings, the average TSMC employee bonus was approximately NT$2.64 million (roughly $87,000), with the total bonus pool reaching around NT$206.1 billion, according to Taiwan’s Liberty Times. Frustrations have risen around the ratio of profits going to employees

The unrest at TSMC has intensified in the wake of Samsung’s landmark union deal last week. Samsung narrowly avoided an 18-day factory shutdown by agreeing to allocate 10.5% of its semiconductor division's operating profit as stock-based bonuses, plus another 1.5% in cash, over a 10-year period. That deal translates to projected average payouts of roughly $340,000 per chip division employee in 2026, based on recent estimates of Samsung's operating profit.

SK hynix agreed to a similar structure last September, setting aside 10% of operating profit for employee bonuses. The comparison is undoubtedly painful for TSMC workers, who have no union and no formal mechanism to negotiate collectively; the company has operated without a labor union since its founding in 1987.

Employee frustration has spilled onto Dcard, a Taiwanese workplace community, and dedicated TSMC Facebook pages, where workers have posted complaints ahead of TSMC's shareholder meeting scheduled for May 28th at the company's Hsinchu headquarters. Some have asked whether forming a union would violate Taiwanese law, and others argue that the company prioritizes shareholder returns and overseas expansion over its workforce.

Doris Hsu, chairperson of silicon wafer manufacturer GlobalWafers, has weighed in on the broader debate, saying that across GlobalWafers' 18 factories in nine countries, some have unions and some don’t, and that the key factor in business performance is whether a company shares profits with workers, not whether a union exists.

Samsung's deal, meanwhile, is already facing legal pushback. A shareholder lawsuit challenges the agreement on the grounds that committing a fixed percentage of operating profit to employee payouts over a decade conflicts with the capital demands of chipmaking at scale.

Lip-Bu Tan, chief executive of Intel, this week confirmed that the company had already begun to work on its 10A and 7A fabrication technologies that will succeed Intel's current-generation 18A and next-generation 14A production nodes sometime in the next decade. Both 10A and 7A processes will presumably be able to use ASML's EUV lithography tools with high numerical aperture optics (High-NA), which will first be used for 14A.

"Now I am starting to work 10A, 7A, the roadmap," said Lip-Bu Tan at JP Morgan's Global Technology, Media and Communications Conference. "People do not [simply] go to you, they are looking for the roadmap for the future. So we want to build a long-term business. […]."

Tan emphasized a long-known business practice that ambitious roadmaps that are properly executed are as important as competitive products or fabrication technologies, as many companies do not just buy products, but roadmaps, as they prefer to work with suppliers for years to come. That said, Intel must offer its partners long-term roadmap visibility, so it has to work on technologies that are years from commercialization.

When it comes to Intel's 14A, its development is proceeding as planned, with version 0.5 of the process design kit (PDK) already available and version 0.9 of the PDK due in October.

"Clearly, the 14A, and we announced in Q1, we have v0.5 PDK so that they can do the test chip to look at our yield and see whether they can, over time, to really design their product and fabricate with us," Tan said. "The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Tan says multiple customers have expressed interest in 14A, though Intel has not yet disclosed them.

"We have multiple customers engaged with us [with 14A], and to really define what product, what foundry location wants to be, what kind of capacity we need," Tan said. "I do not disclose the customer. If the customer wants to disclose, we will support that."

As for Intel's 14A timeline, Intel expects risk production in 2028 and then volume production in 2029, which is about the time when TSMC begins to volume produce chips on its A14 fabrication technology.

Three things must be kept in mind here. Firstly, TSMC's A14 is not a direct rival for Intel's 14A as the latter features backside power delivery and is better suitable for high-end data center-grade processors. Secondly, TSMC is said to start making chips using A14 in late 2028, and the company tends to initiate high volume manufacturing (HVM) with very high yields and volumes. By contrast, Intel initiates volume production at development fabs, and it takes the company some time to reach comparable yields and volumes. Thirdly, Intel's 14A will be one of the first nodes to be compatible with High-NA EUV lithography systems (for select layers) and will be the first production node to have the capability to use such scanners for high-volume manufacturing.

Insertion of all-new High-NA EUV tools — along with new photoresists, new photomasks, new pellicles, new metrology tools, new design rules, new computational lithography flows, and a lot of other innovations — is not going to be easy for Intel, so the company is hard at work working with both ASML and partners to ensure that the new ecosystem is ready for prime time. Coincidentally, Christophe Fouquet, the head of ASML, reportedly said that the first test chips made using these High-NA EUV tools will emerge in the coming months, though he did not specify at which vendor or facility.

All three leading-edge foundries — Intel Foundry, Samsung Foundry, and TSMC — have initiated mass production of chips using 2nm-class process technology. Samsung was the first one to start production using its SF2 node (though it could be argued that this is a rebadged SF3P) around mid-2025, Intel followed suit with its 18A node in November (albeit at development lines in Oregon, not production lines in Arizona), and TSMC initiated high-volume manufacturing using its N2 process at two volume fabs in Taiwan in December. We outline what's next for these three leading-edge foundries.

The current state of the market

The amount of capital, expertise, and experience required to develop leading-edge process technologies and build high-volume fabs supporting advanced nodes is so high that only three companies in the world are currently capable of producing them. Companies like Rapidus have yet to prove they are a viable leading-edge chipmaker. Meanwhile, all three leading foundries are transitioning from traditional node scaling to a more segmented, architecture- and product-driven approach, but are doing so with different priorities.

TSMC is focused on predictable scaling, combined with aggressive specialization, which is why its roadmap is split into high-performance computing-oriented technologies with backside power delivery network (BSPDN) and cost/density-optimized nodes without it.

Samsung has a wide range of node variants, though it is currently more focused on yield improvement, rather than on scaling, which is why its roadmap appears more iterative than breakthrough-focused. This is perhaps why it is behind competitors with its BSPDN implementation.

Intel seems to be pursuing the most aggressive technological roadmap with a conjoined implementation of gate-all-around (GAA) RibbonFET transistors and PowerVia BSPDN, rapid iteration, and the aggressive pursuit of High-NA EUV lithography in 2027 – 2028, years before its rivals.

Intel Foundry: The most ambitious chipmaker

Being a new player in the foundry market and a large integrated design manufacturer (IDM), Intel is pursuing a multi-faceted strategy aimed at addressing the needs of its own products, as well as attempting to land customers that do not necessarily require leading-edge process technologies.

Intel's roadmap is the most ambitious, but arguably the most volatile one, when compared to the plans of other leading foundries. On the one hand, Intel needs the best fabrication technologies to differentiate its own consumer and data center products. To that end, with its 18A and subsequent process technologies, Intel bet on the simultaneous implementation of GAA transistors and a BSPDN to maximize performance, power efficiency, and transistor density. On the other hand, since Intel has zero customers from the automotive and smartphone sectors, it does not have any technologies tailored specifically for these applications.

Intel's 18A is probably the most important technology for the company in years, as it will return production of the company's consumer CPUs back to its own fabs, something that promises to greatly improve margins. Although the company is in the process of improving yields on 18A and current 18A volumes are not significant, Intel is already preparing follow-on refinements such as 18A-P (with enhanced performance and improved power efficiency) and 18A-PT (which supports through silicon vias (TSVs) and can be used for 3D-integrated systems-in-package).

Beyond that, Intel is targeting 14A and 14A-E for 2027 ~ 2028 production readiness and an early ramp. The nodes will introduce Intel's 2^nd Generation RibbonFET GAA transistors, revamped PowerDirect backside power delivery, and Turbo Cells to improve the performance of critical data paths.

These will be the company's first nodes to use High-NA EUV lithography, at least for some 14A and 14A-E variants, which will be another attempt to introduce a technology that will differentiate Intel compared to competing nodes. Intel has said that the interest in 14A from external customers is significant. Musk's Terafab project is set to make use of Intel's 14A, as a licensee, but not as a customer.

At the same time, Intel is heavily relying on node variants to address different use cases, including performance enhancements (P), feature enhancements (E), and through-silicon via support (T). These process technologies are required to enable Intel to build custom multi-chiplet products for consumer and data center applications, which directly support its strategy to produce most of its products at in-house fabs.

Intel's roadmap also includes continued investment in mature nodes such as Intel 16 and UMC 12 as the company pursues a strategy to capture demand outside leading-edge applications, to ensure steady revenue streams.

While Intel's plans are aggressive and ambitious, the abrupt cancellation of 20A in late 2024 highlights the execution risks associated with such a roadmap.

Samsung Foundry: When yields matter more than nodes

Samsung was the first company to adopt GAA transistors with its SF3E technology in 2022, three years before Intel and TSMC. However, low and unpredictable yields have limited the adoption of this technology to niche applications like cryptocurrency mining ASICs. While SF3 was more mature, it was still adopted by select applications, mostly internally. As a result, the highest-performing chips made by Samsung are produced using FinFET-based SF4P and SF4X, which puts the company behind its rivals.

For now, reducing defect density, increasing yields, and ensuring stable yields are the top priorities for Samsung. Last year, it began making mobile system-on-chips (SoCs) using its SF2 node (which it calls the 1^st Generation 2nm GAA process), but among the major goals for the company for this year is to ramp up '2^nd Generation 2nm [SF2P] and prepare performance and power-optimized 4nm process,' which suggests limited adoption of SF2. The fact that the low-power 4nm-class node will be a major workhorse for the company. The company's roadmap also indicates SF2X (HPC-oriented) in 2026 as well as SF2A (for automotive applications) and SF2Z (SF2X with BSPDN) in 2027, though we can only wonder whether these nodes will be widely adopted.

Nonetheless, Samsung's iterative approach to the evolution of its SF2 nodes (SF2=>SF2P=>SF2X=>SF2X with backside power) is evident, which gives us hope that the company's yields will gradually improve.

Samsung's next major node will be SF1.4, a 1.4nm-class process technology optimized for consumer and smartphone applications, which won't feature backside power delivery. Samsung's slides put SF1.4 above the SF3 and SF2 families, which may suggest that this manufacturing process will feature some major enhancements, such as a new GAA transistor design or other major refinements. Samsung expects to mass-produce chips on its SF1.4 technology in 2027, so it can formally leave Intel and TSMC behind with its 1.4nm node.

A big question lingers, and that's whether Samsung plans to finally start using pellicles with its EUV lithography tools starting with SF1.4, or later. A lack of pellicles greatly increases the number of potentially yield-killing stochastic mask-borne defects, which are increasingly dominant at the 2nm and are getting much worse at thinner nodes.

TSMC: New technologies like clockwork

TSMC's roadmap remains the most structured and execution-focused among the three. The world's largest contract chipmaker initiated mass production of chips using its N2 process technology — its first node with GAA nanosheet transistors — at two fabs simultaneously late last year in a bid to meet demand from a wide range of applications, starting from Apple's smartphones and all the way to AMD's server-bound EPYC 'Venice' CPUs. Initiating volume production at two fabs simultaneously is something that rarely happens in the industry, though it looks like structural changes caused by demand from the AI segment are changing many things in the industry.

TSMC is on track to start making chips using performance-enhanced N2P with traditional frontside power delivery and A16 technology that adds backside power delivery on top, a split which highlights TSMC's increasingly segment-specific approach to leading-edge technologies.

Going forward, the company is set to continue offering advanced technologies with and without BSPDN, as this feature may be too expensive for consumer and smartphone applications, but is clearly valuable for heavy-duty data center processors. For example, A14 will emerge as a smartphone-oriented node in 2028, but then will re-emerge as a data center-oriented node once it gets BSPDN in 2029.

In addition, the company will continue to offer mainstream nodes like N4C, N3C, and eventually N2C for applications that are more sensitive to costs. Automotive-specific nodes (N7A, N5A, N3A) will lag leading-edge nodes by one to two generations, as they prioritize reliability and longevity over performance and transistor density.

TSMC's segmentation and yearly cadence for advanced manufacturing nodes enable the foundry to address the most demanding clients like Apple, AMD, Intel, Nvidia, or Qualcomm with competitive process technologies. Ultimately, such cadence and a wide range of nodes reinforce TSMC's position as the most predictable and commercially disciplined foundry.

Fractured futures

To sum things up, TSMC continues to bet on execution discipline and segmentation as it ramps its 2nm-class node at two fabs to meet overwhelming demand from a variety of applications, starting from humble cell phones all the way to heavy-duty servers.

Intel leads in architectural ambitions, as currently it is the only company that uses a process technology that features both gate-all-around transistors and backside power delivery. However, the company admits that its yields will only get to world-class level by 2027, which likely makes Intel's 18A node significantly less attractive to demanding customers.

Samsung sits somewhere in the middle, offering a wide variety of process technologies for different applications, but the company's yields with GAA-based nodes have been a challenge, which is why the firm is now focused on yield increases rather than on breakthroughs, so it does not attempt to leapfrog its competitors.

TSMC's board of directors on Tuesday approved a capital injection of $20 billion into the company's wholly owned subsidiary TSMC Arizona, which will be used to continue the expansion of the Fab 21 site. While the allocation proves that the project is moving smoothly, the company is still facing multiple challenges in Arizona, including labor and water shortages, according to a report from Taipei Times.

The approval of a capital injection is a formal procedure that grants TSMC management the right to use the money for the expansion of Fab 21, and while it is an important milestone, it is a formality, as this is a part of the $165 billion expansion plan that the company introduced last year. What is more important is that TSMC's Fab 21 earned $514 million in profit last year, according to Yeh Chun-Hsien, Taiwan National Development Council (NDC) Minister. Making a profit in a new fab in the first year of full-scale operation is quite a big deal for foundries.

TSMC informed Taiwanese officials that the startup phase of its first Arizona fab proceeded more smoothly than originally projected, which strengthens confidence in the long-term viability of the site, according to Yeh Chun-hsien. At the same time, the company continues to deal with multiple operational difficulties in the U.S., including limited water availability, labor shortages, visa complications for foreign employees, concerns about long-term electricity supply, and regulatory compliance, the report claims.

Water access remains one of the most pressing issues for the project due to the dry and hot climate in Arizona. The company has previously attempted to ease concerns regarding water usage and long-term water supply at Fab 21 by incorporating extensive water recycling and treatment infrastructure capable of supporting advanced fab requirements, though it is unclear whether this has already been done. TSMC hopes to receive assistance from Arizona authorities to ensure reliable water resources for its operations, though environmental and electricity consumption regulations remain concerns as they complicate the project and prevent securing stable power delivery for the site.

Labor availability also remains another major issue. To make matters worse, the company faced difficulties obtaining visas for overseas personnel needed to support operations in Arizona due to the Trump administration's $100,000 fees on the entry of new H-1B visa holders.

In addition, TSMC is encouraging Taiwanese suppliers of semiconductor chemicals and manufacturing equipment to establish operations in the U.S. adjacent to its Arizona campus. However, Yeh noted that enabling broader supplier migration could require adjustments to Taiwan's investment-related laws.

Global semiconductor revenue reached $298.5 billion in the first quarter of 2026, up a whopping 25% from the previous quarter, according to the Semiconductor Industry Association (SIA). The SIA believes that the industry is on track to top $1 trillion in sales this year.

That nearly $300 billion of total revenue accounts for sales of logic, memory, analog, mixed signal and other types of chips. In March 2026, monthly revenue stood at $99.5 billion, which represents a 79.2% increase from $55.5 billion recorded in March 2025 and 11.5% higher from February 2026 levels. These monthly figures are calculated as a rolling three-month average by World Semiconductor Trade Statistics.

The Semiconductor Industry Association represents 99% of semiconductor revenue generated by U.S.-based companies and nearly two-thirds of chip firms headquartered outside the U.S., which means that actual sales of chips by various makers was higher than $300 billion in Q1 2026.

Unfortunately, the actual total revenue of semiconductor makers across the world is hard to estimate accurately, as privately owned companies do not share their financial results with the public.

Some companies are partially integrated and sales of their semiconductors cannot be accurately estimated (e.g, Apple, Bosch, Huawei, Sony, and Tesla). Numerous companies from China tend to fly under the U.S. radar and are therefore reluctant to share sales data with the SIA.

On a regional basis, March 2026 sales compared to the same month a year earlier increased by 108.5% in Asia Pacific, 83.1% in the Americas, 74.8% in China, 46.5% in Europe, and 7.4% in Japan. Sequentially, March sales also grew across all key markets, including 13.3% in Americas, 12.7% in China, 9.8% in APAC, 8.4% in Europe, and 7.1% in Japan.

"Global chip sales remain on track to reach $1 trillion in 2026, with Q1 sales significantly exceeding sales in Q4 2025," said John Neuffer, SIA president and CEO. "Strong sales across the Asia Pacific region, the Americas, and China drove global semiconductor market growth, highlighting broad and robust demand for semiconductors and the countless tech products they enable."

Given the current AI-driven semiconductor supercycle and predictions of years-long shortages of critical chip types, total revenues across the industry seem sure to continue their sharp rise, and manufacturers of chips of all types will likely be able to continue cashing in on the AI bonanza with every chip they can make.

JSR, the Japanese chemical maker that controls roughly a fifth of the global photoresist market, plans to build its first production facility in Taiwan to supply and co-develop advanced photoresists with TSMC, Nikkei Asia reports. The company established a joint venture with a local partner in early April and aims to bring the plant online as early as 2028, investing tens of millions of dollars in the project.

The facility will close a gap that has put JSR at a disadvantage relative to its two largest Japanese rivals. Tokyo Ohka Kogyo (TOK) and Shin-Etsu Chemical both already operate production facilities in Taiwan, where they work directly with TSMC on resist development.

Photoresist is the light-sensitive material used to transfer circuit patterns onto silicon wafers during lithography. At advanced process nodes, the resist must be precisely tuned to work with specific exposure tools and etch chemistries, and that tuning requires constant back-and-forth between the resist supplier and the foundry.

JSR currently develops products for Taiwanese customers by shipping samples from its facilities in Japan, the U.S., and Belgium. Each round trip can take weeks, according to Nikkei, dragging out an iteration process that its competitors can complete far more quickly from local production sites. A Taiwan plant would let JSR embed its engineers closer to TSMC's development teams, a model TOK and Shin-Etsu have already adopted. Beyond photoresist, JSR told Nikkei Asia that it’s also considering producing other materials at the Taiwan site, such as abrasives used to smooth semiconductor substrates.

JSR's Taiwan expansion is part of a broader expansion with the company simultaneously building the world’s first production-scale facility for metal oxide resist (MOR) in South Korea, with mass production expected to begin this year. That plant will supply Samsung Electronics and SK hynix with tin-based MOR for EUV lithography.

MOR absorbs EUV photons more efficiently than the conventional chemically amplified resists used at older nodes, enabling higher resolution with fewer pattern defects. JSR acquired MOR pioneer Inpria in 2021 and has been developing tin-oxide-based formulations since. The company plans to market MOR to TSMC as well, according to Nikkei, putting itself in place for the next generation of EUV and high-NA EUV production lines that TSMC will need at 2nm and beyond.

Japanese companies collectively hold around 80% of the global photoresist market and dominate the high-end EUV segment almost entirely. Chinese firms have made inroads at the KrF and i-line level, but their penetration at ArF and above remains minimal.

"Chinese players are a threat, but it'll still be some time before they can catch up with us and take market share," Toru Kimura, a senior officer at JSR who heads the company's electronic materials business, told Nikkei. JSR's strategy seems to be to stay ahead by locking in co-development relationships at the leading edge, which have the highest technical barriers to entry.

Asian suppliers now represent roughly 90% of Nvidia's production costs, up from about 65% a year earlier, according to data compiled by Bloomberg. That figure captures Nvidia's established data center supply chain: TSMC fabrication, SK hynix and Samsung HBM, and server assembly from Foxconn and Quanta. But the company's physical AI hardware is now adding entire new product categories that route through those same suppliers.

Nvidia's Jetson Thor robotics platform, released last August, is built on the Blackwell GPU architecture and fabricated on TSMC's 3nm process. The top-end T5000 module delivers 2,070 FP4 TFLOPS with 128 GB of LPDDR5X memory, while a lower-cost T4000 variant introduced at CES 2026 offers 1,200 FP4 TFLOPS with 64 GB at $1,999 per unit in volume. Both use Arm Neoverse-V3AE CPU cores and LPDDR5X sourced from Samsung or SK hynix.

These modules compete for TSMC 3nm wafer starts alongside Blackwell data center GPUs. Partners, including Boston Dynamics and Amazon Robotics, are building on the platform, and LG has confirmed that it’s “exploring a strategic collaboration in physical AI,” with Nvidia, including the robotics ecosystem, Bloomberg reported. Nvidia's DRIVE AGX Thor automotive SoC is another Blackwell-based product line competing for the same 3nm wafer capacity.

None of these physical AI products requires TSMC's CoWoS advanced packaging, which remains the primary bottleneck for data center GPU production, but they do consume 3nm wafer capacity and Asian-sourced LPDDR5X, both of which are already constrained.

The same memory market dynamics feeding Nvidia's newer physical AI products are simultaneously killing off its older ones. At the end of April, it was reported that Nvidia has accelerated end-of-life timelines for its Jetson TX2 and Xavier modules because LPDDR4 supply has become too constrained to maintain production. Samsung has moved away from LPDDR4 manufacturing, and AI-driven demand has redirected memory capacity toward higher-margin products.

That forces Jetson customers onto Orin or Thor modules, which use LPDDR5X from the same Asian memory suppliers whose capacity is already stretched by HBM and data center DRAM demand. TSMC's CoWoS advanced packaging for data center GPUs is growing at an 80% compound annual growth rate, TSMC's head of North American packaging told CNBC last month, and chips fabricated at TSMC's Arizona Fab 21 still ship back to Taiwan for packaging.

Nvidia committed to $500 billion in U.S. server manufacturing last year, with Foxconn and Wistron, and Amkor and SPIL are building advanced packaging facilities in Arizona. But those operations are not yet at production scale, and physical AI product lines are widening the range of components sourced from Asia faster than domestic capacity can absorb them.

TSMC's chip-on-wafer-on-substrate (CoWoS) packaging technology has become the de facto standard packaging method for advanced AI and HPC processors that use HBM memory, thanks to TSMC's aggressive development of the technology. Unlike lateral 2.5D CoWoS, TSMC's vertically integrated System on Integrated Chips (SoIC) technology with 3D interconnects has not been adopted as widely. However, now that the company has overcome the first generation's constraints, it will aggressively develop this technology in the coming years, as the company revealed at its recent North American Technology Symposium.

Different kinds of stacking

TSMC's 3D stacking SoIC technology has always been somewhat of a backburner project for TSMC, as it gained support for new process technologies slowly, when compared to CoWoS. From a pure interconnection pitch point of view, TSMC offered a rather fine 9 µm pitch in 2023, which was good enough to enable products like AMD's Instinct MI300-series. However, the 1^st generation SoIC had one major limitation: it only supported face-to-back (F2B) stacking, but not face-to-face (F2F) stacking, which is supported by the 2^nd generation SoIC technology. In 2025, TSMC achieved 6 µm pitches and expects the pitch size to decrease to 4.5 µm by 2029.

Face-to-back stacking imposes fundamental limits because signals cannot travel directly between dies. Instead, they must cross multiple metal layers and pass across through silicon vias (TSVs) in the bottom die, which increases latency, power consumption, and routing complexity.

In addition, this limits how densely connections can be implemented, since TSVs are relatively large structures that cannot be placed at fine pitch across active logic regions without affecting transistor density and design considerations. According to Broadcom, a real-world design using face-to-back stacking can achieve 1,500 signals/mm² with TSVs.

By contrast, face-to-face stacking removes the indirect signal path by aligning the metal layers of two dies directly and connecting them using hybrid copper bonding. This enables straight, ultra-short vertical interconnects without relying on TSVs, which increases signal density by an order of magnitude to 14,000 signals/mm², which therefore increases bandwidth, reduces latency, and cuts energy usage per bit.

As a result, communication between stacked dies resembles on-die wiring rather than chip-to-chip links, which is why companies like Broadcom view it as a crucial capability to scale compute density for next-generation AI and HPC processors.

3D packaging acceleration

Now that TSMC can do both F2F and F2B stacking, development of the technology will proceed much faster than before. The company now touts the usage of N3P dies on top of N4 dies, expects N2P on top of N3P within the next year, N2P on top of N2P by 2028, and envisions 3D stacked A14 dies by 2029.

Notably, the company hasn't demonstrated any process technologies with a backside power delivery in its SoIC roadmap. Yet, TSMC SVP Kevin Zhang reassured us that these nodes can support 3D integration as well.

"That may just be a simplification in the slide, A16 will have stacking capability," said Kevin Zhang, TSMC's Senior Vice President of Business Development and Global Sales, and Deputy COO.

"The SoIC roadmap shown does not cover all possible combinations — there are many permutations. The key takeaways are twofold. First, pitch scaling — from 9 µm to 6 µm, and eventually down to 4.5 µm. Second, the acceleration of stacking timelines. In the past, for example, you might stack N3P on N4, since the base die with TSV takes time to mature — 3nm TSV is only expected around 2027. But looking ahead to 2029, A14 TSV becomes available just one year after initial production. That shows how we are accelerating the schedule, enabling customers to stack the most advanced dies on top of each other much sooner."

The first face-to-face 3.5D designs

Being a leading developer of custom processors for hyperscalers, Broadcom is among the main users of TSMC's CoWoS and SoIC packaging technologies. Broadcom builds some of the world's largest system-in-packages, so it is not surprising that it is also among the first to use TSMC's F2F SoIC technology to build Fujitsu's Monaka supercomputer CPU.

On a high level, Fujitsu's Monaka processor is a heavy-duty general-purpose data center processor, and uses 144 Armv9 cores, spread over four compute chiplets made on TSMC's N2 technology, deploying a stacked face-to-face (F2F) atop dedicated SRAM chiplets (implemented on N5 technology) using hybrid copper bonding (HCB), equipped with a comparatively large I/O die that integrates the processor's memory controllers and PHYs for 12 DDR5 channels. Fujitsu's Monaka also features PCIe 6.0 connectivity with CXL 3.0 support for accelerators and memory expanders, as well as other interfaces expected from a modern data-center-class CPU.

Stacking N2-based CPU chiplets atop N5-made SRAM chiplets enabled Broadcom and Fujitsu to add massive amounts of cache to Armv9 cores to maximize their single-thread performance relatively cost-efficiently, but at the price of additional complexity and challenges surrounding thermals. Due to this, Broadcom and Fujitsu do not stack logic-on-logic, and it remains to be seen when TSMC's clients will actually start to use this option.

Broadcom is currently sampling Monaka with Fujitsu and aims to volume produce the CPU in 2027. Notably, while the company uses hybrid bonding, it also uses 9 µm pitches, which indicates that even innovators like Broadcom are cautious about using the latest versions of 3D integration technologies. This is in stark contrast to CoWoS, as TSMC's clients are eager to use the latest versions of the technology to build bleeding-edge processors.

Nonetheless, TSMC clearly positions its SoIC 3D stacking as a way to increase compute density, so it clearly has reasons to expect this technology to be used widely. After all, if transistor scaling is slowing down, packaging is inevitably becoming the scaling engine.

At the North American Technology Symposium 2026, TSMC revealed its updated CoWoS packaging roadmap with major enhancements. Within chipmaking, the reticle limit is the largest size that a chip can be printed within a single step of the manufacturing process. TSMC's previous CoWoS-based system-in-packages (SiPs) roadmaps topped out at a 9.5-reticle size.

Now the company expects to produce 14-reticle and over 14-reticle-sized System-in-Packages (SiPs) with up to 24 HBM5E stacks by 2029. Such high integration is designed to meet the insatiable demand that AI accelerators have for both compute and memory bandwidth, and signals that packaging, not lithography, acts as a primary driver for semiconductor technologies.

"AI compute scaling is driven by the combination of advanced logic, SoIC 3D stacking, and CoWoS technologies," a statement by TSMC reads.

Bigger, hotter and hungrier

It is common for contemporary process technologies to scale slowly in transistor density, while full-node scaling enables 15% to 20% higher transistor density every three years. Intra-node improvements yield diminishing returns in density, but continue to provide performance improvements and greater power efficiency. This may not be a big problem for consumer product-makers, but it greatly affects the developers of AI and HPC applications, who must improve their solutions every year or two to remain competitive.

For those customers, TSMC has begun mass production of 5.5-reticle-sized CoWoS SiPs, supporting up to 12 HBM3E/HBM4 stacks and has achieved yields over 98%, according to the company.

In 2027, TSMC's CoWoS roadmap outlines a 9.5-reticle-sized interposer that supports 12 HBM5 stacks, which is expected to require a 120 mm by 150 mm substrate. In 2028, the company expects to produce a 14-reticle-sized interposer capable of carrying 20 3D-stacked compute chiplets and 20 HBM5 modules. By 2029, TSMC expects to produce interposers over 14 reticle sizes, with up to 24 HBM5E stacks. One standard reticle measures 26 mm by 33 mm (858 mm²), so a 14-reticle-sized interposer measures 12,020 mm², or the size of a small plate, and slightly larger than a CD.

An SiP that uses a 14-reticle-sized interposer and measures 12,020 mm² will consume an enormous amount of power, will require an exotic cooling solution (think exotic cold plates like those developed by Frore Systems, immersion cooling, or a combination of both), and will require a massive substrate, which will occupy a significant share of a server motherboard's real estate. The dimensions of the SiP alone will redefine how AI servers are built, whereas power consumption and cooling requirements are poised to open doors to a host of new technologies.

48x more compute transistors, 34x more bandwidth by 2029

Such gargantuan multi-chiplet processors show that advanced packaging is now the de facto scaling engine for the industry. In fact, TSMC's lateral CoWoS and vertical SoIC technologies enable faster growth of transistor budgets than traditional Moore's Law scaling. In addition, such SiPs also offer more memory bandwidth.

Based on TSMC's expectations, its customers will be able to put (at least) as many as 24 3D-stacked compute chiplets on one 14 reticle-sized CoWoS interposer by 2029, when A14 will be in mass production. When combined with scaling enabled by the latest process technologies (4x from N7 to A14), an ultra-high-end SiP from 2029 with 24 3D-stacked A14-based chiplets will be able to carry 48x more compute transistors than a high-end SiP with two N7-based chiplets from 2024, according to TSMC. Granted, we've rarely seen frontier dual-chiplet N7-based SiPs in 2024, even a cautious Nvidia opted to use 4NP instead.

There is a catch regarding 3D-stacked compute transistors, though. The bottom die may overheat, whereas the top die must get enough power to reach its full potential. To that end, many designs use the bottom die for cache (e.g., AMD's Zen 5-based CPUs with 3D V-Cache), not for compute.

Nonetheless, even a 24x increase in the number of compute transistors per high-end SiP in five years is a breakthrough that could not be achieved by Moore's law alone. However, such integration comes at a price. In the 2030s, cutting-edge SiPs with 24 3D-stacked compute chiplets and 24 HBM5E modules will likely cost an order of magnitude more than a high-end SiP from the mid-2020s.

In addition to compute capability, large CoWoS interposers also enable considerably higher memory bandwidth simply because they can carry more HBM stacks. It is not that simple, though. Total memory bandwidth scales dramatically, driven by the combination of wider HBM4 and HBM5 interfaces, more advanced HBM base dies built on TSMC’s N3P process, and ongoing CoWoS improvements that enable faster interconnect speeds. As a result, a high-performance SiP integrating 24 HBM5E stacks in 2029 is expected to deliver up to 34x higher bandwidth when compared to a reference SiP with eight HBM3 stacks in 2024, according to TSMC.

"HBM bandwidth scaling comes from multiple factors," said TSMC. "First, there is the memory itself — progressing from HBM3 to HBM4, with higher I/O counts. In addition, we are leveraging more advanced logic technologies for the base die, which allows us to push data rates well beyond 10 Gb/s per pin, something that was unheard of in traditional DRAM. At the same time, our CoWoS technology enables integration of more HBM stacks within a single package. […] All of these factors together — higher data rates, more I/O, and more stacks — contribute to the overall bandwidth scaling."

Slower transistor scaling

One of the things that strikes the eye about the current and upcoming process technologies due later this decade is the slow scaling of transistor density. While A14 is set to increase per-chip transistor density by 20% compared to N2 technology in 2028, its optical-shrink successor (A13) is only poised to provide a 6% higher density a year later.

Fortunately, TSMC continues to aggressively develop its CoWoS packaging technology, which promises to enable developers of system-in-packages to put 24 3D-stacked compute chiplets and 24 HBM5E modules onto one massive 14 reticle-sized interposer before the end of the decade. This will increase compute transistor count and memory bandwidth per SiP by 48x and 34x, respectively, compared to high-end data center SiPs in 2024, according to TSMC.

However, this level of integration will likely come at a high cost. System-in-packages with up to 24 3D-stacked compute chiplets and 24 HBM5E stacks in the 2030s will probably cost an order of magnitude more than high-end SiPs from the mid-2020s.

Taiwan's stock market is now worth more than the United Kingdom's, according to recent Bloomberg data, in a shift driven almost entirely by the insatiable global appetite for AI chips. The island's listed companies carry a combined valuation of roughly $4.3 trillion, edging past Europe's largest equity market, despite Taiwan's economy being less than a quarter the size of the UK's. South Korea, powered by Samsung and SK hynix, is roughly $140 billion behind and closing fast.

As for Taiwan’s stock market constituents, TSMC makes up the bulk, with a market cap of approximately US$1.98 trillion, or 40% of Taiwan’s entire stock market value. No other major economy has this degree of single-company dependence. By comparison, Apple represents roughly 7% of the S&P 500.

On Thursday, Taiwan's Financial Supervisory Commission raised the single-stock investment cap for local equity funds from 10% to 25% of a fund's net asset value. The change applies only to companies whose market weighting exceeds 10%, a threshold TSMC alone meets. That adjustment triggered a 4.3% jump in TSMC shares on Friday and pushed the benchmark TAIEX up 2.7%, according to Taiwanese media.

TSMC reported record first-quarter earnings last week, with net income up 40.6% year-over-year to roughly $18 billion. The company raised its full-year revenue guidance to more than 30% growth and confirmed plans to add another 3nm fab to meet AI demand, which it expects to outstrip supply through 2027.

South Korea's market, KOSPI, has already overtaken both Germany and France this year and is up 44% in 2026. Samsung and SK hynix account for nearly half the index's total weighting. The former’s share price has nearly quadrupled since the start of 2025, while SK hynix has risen roughly sixfold over the same period. These gains reflect the ongoing memory supercycle, with demand for HBM far exceeding current production capacity.

William Bratton, head of cash equity research for Asia-Pacific at BNP Paribas, told the Financial Times that, aside from ASML, European-listed equities have almost no exposure to the current AI hardware buildout. He added that South Korea could overtake the UK as well if the current rally continues.

The disparity between these semiconductor-heavy Asian markets and Europe highlights how narrowly the financial benefits of the AI infrastructure boom are distributed. Taiwan's GDP is roughly $977 billion, according to IMF estimates, versus the UK's $4.3 trillion. While the gap between those two economies hasn’t changed, the gap between their stock markets has.

TSMC revealed its general manufacturing technology roadmap through 2029 at its North American Technology Symposium 2026 on Wednesday. Among the key highlights the company presented were its 1.2nm and 1.3nm-class fabrication processes called A12 and A13, an unexpected extension of the N2 family named N2U, and the lack of plans to use High-NA EUV lithography for any nodes through 2029. Perhaps the most notable part of the technology-related announcement was firming the multi-faceted approach to new node development.

"Last year we announced A14 as our most advanced, 2^nd Generation nanosheet technology, scheduled for production in 2028," said Kevin Zhang, senior vice president of business development and global sales and deputy COO at TSMC.

"This year, we are introducing derivatives of A14, including A13 and A12, both planned for production in 2029. A13 is an incremental enhancement of A14 achieved primarily through optical shrink, delivering about 6% area reduction while maintaining full design-rule and electrical compatibility, enabling customers to benefit with minimal redesign."

Changing the rules of the game

Historically the lion's share of TSMC's revenue originated from the smartphone industry, but more recently AI and HPC have outpaced handsets. This was clearly reflected in the company's plans, so TSMC's latest roadmap highlighted a deliberately bifurcated strategy that segments leading-edge nodes by end-market requirements rather than pursuing a one-size-fits-all approach. As a result, the company is adopting a new strategy for process technology introductions in which it will continue to offer a new node for client applications every year and will roll-out a new node for heavy-duty AI and HPC applications every two years.

On one hand, processes like N2, N2P, N2U, A14, and A13 are aimed at smartphones and client devices — where costs, power efficiency, and IP reuse are crucial and strong design compatibility is welcome, while incremental improvements can be tolerated as long as TSMC can deliver a new node every year.

On the other hand, nodes such as A16 and A12, aimed at AI and HPC application, must offer strong performance improvements to justify transition to newer technologies, and costs are less important. These nodes integrate Super Power Rail backside power delivery (SPR) to address power integrity and current delivery constraints of AI data center and HPC workloads and offer tangible performance, power, and transistor density improvements — albeit, at a biennial cadence.

*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.

A13 and N2U: New nodes for client applications

Last year TSMC introduced its A14 process technology, which is set to rely on the company's 2^nd Generation gate-all-around (GAA) nanosheet transistors, offer additional design flexibility with NanoFlex Pro technology, and serve as the foundry's premium node for high-end smartphone and client applications sometimes in 2028. This year the company announced A13, which will build upon A14.

TSMC's A13 is an optical shrink of A14 designed to extract additional efficiency with minimal disruption. A13 reduces linear dimensions by about 3% (to ~97% scale), which translates into roughly 6% higher transistor density amid maintaining full design-rule and electrical compatibility with A14. From many points of view, A14 continues TSMC's long-standing tradition of offering optical shrinks of its process technologies (N12, N6, N4, N3P) — though, previously, these could deliver more tangible benefits in general. The approach enables TSMC's customers to reuse IP with little to no redesign effort, but with only incremental improvements.

While A14 is set to deliver full-node improvements in power, performance, and density, to extract them, chip and IP designers must use all-new tools, IPs, and design methodologies. By contrast, A13 delivers incremental gains enabled by design-technology co-optimization (DTCO), but which does not require to change anything to extract these gains. A13 is expected to enter production in 2029.

In addition to offering customers its all-new A14 node in 2028, TSMC plans to offer them a cheap way to improve their N2-based designs with N2U. N2U will be the third-year extension of the N2 platform that leverages DTCO to provide about 3% – 4% higher performance at the same power or 8% – 10% lower power at the same speed while allowing a modest 2% – 3% logic density improvement. The node will maintain compatibility with N2P IP, which will enable its customers (particularly from the client space) to build new products without transition to an all-new process and incur rather massive costs. For example, if a company plans to build a mid-range product using IP of a high-end product implemented using N2P in 2027, it can do it with N2U in 2028.

"We continue to extend our 2nm platform with N2U, which provides additional improvements in performance, power, and density through design-technology co-optimization," Zhang said. "Our strategy is to continue enhancing each node after introduction, allowing customers to maximize the return on their design investments while still gaining incremental PPA benefits."

A16, A12, and N2X: Maximum performance at any cost

While TSMC's N2 is set to be adopted both for client and data center applications, the company preps A16 with its Super Power Rail backside power delivery that is specifically tailored for high performance data center applications. Essentially, A16 is N2P with SPR that will rely on the 1^st Generation nanosheet GAA transistors and provide significant power, performance, and transistor density advantages over N2 and N2P nodes, albeit at higher cost.

It is noteworthy that TSMC now lists A16 as a 2027 process technology, which is technically a slip from 2026.

"A16 will be ready for production in 2026," Zhang said. "However, actual product ramp depends on customers, and we expect volume production to begin in 2027. That is why we aligned it to that timeline."

Interestingly, the arrival of A16 does not replace N2X, a performance-enhanced variant of N2P that uses traditional front side power delivery to push clocks of N2-based designs to the max.

A16 will pass the baton to A12 — set to arrive in 2029 — which is projected to bring full-node advantages to TSMC's data center-class nodes. While TSMC does not disclose actual numbers, expect A12 to offer the same kinds of benefits over A16 as A14 brings over N2 as it is set to rely on the company's 2^nd Gen nanosheet GAA transistors and NanoFlex Pro technology.

“I can say that A16 is our first-generation technology with Super Power Rail, or backside power delivery, and A12 is the next generation,” Zhang said. “A13 and A12 are built on A14 with significant geometric scaling. To continue shrinking the frontside geometry, you also need to scale the backside to achieve overall density benefits. So there are many enhancements being implemented as we move from A16 to A12, particularly related to backside power delivery. That is all I can share.”

No High-NA on horizon

One interesting thing to note about TSMC's upcoming A13 and A12 process technologies due in 2029 is that none of them will require High-NA EUV lithography tools, which is stark contrast to Intel's approach to its 14A production node and successors that are set to use High-NA EUV scanners starting in 2027 – 2028.

"I tell you, I am amazed by our R&D team," said Kevin Zhang. "They continue to find a way to drive the technology scaling without using High-NA. One day they may have to use it, but at this point, we continue to be able to harvest the benefit from current EUV, not have to go to High-NA, which, you know, very, very expensive."

TSMC this week posted financial results for the first quarter of 2026 and lifted its 2026 revenue guidance and capital expenditures to the high end of its original expectations. Accelerating sales of AI accelerators and accompanying hardware increases demand for TSMC's wafers, which is why the company said it would build another 3nm-capable fab in addition to those already planned. But while the company is confident in its long-term prosperity driven by the AI megatrend, it warned about profitability due to the war in the Middle East.

AI megatrend earns TSMC tens of billions in one quarter

"Our conviction in the multiyear AI megatrend remains high, and we believe the demand for semiconductors will continue to be very fundamental," said C.C. Wei, chief executive of TSMC, during the company's earnings conference. He admitted that capacity during the quarter was 'tight,' whereas Jen-Chau Huang, TSMC's chief financial officer, confirmed 'higher-than-expected' overall capacity utilization.

Indeed, the HPC segment (an ambiguous term that TSMC uses to describe everything from client PCs to high-end AI accelerators) accounted for 61% of TSMC's revenue in Q1 2026 (or approximately $21.9 billion), up from 46% in Q1 2024 (approximately $8.68 billion), which represents colossal growth in just two years. The smartphone segment accounted for 26% of TSMC's earnings in Q1 2026, whereas IoT and automotive commanded 6% and 4% of the company's revenue in the same quarter.

Based on TSMC's annual report released this week, it looks like Nvidia, with its aggressive capacity booking strategy, has become TSMC's top customer, accounting for 19% of the foundry's revenue for 2025, dethroning Apple, which was responsible for 17% of TSMC's earnings for 2025.

On the fabrication technologies side of matters, TSMC's 5nm-class nodes accounted for 36% of the company's wafer revenue in Q1 2026 (driven by the success of Nvidia's Blackwell AI accelerators), 3nm-class processes were responsible for 25% of the foundry's earnings, while 7nm-class technologies represented 7% of TSMC's revenue. In general, advanced nodes (7nm and below) accounted for 74% of the company's earnings. Yet, keep in mind that while TSMC is mass producing 2nm-class (N2) chips for its customers, it has not formally shipped them to clients and therefore does not recognize 2nm-related revenue.

Capacity additions

As Nvidia's leading AI platforms, as well as offerings from other vendors, are set to shift from TSMC's 5nm-class family of nodes (N5, N4) to 3nm-class lineup of process technologies (N3), demand for the latter is going to skyrocket this year and remain strong for years to come. To meet this demand, TSMC will add three N3-capable fabs to its lineup over the next couple of years.

"Historically, we do not add additional capacity to a node once it has reached its target capacity," Wei said. "However, as a foundry, our first responsibility is to provide our customers with the most advanced technologies and necessary capacity to unleash their innovations. Based on our assessment, to meet the strong demand for AI applications, we are stepping up our CapEx investment to increase our N3 capacity."

First up, the company will add a new N3-capable fab module to its Gigafab cluster at Tainan Science Park, aiming to start volume production in the first half of 2027. While TSMC has been building the fab module for some time, this is the first time it has disclosed its capabilities.

Secondly, TSMC's N3-capable Fab 21 phase 2 in Arizona is on track to come online in the second half of 2027. This is the first time the foundry has clarified when Fab 21 phase 2 is set to begin making chips. TSMC's CEO also confirmed that the company had acquired the second plot of land near Fab 21 to build additional fab modules, though he never confirmed how many fab modules would be built.

Thirdly, the company plans to upgrade the capabilities of its Fab 23 phase 2 (aka JASM phase 2) to 3nm by installing more advanced equipment. Originally, Fab 23 phase 2 was projected to make chips on N6 (6nm-class) and N7 (7nm-class) fabrication technologies, then TSMC pondered upgrading it to N4 (4nm-class). Now, the plan is to make it N3-capable when it comes online in 2028.

The decision to add 3nm capacity was not made overnight, though it looks like TSMC expects demand for FinFET-based N3 — its final FinFET node — to remain strong well into the second half of the decade (it takes a year to ramp up a fab, so these three fabs will contribute meaningfully to TSMC's capacity in 2028 - 2029). Separately, the company will continue converting N5-capable facilities into N3-capable fabs in Taiwan and make some of its fabs capable of building chips on N7, N5, and N3 nodes.

"In addition to all the new fabs, we continue to convert 5nm tools to support 3nm capacity in Taiwan," Wei added. "We are also leveraging our manufacturing excellence to drive greater productivity across our fab in all locations to generate more wafer output. We are also focusing on capacity optimization across nodes, including flexible capacity support among N7, N5, and N3 nodes."

One of the main challenges for TSMC's expansion is to get fab tools to support new capacity as fast as possible, but this is not easy, as leading suppliers of semiconductor production equipment are also constrained in terms of capacity.

"We try very hard to speed it up and pull in all the equipment as we can, [but] our supply is very tight," Wei said. "Demand is continuing to increase, so we continue to work with our suppliers to speed it up."

As far as TSMC's N2 and A16-capable capacity is concerned, the company is currently ramping Fab 20 in Hsinchu Science Park and Fab 22 in Kaohsiung Science Park. While the capacity of the former will remain largely intact in the coming years, Fab 22 will gain capacity aggressively over time, according to Global Semi Research, though TSMC did not touch upon N2 capacity expansion during the earnings call.

Another record quarter, but there may be hiccups

TSMC's first quarter revenue reached $35.9 billion, an increase of 40.6% year-over-year, and a 6.4% rise over the previous quarter. The company's net income totaled $18.2 billion, which is the company's highest net profit for a quarter, while its gross margin was 66.2%. TSMC expects its Q2 2026 revenue to be between $39 billion and $40.2 billion, which is a 32% year-over-year growth.

"Our business in the first quarter was supported by strong demand for our leading-edge process technologies," said Wendell Huang, Senior VP and Chief Financial Officer of TSMC. "Moving into second quarter 2026, we expect our business to be supported by continued strong demand for our leading-edge process technologies."

In addition, the company indicated that for the full year 2026, it expects revenue to increase to over 30% (up from its original expectations of around 30%) over the previous year to approximately $158 billion, which gives it an opportunity to increase its CapEx budget towards the high-end of its guidance between $52 billion and $56 billion.

Meanwhile, TSMC warned that its costs may increase due to the ongoing war in the Middle East.

"In addition, given the recent situation in the Middle East, prices for certain chemicals and gases are likely to increase," said Huang. "Based on our current assessment, there may be impact to our profitability, but it is too early to quantify the impact."

TSMC's chief executive has warned that Intel Foundry is a 'formidable' rival in the chipmaking industry at the company's most recent earnings call. Despite not yet landing many high-volume external customers, Intel's semiconductor production operations remain among the largest in the industry, a fact now more keenly felt by TSMC.

"We view Intel as our formidable competitor and do not underestimate them," said C.C. Wei, chief executive of TSMC, during the company's latest earnings call this week. "But having said that, there are no shortcuts. The fundamental rules of the foundry game never change: they need the technology leadership, manufacturing excellence, customer trust, and most of all, the service [to win market share]."

Although TSMC produces a significant percentage of Intel's products, the company still makes the bulk of its products, including its data center-grade server CPUs, at its own fabs. Intel's Xeon processors command a larger server CPU market share than AMD's EPYC products (even though AMD has captured the most lucrative parts of the market thanks to high core count and performance), so Intel is not an underdog.

Furthermore, the company is now ramping up production of client Core Ultra 3-series 'Panther Lake' and data center Xeon 6+ 'Clearwater Forest' CPUs at its Fab 32 in Arizona using its 18A fabrication process (1.8nm-class) that relies on gate-all-around RibbonFET transistors and boasts a backside power delivery network called PowerVia. While TSMC's N2 production is now ramping at two fabs and also uses GAA nanosheet transistors, it does not support a BSPDN, which makes Intel's technology somewhat more progressive, at least for some designs. TSMC's A16 will bring an even better BSPDN implementation called Super Power Rail (SPR), but this will happen only in late 2026.

When it comes to revenue from chip production and packaging (and associated services), TSMC earned $33.731 billion in Q4 2025, whereas revenue of Intel Foundry was $4.5 billion, which makes Intel Foundry the world's second-largest foundry, but a long way off first place. TrendForce estimates that Samsung Foundry earned $3.399 billion in Q4 2025, SMIC's revenue was $2.489 billion, UMC's earnings totaled $1.993 billion, whereas GlobalFoundries followed with $1.83 billion in the fourth quarter of last year. While Intel Foundry primarily serves the Intel Products division and provides advanced packaging for AWS and some other companies, so does Samsung Foundry, as its parent company's LSI and Semiconductor divisions are its key customers.

It remains to be seen whether Intel's 14A process technology will gain traction with external customers and whether the company will ever have production capacity comparable to that of TSMC. Yet, at this point, there are only three companies in the world — Intel, Samsung, and TSMC — that still have ambitions and the capability to produce logic chips on leading-edge process technologies, which is another reason why TSMC calls Intel a formidable rival. At the end of the day, being one of the three semiconductor champions already deserves respect.

Intel CFO Dave Zinsner told the Morgan Stanley TMT conference last month that Intel Foundry is "close to closing some deals that are in the billions per year in terms of revenue" on advanced packaging alone, with EMIB-T, the next-generation variant of Intel's embedded bridge technology, driving customer interest as TSMC's CoWoS-L capacity remains structurally oversubscribed.

That tech, EMIB-T, which adds through silicon vias (TSVs) to the bridge, is expected to enter production fab rollout this year and addresses the limitations that have kept standard EMIB out of high-power AI accelerator sockets: HBM 4 class power delivery and large package scaling.

If these “billions per year” in deals close, it’d mark quite the turnaround for Intel Foundry, which generated just $307 million in external revenue last year against a $10.3 billion operating loss. Given that 18A isn’t expected to reach industry-standard yields until next year at the earliest, packaging is the fastest on-ramp for Intel, and EMIB-T is what could convert that into AI accelerator revenue. Intel Foundry's most recent announcement aligns well with this, having signed up to join Musk's Terafab project, though the reality of the effort delivering on all that's been promised remains extremely optimistic, as we've broken down.

EMIB-T and PSVs

Standard EMIB, which has been in volume production since 2017, embeds small silicon bridge dies in cavities within an organic substrate to route signals horizontally between adjacent chiplets, avoiding the cost and reticle limits of a full silicon interposer.

Intel deliberately skipped through-silicon vias entirely with EMIB, keeping the bridge die simple and cheap. That meant power had to be routed around the bridge via the organic substrate in long, resistive paths, limiting the current that could be delivered to the dies above. That ceiling was fine for the likes of Sapphire Rapids and Ponte Vecchio, but not for HBM4-class accelerators.

EMIB-T reverses that decision by adding through-silicon vias (TSVs) to the bridge die. In doing so, EMIB-T enables vertical power delivery directly through the bridge, integrates Metal-Insulator-Metal capacitors for noise suppression, and adds a copper ground plane grid for signal isolation.

Dr. Rahul Manepalli, Intel Fellow and VP of Substrate Packaging Development, gave us a look into the full specifications of EMIB-T at last May’s Electronic Components Technology Conference — a 45-micron bump pitch with a roadmap to 35- and 25-micron, energy efficiency of around 0.25 pJ/bit, and UCle-A interfaces running at 32 Gb/s of data transfer or higher per pin. EMIB-T supports HBM3, HBM3E, HBM4, and future HBM5 stacks, and scales to a 120mm x 180mm package supporting more than 38 bridges and over 12 reticle-sized dies.

Intel then followed up just before Christmas with a conceptual 2.5D/3D package integrating 16 compute elements across eight base dies, 24 HBM5 stacks, and a 10,296 mm² silicon footprint, scaling to 12x reticle size and beating TSMC's planned 9.5x CoWoS-L ceiling. For comparison, TSMC's CoWoS-L roadmap targets 5.5x reticle this year and 9.5x by 2027, while Intel is targeting 8x reticle in 2026 and 12x or more by 2028.

Bernstein analysts estimate a substantial cost differential, with EMIB packaging running in the low hundreds of dollars per chip versus an estimated $900 to $1,000 for CoWoS on a Rubin-class accelerator, according to figures cited by Investing.com in recent packaging analysis. Intel also claims roughly 90% wafer utilization for bridge dies versus approximately 60% for large interposers.

CoWoS-L bottlenecks

TSMC has expanded CoWoS capacity from approximately 35,000 wafers per month at the end of 2024 to roughly 80,000 by the end of 2025, with a target of around 130,000 by the end of this year through new facilities at AP7 in Chiayi and AP8 in Tainan. As a result of these aggressive ramp-ups, Counterpoint Research projects industry-wide advanced packaging capacity could expand by roughly 80% year-over-year in 2026.

Nvidia secured more than 60% of TSMC's total CoWoS capacity for 2025 and 2026, with every Blackwell GPU and the upcoming Rubin architecture requiring CoWoS-L. At the back-end of 2025, it was reported that TSMC’s CoWoS capacity was stretched due to AI demand, and that Intel was picking up packaging interest from firms either blocked from accessing CoWoS or looking for a shorter path to production.

TrendForce then reported in early December that both CoWoS-L and CoWoS-S were fully booked, and that Google had cut its 2026 TPU target by 1 million units due to allocation limits. TSMC CEO C.C. Wei, of course, said during the Q3 2025 earnings call that AI-related capacity, both front-end and back-end, remained very tight, falling “about three times short” of AI demand.

Only a handful of customers have been publicly named as being interested in EMIB-T, and there’s been no official confirmation by Intel to date. MediaTek was named by the Commercial Times back in November as actively recruiting engineers with EMIB experience, with the publication adding that Intel was “tapping Intel’s advanced EMIB-T packaging” to secure more capacity. Amazon is reportedly another named customer, claiming Intel is in active discussions with AWS for Trainium-class custom AI processor packaging.

Meanwhile, standard EMIB has the customer pipeline that EMIB-T doesn’t. Nvidia's $5 billion September 2025 investment in Intel includes confirmed use of EMIB and Foveros, with Jensen Huang and Lip-Bu Tan naming both technologies on the joint announcement call, and DigiTimes has reported that approximately 25% of Feynman GPU packaging will run through Intel. Microsoft's Maia AI accelerator is Intel Foundry's marquee 18A customer under a $15 billion lifetime contract originally announced at Intel Foundry Direct Connect 2024, while Google is understood to be designing EMIB into its 2027 TPU v9.

Intel’s Foundry VP of Packaging, Mark Gardner, told EE Times way back in March last year that Intel is "in production today and have been in production even last year in cases where we took things that were designed for CoWoS and are now designed for manufacture with either EMIB or Foveros," confirming that live design migration off TSMC is already occurring on the standard EMIB platform.

EMIB-T for Jaguar Shores?

Clearwater Forest, the 288-core Xeon 6+ E-core server processor formally launched in H1 2026 after a delay from its original 2025 target, uses second-generation standard EMIB combined with Foveros Direct 3D hybrid bonding across a 17-tile package. The configuration spans 12 compute tiles on Intel 18A, three base tiles on Intel 3, and two I/O tiles on Intel 7, connected by 12 EMIB bridges. Diamond Rapids, the Xeon 7 P-core server processor with up to 192 cores, also targets H2 2026 using standard EMIB plus Foveros.

Jaguar Shores, the successor to the canceled Falcon Shores AI accelerator, is the likely first Intel product to use EMIB-T. A leaked test chip showed a 92.5mm x 92.5mm package with four compute tiles and eight HBM4 interfaces on Intel 18A. That HBM4 integration is exactly the use case that standard EMIB will struggle with, making Jaguar Shores the natural first home for the variant. Panther Lake, Intel's first 18A client processor shipping in volume since late 2025, uses Foveros-S 2.5D rather than any EMIB variant.

No EMIB-T customer production for a ‘year or two’

Intel's packaging footprint spans three continents. In Rio Rancho, New Mexico, Intel launched the Fab 9 facility in January 2024 as the first co-located high-volume advanced packaging site, adjacent to the existing Fab 11X and backed by a $3.5 billion investment. Intel later received $500 million in CHIPS Act funding earmarked for further modernization of Fab 9, Fab 11, and Fab 11X.

In Asia, the Penang, Malaysia, advanced packaging complex is 99% complete, with first-phase operations beginning sometime this year. Intel has also outsourced EMIB production to Amkor’s Songdo K5 facility in South Korea — described as a “first-ever” outsourcing move by TrendForce — with additional Amkor sites planned in Portugal and Arizona.

However, EMIB-T itself hasn’t yet shipped in any commercial product. Standard EMIB has been in volume since 2017 and is what every named Intel packaging customer is currently using, but the TSV-enhanced variant is only now due to roll out, with external customer designs expected in production "in the next year or two," says Mark Gardner.

China is stepping up efforts to pilfer semiconductor-related know-how and experienced workers from Taiwanese companies, reports Reuters, citing Taiwan's top security agency. The report claims that external restrictions on shipping advanced fab tools and other technology to the People's Republic of China are among the reasons why the mainland is attempting to grab those resources from the island nation.

China is targeting Taiwan's semiconductor ecosystem to gain access to advanced chip manufacturing technology and skilled talent in a bid to bypass those international restrictions, according to Taiwan's National Security Bureau. In particular, China uses indirect methods — front companies, recruitment schemes, and covert channels — to poach engineers, obtain sensitive know-how, and even procure restricted fab tools, the NSB claims.

Taiwan is famously home to TSMC, the world's largest and most advanced contract chipmaker, which produces chips using 2nm-class fabrication technologies in high volume. By contrast, China-based SMIC can only mass produce chips on 7nm-class nodes, which are at least two generations behind TSMC's technologies.

The PRC cannot get sophisticated tools from Europe and the U.S. to develop its own advanced manufacturing processes and use them for high-volume production. As a result, the efforts of Chinese companies and even government-linked entities to steal technologies, talent, or restricted pieces of equipment will inevitably continue. Even as far back as the 2000s, international courts found SMIC guilty of illegally obtaining fabrication technologies from TSMC, so the Chinese foundry had to pay the Taiwanese company compensation.

Nowadays, it is close to impossible to steal the secrets of a semiconductor manufacturing process without stealing the fab itself, so Chinese attempts to obtain Taiwanese chip-making know-how are getting more sophisticated and involve the poaching of engineers, among other things, according to the NSB. As a result, Taiwan continues to strengthen legal and regulatory barriers to prevent technology transfer, illicit recruitment, and espionage network activity from operating in the country.

According to the report, Taiwan's National Security Bureau claims that cyber activity against its sensitive assets remains intense. More than 170 million intrusion attempts against Taiwan's Government Service Network were recorded in the first quarter alone. Military pressure around Taiwan is rising, too. In the first quarter of 2026, more than 420 Chinese aircraft operated near the island, alongside naval forces that carried out 10 coordinated combat-readiness patrols. Those tensions, in addition to the covert operations, recruitment efforts, and illicit trading methods the report describes, will only continue to dog Taiwan as it continues its reign at the leading edge of semiconductor manufacturing.

TSMC is reportedly mulling another round of expansion in the U.S., which will expand its capacity in Arizona to 12 fabs, four advanced packaging facilities, and at least one R&D center, if the recent rumors published by DigiTimes are to be believed. The said round of TSMC's expansion in America will work as a part of the intergovernmental deal between the U.S. and Taiwanese governments under which Taiwanese entities are to invest $500 billion in various American high-tech sectors.

Rumors about TSMC's plans to significantly expand its site near Phoenix, Arizona, have been floating around for some time, but the company has never confirmed them. Back in early March, it was reported that TSMC planned to expand its presence in Arizona to 10 advanced fabs, but DigiTimes now claims that the company is looking forward to building another Gigafab complex adjacent to Fab 21, bringing the number of fabs to 12 and increasing the number of advanced packaging facilities to four. For now, this should be considered a rumor because some numbers do not add up.

TSMC recently acquired approximately 900 acres of land adjacent to its existing 1,100-acre campus, bringing the total area of the site to 2,000 acres, which is comparable to a small town, according to market rumors. The acquisition, along with industry chatter about plans to increase investments in Arizona by another $100 billion, certainly supports the possibility of a major expansion of the Fab 21 and possibly another site in the region. TSMC's existing plan includes building six Fab 21 modules, two advanced packaging facilities, and one R&D facility, up from three Fab 21 modules planned initially.

Unofficial information that TSMC needed to acquire land to build additional Fab 21 phases, two advanced packaging facilities, and an R&D center emerged last fall, so the buyout of an additional 900 acres points to sticking to the existing expansion plan introduced in March 2026.

Furthermore, doubling the number of fab modules in the U.S. from 6 to 12 over the next 5 to 10 years will cost considerably more than $100 billion, as a modern leading-edge 2nm-class logic fab module with a roughly 20,000-wafer starts per month capacity costs roughly $25 billion to $35 billion. Building six or more advanced fab modules (that will probably be capable of 1.4nm or more advanced technologies) will cost considerably more than $100 billion.

While we certainly have to keep in mind that there is no smoke without fire, for now, all the rumors about TSMC's expansions in the U.S. should be taken as rumors. In fact, even if the company has plans to expand its capacity in America due to strategic reasons, it does not look like the company has finalized any plans, which is why all the information that surfaces cannot be accurate.

The global semiconductor foundry market generated a record $320 billion in revenue in 2025, growing 16% year-over-year, according to Counterpoint Research's Foundry Market Supply Tracker published on Monday, March 30. Demand for AI GPUs and custom AI ASICs drove the gains across both advanced manufacturing and advanced packaging, with TSMC accounting for 38% of the total market and growing at more than four times the rate of its nearest competitors.

Counterpoint's figures use an expanded "Foundry 2.0" definition that includes pure-play foundries, non-memory integrated device manufacturers (IDMs), outsourced semiconductor assembly and test (OSAT) companies, and photomask suppliers. Under that framework, pure-play foundries accounted for 54% of revenue and grew 26% YoY, while non-memory IDMs made up 27% and grew just 2%.

TSMC's full-year revenue grew 36% YoY, though quarterly growth moderated to 25% in Q4 2025 from the 40%-plus rates posted earlier in the year. The slowdown reflected a higher comparison base in high-performance computing and typical consumer electronics seasonality.

"The key question is no longer just wafer capacity, but system-level integration," Jake Lai, senior analyst at Counterpoint Research, said. "As front-end scaling becomes more constrained, bottlenecks are increasingly moving to the back end."

Non-TSMC foundries collectively grew a more modest 8% YoY, aside from Chinese foundries, which were the exception. SMIC posted 16% growth, and Nexchip grew 24%, both supported by ongoing localization efforts. Counterpoint expects double-digit growth from Chinese fabs to remain sustainable into 2026.

Samsung had what Counterpoint described as a mixed year, but the firm's analysts see room for improvement. "Demand for its 4nm node has been relatively solid, supporting better pricing, and the ramp of 2nm should help it secure higher-value designs, particularly in AI and mobile," Tom Kang, research director at Counterpoint Research, said.

Intel Foundry held 6% of the total Foundry 2.0 market by revenue, according to Counterpoint's breakdown, placing it alongside Texas Instruments and Infineon among the non-memory IDM segment. Non-memory IDMs largely worked through their inventory corrections in the second half of 2025. Texas Instruments posted a 13% YoY rebound, and Infineon grew 5%.

The OSAT segment grew 10% YoY in 2025 as ASE/SPIL and Amkor absorbed spillover demand from TSMC's constrained internal advanced packaging capacity. ASE grew at an above-average rate and became the second-largest player by revenue in the entire Foundry 2.0 market, behind TSMC. Counterpoint projects that industry-wide advanced packaging capacity could expand by roughly 80% YoY in 2026, driven by AI customers locking in long-term partnerships with OSAT vendors for CoWoS-S and CoWoS-L production.

"Advanced packaging is no longer just a supporting step but becoming a gating factor for AI deployment," said Counterpoint Research senior analyst William Li.

Most of the political ping-pong revolving around the black hole of AI concerns the sale and tariffs of accelerator cards, but there are many other stakes in play. UDM Money is reporting that one of the three landmark cases involving the alleged theft of trade secrets from TSMC has run through investigative and court proceedings, and a verdict is scheduled for April 27.

The case is one of three related indictments pertaining to former TSMC engineer Chen Li-ming, who allegedly orchestrated industrial espionage for Tokyo Electron Taiwan. Li-ming worked in yield management at TSMC and switched jobs to the marketing department at the Japanese firm, where he allegedly coordinated espionage in two separate operations.

The remarkable nature of the cases is due to the Taiwanese courts invoking the National Security Act for the first time in the context of semiconductor manufacturing, first in charging Chen Li-ming and his associates (on two separate counts), and Tokyo Electron itself. If this is all sounding familiar, chances are you're thinking of the separate, ongoing trade secret indictment against Intel engineer Wei-Jen Lo.

The Li-ming case that is about to conclude hails from August 27 and evaluates allegations that, after he joined Tokyo Electron, around 2023, he convinced TSMC engineers Wu Bing-chun and Ko Yi-ping to syphon away key technical information about 2 nm processes. This charge could result in 14 years of prison time for Li-ming, nine years for Bing-Chun, and seven years for Yi-ping. The data stealing was presumably to help Tokyo Electron become a supplier for TSMC.

That's not Li-Ming's only concern, however. A second case that kicked off in January discusses his involvement in getting another TSMC employee, Chen Wei-chieh, to photograph trade secrets regarding 14nm chip technology, with the knowledge of a Tokyo Electron manager with the surname Lu.

This second civil case covers not only the data theft but also the destruction of evidence, as apparently the trio shared their information on a cloud-sharing platform. The prizes for this endeavour could be as severe as seven years for Li-ming, close to nine for Wei-Chieh, and one for Lu. The recent nature of that indictment means that the investigation or court proceedings are still ongoing, and no sentence date has been set.

Taiwan courts seemingly add up sentences for related charges, with a 20-year cap. Given the groundbreaking nature of this case, Li-ming could still be staring down the barrel of two decades in prison. As for Tokyo Electron Taiwan, its own case could cost the company a fairly modest NT$145 million, or about $4.52 million / €3.95 million, for "[failing] to take adequate steps to prevent the illegal acts." The original fine was NT$120 million, but it got a NT$25 million bonus after the most recent indictment.

Although the $20 billion funds injected in Elon Musk's TeraFab project — which is supposed to build logic and memory chips as well as package them under one roof — is barely enough to build a 7nm-class logic fab, Elon Musk's eventual ambitions include producing millions or billions of AI chips that consume 1 terawatt (1 TW) of power per year. This ambition by far exceeds today's industry capacity, and if Musk pursues it, he will need $5 trillion, according to Bernstein, a premier semiconductor analysis firm (via @Jukan05). Interestingly, the order of the sum is similar to what Sam Altman was seeking for his failed fab network a couple of years ago.

To build 1 TW of AI silicon per year, Elon Musk's TeraFab would need to process 22.4 million Rubin Ultra GPU wafers, 2.716 million Vera CPU wafers, and 15.824 million HBM4E wafers annually using from 142 to 358 fabs, according to Bernstein.

The firm gets these figures, which it describes as "a very rough back-of-the-envelope wafer capacity calculation," by using a top-down approach, translating rack-level power demand into required semiconductor manufacturing capacity. Using power consumptions of rack-scale systems (120 kW for Rubin to 600 kW for Rubin Ultra), analysts convert system volumes into chip counts and then into wafer demand using their die sizes, such as ~825 mm² for GPU dies, ~800 mm² for CPU dies, the number of HBM stacks, and yields.

But Bernstein seems to overstate the typical capacity of logic fabs (50,000 wafer starts per month, WSPM, instead of 20,000 WSPM), understates the capacity of DRAM fabs (50,000 WSPM instead of 100,000 – 200,000 WSPM), and assumes prices per fab at $35 million, which likely inflates total estimates even if the multi-trillion-dollar magnitude is generally correct.

Trillions for fabs and packaging facilities

Based on what we know about the modern semiconductor industry, a modern leading-edge logic fab typically delivers around 20,000 WSPM, or roughly 240,000 wafers per year. To produce 25.116 million logic wafers annually, TeraFab would require about 105 fabs at perfect yields, or 126 fabs at 80% yields. A 2nm-class capable fab costs from $25 billion to $35 billion (~$30 billion midpoint), so logic capacity alone would require around $3.15 trillion, assuming a 100% yield and $3.78 billion at 80% yield.

For context, TSMC shipped 15.023 million 300-mm-equivalent wafers in 2025, which includes 200-mm wafers and 300-mm wafers made on outdated process technologies. Also important, TSMC currently operates about 50 300-mm fab modules built over two decades.

Large-scale high-bandwidth memory (HBM) production is also crucially important for achieving Elon Musk's goals for TeraFab. Modern DRAM fabs — run by Micron, Samsung, and SK hynix — typically offer 100,000 to 200,000 WSPM (so, let us take 150,000 WSPM as the midpoint). Producing 15.824 million HBM4E wafers would require about 9 fabs at 100% yield, or ~12 fabs at 70% yield. Each of these fabs costs at least $20 billion, or roughly $240 billion for front-end memory capacity alone. However, HBM output is constrained by stacking and packaging capabilities and yields, not only by the output of DRAM devices. For comparison, the three major DRAM makers currently operate only ~30 fab modules built since the early 2000s.

Advanced packaging facilities used for 2.5D and 3D integration, as well as HBM assembly, cost around $2 billion to $3.5 billion per phase, and TeraFab would require tens or even hundreds of such facilities to assemble AI processors and HBM stacks, which means hundreds of billions of dollars in additional investment.

Altogether, TeraFab would require well north of $4 trillion, which generally aligns with Bernstein's $5 trillion estimate, excluding land, process R&D, software, and ecosystem development.

Constraints beyond money

Raising $5 trillion would be extraordinarily difficult. For context, companies like Nvidia, Apple, and Alphabet have market capitalizations of $4.34 trillion, $3.71 trillion, and $3.5 trillion, respectively, so Musk would need to mobilize capital exceeding the value of the world's most valuable corporations. It is hard to imagine a private fundraising round, consortium, or even sovereign funding of this magnitude. For example, even if the U.S. would like to fund Musk's semiconductor venture, it could not do this that easily, as its budget for this year is about $7 trillion.

The only conceivable path would involve multi-government backing, sovereign wealth funds, hyperscalers, and capital markets acting in concert. However, we doubt this is possible at all. Furthermore, at a scale of $5 trillion deployed within a foreseeable timeframe, constraints would extend beyond capital and would include limited availability of wafer fabrication equipment, construction materials, and a sufficiently large and skilled workforce to build, operate, and maintain such fabs.

Then again, does Musk really plan to build a foundry that would leave behind TSMC, Samsung, and Intel combined just to make enough chips for Tesla, SpaceX, and xAI? Well, this is an open question.

Elon Musk spent quite some time last fall complaining that existing foundries cannot meet his company's demand for high-performance AI processors and proposed an idea to build his own chipmaking venture. Apparently, this was not just a brag but rather an announcement of a long-term project. Now the project has gotten its launch date: March 21, 2026.

"Terafab Project launches in 7 days," Elon Musk wrote in an X post.

He did not elaborate on any details about the project, though his previous comments indicated that this is indeed a long-lasting semiconductor production facility project that would enable his companies — Tesla, SpaceX, and xAI — to get enough supply of AI accelerators.

Musk once mentioned that his companies might need 100 – 200 billion AI chips per year, and if it cannot get them from existing foundry partners, then the company will consider building its own fabs. Apparently, the Terafab Project seems to be the brand depicting the endeavor and scale, though it does not provide any reasonable portrayal of the nature of the project.

Speaking in an interview with Moonshots, Elon Musk argued that the semiconductor industry may be approaching cleanroom design incorrectly. Instead of keeping entire buildings ultra-clean, Musk suggested that fabs should focus on isolating silicon wafers themselves throughout the manufacturing flow, keeping them sealed from the surrounding environment at all times. He surmised that would allow him to eat cheesburgers in the cleanroom while chips were being made.

Rebuilding the whole supply chain for such fabs would take the industry a couple of decades, to say the least. For this, Musk argued that his planning horizon is closer to one to two years, and he rarely looks beyond three years, which makes the traditional semiconductor buildout cycle incompatible with his projected demand.

He added back then that if foundries could accelerate expansion and supply 100 billion to 200 billion AI chips per year within Tesla’s required timeframe, the company would gladly rely on external manufacturing instead of pursuing its own facilities.

Apparently, we are going to see details about the project in a week. The again who launces a multi-billion project on Saturday? This is what we are going to see next Saturday!

Following a rabid weekend of tariff rulings and press conferences, the Trump administration has settled on a blanket 15% tariff for basically all goods entering the United States. This has upended global trade as countries look to confirm their final rates, with many of them having previously negotiated different rates - some higher than 15%, some lower. While Bloomberg suggests China is a big winner of the redrawing of tariff percentages, it also threatens to hand companies like TSMC a big win by negatively impacting U.S. chip companies like Nvidia and Intel.

Pledges and promises

One of the second Trump Administration's main goals has been in what it views as a necessary rebalancing of global trade. A big part of that has been to encourage companies to bring their manufacturing facilities to the United States, particularly high-tech chip manufacturers.

Alongside investing in companies like Intel, the U.S. government has used trade blocks and tariffs to push for companies like TSMC and Micron to open up new manufacturing facilities in America. If they do, they get discounts on their tariff rates. A major part of recent discussions between the U.S. and Taiwan (and particularly TSMC) was in securing a favorable tariff exemption, in exchange for further investment in American manufacturing facilities. The agreed-upon figure was 15%, though the details were scant. However, the prevailing sentiment was that with enough investment, tariffs might disappear entirely for a select few.

TSMC's announcement earlier this month that it could invest a further $100 billion in advanced manufacturing in Arizona was with the idea of taking advantage of a potential zero-tariff loophole. Companies looking to manufacture chips in the U.S. could import up to 2.5 times the manufacturing capacity of planned facilities, and up to 1.5 times the manufacturing capacity once the facility begins production.

In late 2025, TSMC accelerated plans to bring its latest manufacturing facilities to the U.S. as a major show of solidarity with the Trump administration's goals.

That's all been thrown out the window as of this weekend's Supreme Court ruling and subsequent announcements. But if 15% was what Taiwan had gained for its efforts, and now it faces 15% regardless, it may have been given a golden opportunity. It may be able to leverage existing agreements and investment plans to secure a better-than 15% rate for its products, or it could drop them entirely and still likely only face the same 15% maximum tariff rate as everyone else.

And better yet, whichever avenue companies like TSMC go down, they'll have an advantage over American firms doing the same.

Building here still means importing here

The vast majority of the world's most advanced semiconductor manufacturing happens in Taiwan, but the Trump administration has made a major play to bring some of that to U.S. shores, even claiming to want as much as 40% of TSMC's total manufacturing to be based in America in the future — something that TSMC has said is impossible.

But it has secured massive new manufacturing investments from international firms like TSMC, Micron, and others, as well as investing domestically in Intel. It's also thrown up major trade blocks to limit other countries' (particularly China) access to the latest AI accelerators and the equipment used to make leading-edge nodes.

These latest trade tariffs do nothing to help America or American businesses, though. In what is either a continued misunderstanding or a gaslighting attempt by the Trump administration, foreign companies do not pay the tariffs when goods are imported; the importing companies do.

That means for companies looking to import chips from TSMC, they'll have to pay that 15% fee, not TSMC. For companies looking to manufacture chips in America, they're still reliant on key raw materials for chip manufacturing. Broad tariffs raising the cost base for everything imported into America means raising prices on those key materials, in turn making U.S.-based chip manufacturing more expensive for everyone involved.

This comes at a poor time for Intel, which is hoping to bring its cutting-edge facilities online as fast as possible. Its planned Fabs have potential chip complexity and yield advantages over even some of TSMC's best facilities, though they have yet to start production. Increasing the costs of these raw materials and further squeezing supply chains is not ideal for such a venture.

A lack of clarity

Nothing is clear about these new tariffs, and there's a distinct possibility that they don't apply to semiconductors and electronics, or at least, aren't designed to.

The new tariffs are being brought in as part of Section 122 of the U.S Trade Act of 1974, which gives the executive branch limited and temporary ability to apply tariffs to imported goods. But as the Singaporean Ministry of Trade highlights, some products should be excluded from this Section.

"Certain types of goods are exempted from the Section 122 tariffs, such as energy and energy products, pharmaceuticals and pharmaceutical ingredients, certain electronics, certain aerospace products and metals used in currency and bullion, amongst others," it said in a statement over the weekend. "In addition, semiconductors and pharmaceuticals are not subject to the Section 122 tariffs, as they may be the subject of Section 232 tariffs that have not yet been imposed."

However, as White Case LLP highlighted in January, the Trump administration has already leveraged Section 232 for 25% tariffs on a limited selection of semiconductors imported into America. Those tariffs could easily be expanded with the legal justification that it's for matters of national security. Trump has previously used similar justifications to limit imports of Steel and Aluminum during his first term.

Uncertainty prevails

Although somewhat expected, the U.S. Supreme Court's ruling has thrown the Trump administration into chaos, and it has responded in kind. The new tariffs are sweeping, confusing, and very temporary, at least for now. It throws into question all existing deals, which were less foundationally secure than traditional trade agreements anyway.

In the near term, though, it's looking like some of the greatest beneficiaries of America's further turn inwards towards self-sufficiency may be helping anyone and everyone but America itself.

As part of the recently concluded trade arrangement between the U.S. and Taiwan, Taiwanese companies including TSMC will invest $250 billion in the U.S. in exchange for exemptions from potential chip tariffs, Financial Times reports.

Limited disclosure around the terms of this commitment has introduced major uncertainties regarding TSMC's future capital spending, manufacturing allocation, and long-term strategy, however. And meanwhile, a market rumor suggests that TSMC may invest an additional $100 billion in its U.S. facilities, bringing its total commitments to $265 billion — and making TSMC one of the biggest ever investors in America.

The $250 billion figure largely reflects previously announced plans, and TSMC is projected to be the biggest spender. The company has already committed $165 billion to its Fab 21 campus in Arizona, which includes six fab modules, two advanced packaging facilities, and a research and development center. According to U.S. commerce secretary Howard Lutnick, roughly $100 billion of TSMC’s existing commitments are included in the investment total, and TSMC's supply chain partners are projected to contribute about $30 billion.

According to market rumors, TSMC may invest an additional $100 billion to construct four more fab modules in Arizona in a bid to avoid tariffs. TSMC's recent acquisition of approximately 900 acres of land adjacent to its existing 1,100-acre site supports the possibility of expansion on that scale.

Other Taiwanese companies, including Foxconn, are expanding U.S. capacity to assemble AI servers, though these projects are considerably less capital-intensive and are expected to total no more than $20 billion, according to Financial Times.

The arrangement reportedly allows companies building U.S. facilities to import chips tariff-free at up to 2.5 times the planned capacity during construction, followed by a reduced quota equivalent to 1.5 times capacity once production begins, Financial Times reports. Analysts say that once the new fabs finish construction, the temporary rule allowing higher tariff-free import volumes will expire. After 2032, this could leave TSMC without enough U.S. capacity to keep all shipments to American customers exempt from tariffs, which is why the company may need to build additional fabs by around 2035 to maintain full tariff-free coverage, according to Financial Times.

Even if the Arizona complex ultimately reaches its theoretical capacity — 10 fab modules, at least two advanced packaging facilities, and an R&D center — TSMC's presence in the U.S. is poised to remain considerably smaller than its operations in Taiwan. For now, TSMC estimates that up to 30% of its chips on N2 (2nm-class) and more advanced process technologies will be made in America. Taiwanese officials have rejected suggestions that 40% - 50% of semiconductor production on the island could shift overseas, particularly to the U.S.

It should be noted that only $8.2 billion of Taiwan’s $198 billion in exports to the U.S. in 2025 consisted of standalone semiconductors. Most chips made in Taiwan enter the U.S. being installed into finished goods spanning from smartphones to AI servers, which greatly complicates tariff enforcement as importers may struggle to identify or report the value of individual chips. As a result, many observers wonder whether such tariffs could be practically collected.

Following the announcement of impending chip import tariffs in January, the Trump Administration is now planning to offer major U.S. tech companies like Google, Microsoft, and Amazon the ability to circumvent them. However, the number of TSMC-made chips exempt from the tariffs may be directly tied to the Taiwanese chipmaker's scale of investment in American operations.

This follows recent trade negotiations between the U.S. and Taiwan, where the Trump Administration agreed to cut tariffs on imports from the island to 15 percent from 20 percent, but that was contingent on Taiwanese companies investing $250 billion in the American chip industry, specifically chip fabrication on U.S. shores.

With TSMC as Taiwan's (and the world's) premier cutting-edge semiconductor manufacturer, the bulk of this investment will need to come from its coffers. According to Financial Times' sources, the scale of those U.S. investments still requires significant work to plan out, and the tariff exemption rules are just another wrinkle for the company to work out.

“We’re going to be monitoring what unfolds after this is unveiled like hawks to make sure that the integrity of what we’re trying to accomplish with the tariffs and the rebates isn’t undermined and that this doesn’t end up being a giveaway to TSMC,” an official told the Financial Times.

In recent days, TSMC has made it clear that, as much as the Trump Administration would like it, there's no way it can get its American production capacity up to 40% of its total output.

Bringing it home

Amidst the seemingly chaotic international policies and trade negotiation tactics of the Trump administration, one thread has run through it all with some consistency: It wants cutting-edge chip manufacturing to be located on American soil. Although President Trump has acted as a vanguard for this kind of approach to silicon supply chains and immediate, localized access to fabrication, the reshoring of chipmaking efforts isn't singularly tied to American interests. We've seen China develop competitive AI accelerators, and the EU heavily investing in its own initiatives.

In the wake of the enormous AI infrastructure boom in mid-2025, many countries around the world have focused on building up their own national infrastructure and access to semiconductors, both leading-edge and older, more specialized chips. As it's become clearer that the future of many economies and national security itself relies on a ready supply of fast, efficient silicon, bringing the manufacture of that hardware in-house has a long list of advantages.

In America, this has led to aggressive trade talks with China, as both countries flexed their respective muscle - for the U.S., high-end GPU exports. For China, raw materials like rare earth minerals. This is all in an effort to secure the firmest of footing in this new race for AI and semiconductor dominance. Although in 2026 trade has opened up a little with export licenses and profit-sharing initiatives, the real fallout is China massively boosting its development of inference GPUs and ASICs, and the U.S. looking to increase stockpiles of critical rare earth minerals.

It's also led to the Trump Administration looking to accelerate its own domestic chip industry. With so much of the world's expertise and chip fabrication facilities located in Taiwan, a major focus of the White House's aims has been to encourage TSMC and its contemporaries to build in America.

Along with other companies, TSMC is now doing that and on a grand scale. But the specific size of the investment, and these latest tariff carve-out carrots, are nebulously complex.

Cautious, massive expansion

In the recent Taiwan-U.S. trade deal, America agreed to cut import tariffs from Taiwan to 15% in exchange for Taiwanese companies investing $250 billion in the American chip industry. Specifically, it will allow them to import 2.5 times the new facilities' planned capacity tariff-free, during the construction period. Companies that have already built capacity in America will receive 1.5 times those facilities' capacity in tariff exemptions.

The idea is that TSMC and other Taiwanese firms that invest in the U.S. will allocate their tariff-exempt chips to hyperscaler AI companies like Google, Microsoft, Amazon, and Meta. But since the math on the investment scale and how that relates to chip allocations is so hazy, there are still many details to be worked out. Much of it depends on what kind of fabrication capacity TSMC can project it will reach within the next two years.

To date, TSMC has pledged to invest $165 billion in building chip fabrication capacity in America. It is reportedly quite nervous about further expansion, considering the fears of an AI bubble, and the U.S. government's own investment in TSMC competition, like Intel. If demand for chip fabrication falls dramatically in a year or two because of a change in the winds of global development, TSMC could be left with unneeded production capacity that isn't even online yet, in a similar fashion to memory suppliers a few years ago following the pandemic boom.

TSMC and other Taiwanese chip firms are now towing a similar line to major U.S. companies and international governments on working with the current White House team. Engaging with complex trade practices is an important component of maintaining strong financial and trade opportunities in the near term. But the weaker long-term strategic thinking of the Trump administration risks dragging down any firms that rely too heavily on its coercive suggestions on longer-term planning.

Although major U.S. investment is coming, TSMC may need to tread carefully to avoid falling afoul of the risks on either side of the equation.

The artificial intelligence supercycle is reshaping the semiconductor and electronics industries, as the scale of the AI infrastructure buildout strains the entire supply chain. While developers of AI accelerators like Nvidia are cashing in on the AI boom, it's memory makers that will earn the most cash, according to estimates from TrendForce. Arguably, this is a result of the different business models and expansion strategies memory makers use compared to foundries, in addition to the behavior of the commodity market.

Demand outstrips supply

The company projects that while global foundry revenue is expected to total $218.7 billion, 3D NAND and DRAM revenue will reach $551.6 billion, which means that the total market for memory is more than twice as large as contract chip production. TrendForce attributes this to structural market changes caused by AI buildouts. The latter creates elevated demand for specific types of memory, creating shortages of all types of memory, and therefore affecting prices across the industry. As a consequence, while the AI industry does not need low-capacity commodity memory devices, they also become substantially more expensive amid tight supply. This creates the perfect conditions for memory makers to capitalize upon.

Indeed, the spot price of a 16 Gb DDR5 chip at DRAMeXchange was $38 on average, with a daily high of $53 and a daily low of $25. By contrast, the very same chip used to cost $4.75 on average just one year ago ($3.70 session low, $6.60 session high). Similar changes occurred to the prices of 3D NAND memory in recent quarters.

Fundamental differences

Just like some other analyst firms, TrendForce calls the AI megatrend a 'supercycle,' indicating its overwhelming ubiquity, which affects multiple industries, and its potential length.

There were two periods in the last few decades when revenue of memory makers grew significantly year-over-year for two years in a row: in 2017 – 2018, when hyperscalers built their vast data centers (+62% in 2017 and +27% in 2018), and in 2020 – 2021, when people increased purchases of PCs amid the COVID-19 pandemic. In both cases, memory makers increased capacity to meet demand and maintain their market share, which caused sharp drops in revenue back in 2019 and 2022.

The foundry industry — which is much more capital-intensive than the 3D NAND or DRAM industries — uses fabs that are harder and longer to build, and only suffered a year-over-year revenue decline in 2023.

The situation today is vastly different. On the one hand, leading developers of frontier AI models need the most powerful clusters to train their models, therefore creating demand for leading-edge hardware with expensive HBM3E memory and plenty of storage. On the other hand, these companies and their clients need more powerful inference systems to use those models. Therefore, demand for CPUs, AI accelerators, memory, and storage does not decline over time. Meanwhile, buyers like cloud service providers (CSPs) tend to be less sensitive to price increases, which is why 3D NAND and DRAM suppliers are expected to raise average selling prices more aggressively than in the past cycles.

Foundry vs. Commodity

3D NAND and DRAM are commodities, so their prices behave like prices of commodities, almost immediately reacting to tightening supply, increasing demand, or sentiment among buyers. While large PC makers purchase their memory at prices agreed upon every six months, a significant portion of memory is sold on the spot market.

This dynamic is reflected in TrendForce's projections that show memory revenue growth accelerating after the downturn of 2022 – 2023, including an expected 80% increase in 2024, followed by 46% growth in 2025, and a projected 134% surge in 2026.

By contrast, foundries tend to operate under long-term agreements that smooth price fluctuations, which prevents sharp swings that characterize memory markets. Even during periods of strong demand, foundry pricing adjustments occur gradually, which means slower revenue growth compared to memory vendors.

TrendForce models that following a 19% year-over-year revenue increase in 2024, the foundry market grew 25% in 2025 and will grow another 25% this year.

As a result, boosted by the AI supercycle and not constrained by long-term agreements, memory vendors will earn more than two times more this year alone compared to producers of logic, which have to adhere to their long-term contracts.

The biggest question

With HBM4 memory devices using four times more silicon than typical DRAM ICs, it is obvious that memory makers cannot meet all the demand that exists because of insufficient capacity, which results in price adjustments. However, the biggest question is how significantly current commodity 3D NAND and DRAM prices are influenced by insufficient supply, and how significantly they are influenced by typical commodity memory market behavior that dictates that customers buy more memory when it is getting more expensive, as it may get even more expensive in the future?

The U.S. Department of Commerce is reportedly planning tariff carve-outs for AI hyperscalers within the country, including Amazon, Google, and Microsoft, among others. According to the Financial Times, the move will allow these companies to acquire the chips they need to remain competitive in the AI race, while still pushing chip makers like Taiwan Semiconductor Manufacturing Company (TSMC) to continue investing in the U.S.

Taiwan and the U.S. agreed on a trade deal last month, with Washington cutting tariffs on the island from 20% to 15% in exchange for a $250-billion commitment on direct investments, plus another $250 billion in credit guarantees from Taipei to allow its companies to invest in the American semiconductor industry. The 15% tariff is set to include chips made on the island, but Taiwanese companies building fabs in the U.S. will get an exemption.

These chip manufacturers can import two and a half times their fab’s planned capacity tariff-free while their plants are under construction. That number would then fall to just 1.5 times once they start churning out semiconductors locally. TSMC is expected to allocate its exemptions to its Big Tech clients that are ordering huge numbers of AI chips, but the total quantity of tariff-free chips will still depend on the company’s investments in the U.S.

At the moment, TSMC has already committed to invest $165 billion in the U.S., with one fab already operational in Arizona. Despite this, a source told the Financial Times that U.S. President Donald Trump is delaying the signing of the agreement. “We’re going to be monitoring what unfolds after this is unveiled like hawks to make sure that the integrity of what we’re trying to accomplish with the tariffs and the rebates isn’t undermined and that this doesn’t end up being a giveaway to TSMC,” the administration official said.

On the other hand, the TSMC board recently announced a $45 billion spending package on new fabs. This is a massive change for the company, which usually spreads out its capital appropriation throughout the year. This recent move instead saw a huge chunk of the chip maker’s planned $52 to $56-billion budget for capital expenditure allocated in the first quarter of 2026. It’s unclear how much of this will be spent on American fabs, though. Although Taiwan rejected the possibility of moving 40% of its semiconductor capacity inside the U.S.’s borders, it said that the production capacity of both local and American chip production is expected to scale hand-in-hand as the AI infrastructure build-out continues, driving record demand for the latest chips.

TSMC on Tuesday held a board meeting where it, among other things, approved plans to spend $44.962 billion on building new fabs and upgrading existing production capacities. The approval is a part of the company's general plan to spend between $52 billion and $56 billion on capital expenditures this year, with the rest of the funding to be approved at a later meeting. In addition, the company promoted a developer of its 1nm-class process technology.

A record spending approval

TSMC holds board meetings — where it approves things like capital appropriations, capital injections, or distribution of dividends — every quarter. However, the company usually attempts to approve its CapEx appropriations more or less evenly throughout the years. For example, last year the board approved spending of $17.141 billion in Q1, $15.247 billion in Q2, $20.657 billion in Q3, and $14.981 billion in Q4, with some of the funds to be spent in 2026 or even later. Approval of a plan to spend $44.962 billion is a record one and indicates that the company is getting more aggressive with its expansion, as well as its projects getting more costly, which is in line with the general industrial trend for fabs to get more expensive.

It should be noted that approvals of capital appropriations are not indicators of actual spending, but these are allowances for management to spend them on certain projects, which may or may not be parts of the ongoing fiscal year's CapEx. Yet, as TSMC's CapEx budgets are increasing year-over-year, so are capital appropriations.

Earlier this year, TSMC announced plans to spend between $52 billion and $56 billion on all-new manufacturing capacities, upgrading existing fabs, and building advanced packaging facilities. The contract chipmaker plans to spend between 70% and 80% of its 2026 CapEx on advanced process technologies, between 10% and 20% of the budget on advanced packaging and mask making, as well as approximately 10% on specialty technologies.

Accelerated spending on advanced fabs is designed to make TSMC unbeatable to Intel and Samsung Foundry when it comes to availability of the state-of-the-art production capacities. If the company has considerably more capacity than its rivals, it will be more likely to land big orders from big customers. If TSMC has slightly more capacity than its clients need, then the latter will unlikely outsource even a part of their production to competitors.

Lead A10 developer gets promoted

Another notable happening at the meeting is the promotion of S.S. Lin — who is currently senior director at TSMC's research and development organization responsible for the development of the company's A10 process technologies (1nm-class) — to a vice president status.

The promotion is likely a sign that the upper management is satisfied with where the A10 platform development is going and the preliminary results that have been achieved so far. The promotion may also mean that as a VP, S.S. Lin will be able to oversee more technology programs than a single (yet very important) process node as well as have greater influence over roadmap goals, priorities, and resource allocation, though we are speculating. Also, as the A10 program is moving from research and development towards finalization and adoption by partners and customers, the program leader may need to have more power to execute their goals.

A10 is TSMC's post-A14 fabrication process expected to be available to its clients sometimes in 2030 or later. The company expects A10 to enable it to make monolithic chips with over 200 billion transistors at the time. Some believe that TSMC plans to start using High-NA EUV lithography tools with its A10 node.

Taiwan's government has rejected calls from U.S. officials to shift a large portion of semiconductor manufacturing to America, stating that relocating 40% of the island's chip production is not feasible, reports Reuters. The authorities expect companies like TSMC and UMC to keep expanding their production capacity on the island, even though TSMC is now actively expanding overseas and other countries are looking for the onshoring of chipmaking.

Vice Premier Cheng Li-chiun said in an interview with Taiwanese television station CTS that she had clearly told the U.S. government that Taiwan's semiconductor ecosystem cannot simply be transferred elsewhere. The semiconductor sector will continue expanding domestically, while overseas investments — including those that TSMC makes in its U.S. production capacity — will proceed only alongside continued growth at home.

According to Cheng, Taiwan's overall semiconductor capacity — including existing fabs as well as future projects — is expected to exceed investments made in the United States or any other country.

The comments are a response to the recent statements by U.S. Commerce Secretary Howard Lutnick, who said that concentrating a large portion of global semiconductor production close to China represented a strategic vulnerability. He also indicated that the goal of the U.S. government is to increase the country's share of the market of leading-edge semiconductor manufacturing to 40% in three years, by the end of President Trump's current term.

How that can be possible, given the fact that it takes three years to build a fab in the U.S. and then about a year to ramp it, is something Lutnick did not disclose. Yet he warned that if such goals are not achieved, tariffs on Taiwan-made goods could potentially increase to as much as 100%.

In earlier remarks, Lutnick also described a scenario in which leading-edge semiconductor production could be split roughly evenly between Taiwan and the United States, which indicates that the U.S. government has a fairly flexible position when it comes to actual market share numbers.

By contrast, Taiwanese officials reiterated that there are no plans to relocate the island's science parks, which form the core of its semiconductor manufacturing ecosystem, and are indispensable parts of the country's so-called silicon shield. Nonetheless, Taiwan authorities have no problems with TSMC expanding overseas as long as its most advanced technologies remain in Taiwan.

Among semiconductor companies, Intel has always been the biggest one both in terms of revenue and in terms of headcount. However, following massive layoffs at Intel in recent years, TSMC has by now outpaced Intel as the world’s biggest semiconductor employer. While Intel is still an exceptionally huge semiconductor company that employs more people than AMD, Nvidia, and Arm combined, the moment when TSMC becomes bigger than Intel from a headcount point of view represents a milestone for the industry.

85,100 employees after years of cuts

Intel employed 85,100 people as of December 27, 2025, following substantial job cuts at Intel in 2024 and colossal job cuts in 2025. TSMC had 83,825 full-time employees serving in various capacities as of December 31, 2024, following years of aggressive hiring amid expansions overseas as well as building out new production capacity in Taiwan. As of December 31, 2025, TSMC employed 90,557 people, according to its Annual Report the company published this week, which is nearly 7,000 full-time employees more than a year before, therefore surpassing Intel as the biggest employer in the semiconductor industry.

To put the numbers into context, AMD had approximately 31,000 of full-time employees (FTE) in the end of 2025, Nvidia employed around 36,000 people full time at the end of its fiscal 2025 (i.e., calendar 2024), Qualcomm had about 52,000 employees on its payroll as of September, 2025, Apple exited its fiscal year 2025 with 166,000 full-time equivalent employees, whereas Arm had roughly 8,330 FTEs as of March 31, 2025. All of these companies have been hiring aggressively in recent years as they have benefited greatly from the increased demand for semiconductors amid the AI and cloud data centers expansions. This makes Intel one of a few semiconductor companies that have been aggressively reducing their headcount in 2024 – 2025.

It should be noted that comparing Intel to other companies in the industry is not exactly an apples-to-apples comparison. Intel is among a few remaining integrated design manufacturers (IDMs) and is the only IDM that still produces chips on a leading-edge process technology in-house. By contrast, TSMC is the world's largest contract chipmaker that certainly runs more fabs and packaging facilities than Intel at this point, so the number of its employees shows how vast its manufacturing operations are. Yet, TSMC does not develop its own products. AMD, Apple, Nvidia, and Qualcomm develop very competitive products, but they do not conduct any in-house manufacturing, so they do not have appropriate personnel.

One may argue that Intel employs way too many people in terms of such metrics as revenue per employee. That being said, Intel maintains and operates multiple fabs and packaging facilities across the world (something none of its direct rivals do these days, except TSMC); it has vast R&D operation as it develops process technologies (again, only TSMC does it among its rivals), it designs multiple products, and it also happens to develop technologies that become industry standards. Although Nvidia designs vertically integrated data center platforms, whereas AMD tends to adhere to industry standards, Intel does plenty of fundamental work behind things like DDR, PCIe, USB, and Thunderbolt, just to mention a few technologies.

Intel still spends more than AMD and TSMC on R&D

Intel's spending on research and development (R&D) illustrates how many projects the company handles at once, both on the foundry and on the products side. Even after a sharp cut of R&D expenses in fiscal 2025, Intel spent $13.8 billion on R&D, which is more than AMD, TSMC, Qualcomm, or TSMC did. Nvidia yet has to report its FY2026 results — which roughly correspond to calendar 2025 — and while it will likely leave Intel behind, this will be the first time ever. Of course, the company has been outspent by Apple since 2018, but Apple spends a lot on development of actual products, so this is again not an apples-to-apples comparison.

For obvious reasons, after cutting approximately 40 thousand positions in two years, it is hard to expect Intel to keep R&D investments at its 2025 level. Along with people, dozens of projects have either been shut down or merged with others, so the company's R&D expenses will be reduced further in 2026. At this point, we can only wonder whether Intel's R&D budget for this year will match that of AMD and TSMC, or will still remain ahead of both companies.

To some degree, R&D spending is a good benchmark that shows the financial health of the company. However, it also gives an idea of where the company is going in the next three to five years. In Intel's case, it must spend on the development of products that will be competitive with those from AMD, Nvidia, and Qualcomm in the latter half of the decade and early next decade. It must also spend on next-generation process technologies to stay competitive with TSMC.

Therefore, in the best-case scenario, Intel must spend more than AMD, Nvidia, Qualcomm, and TSMC combined — like it used to do in 2014 – 2019 — to stay ahead of everyone. However, given the current situation (after Intel exited 5G, modem, 3D NAND, Optane, servers, and many other businesses), the company's R&D budget must be comparable to the combined R&D spending by AMD and TSMC, its two key rivals in the products and foundry realms. If Intel cannot properly fund R&D for its products and semiconductor production operations, it only remains to be seen whether the company retains its relevancy in the late 2020s and the early 2030s.

The voracious appetite of the generative AI revolution has overhauled any number of industries so far in its three-year history. First, it upended demand for high-end chips, pushing companies like Nvidia to record high valuations and putting pressure on all parts of the manufacturing process to churn out chips to meet that need. Then it began to make power grids break and buckle, requiring the need for a rethink about how we send energy to data centers. And those data centers are also facing the strain as they’re needed more often for AI training and inference, even eking out extra demand for commodities like copper that are integral to their operations.

Those data centers need to respond to that demand for more capacity and the challenges of copper shortages, argues Vaysh Kewada, CEO and co-founder at Salience Labs, a silicon-photonics company focused on networking bottlenecks in AI data centers. The bigger and more intensive AI models that continue to roll out, alongside the shift away from chatbots to agentic AI, are pushing those within the sector towards photonics.

“We're targeting the scale up domain of AI data centers, where we're seeing that they're increasingly limited by not just the bandwidth, but the latency of predictability, especially as we scale to larger workloads and agentic workloads,” she said in an interview with Tom’s Hardware Premium. For that reason, “there’s a lot of attention at the moment around photonics.”

Others agree: 2026 is “the year of increasing visibility into design wins and building momentum for silicon photonics,” wrote Aaron Rakers, equity analyst at Wells Fargo Securities, in a recent research note. Wells Fargo estimates that the total addressable market for photonics could end up being $10-12 billion by 2030, thanks to the industry’s shift to bigger capacity.

That sounds like good news, but it comes with a catch. Behind the bullish forecasts, those within the photonics industry warn that, like all those sectors that have been eaten up and spat out before, the next set of constraints, including reliability, packaging, manufacturing capacity, and how data is actually routed once it hits fibre, could become the next hard limit on AI scaling.

Data is the new choke point

The boom in photonics might come as a surprise to some. “Photonics is something that already exists within the data centre today,” said Vivek Raghunathan, CEO and co-founder at Xscape Photonics, in an interview with Tom’s Hardware Premium. “Optical cables and the silicon photonics technology already exist when it comes to connecting different switches as part of a pluggable transfer ecosystem.”

But now that section of optics is being pushed out of there and into ultra-fast links that link large numbers of GPUs into a single compute fabric. “Ultimately, the network is the bottleneck for these workloads, because they're just far too large to run on a single GPU,” Kewada said.

Using photonics means you can get between 10 and 100 times more information back and forth from the memory before they output a single stream of reference, Raghunathan explained. That’s important because what AI systems do now is changing, requiring that extra information shifting. The average AI user is moving from asking single prompts of a model to running chains of tasks, and Kewada said that the hardware is already struggling under current AI use. “If it’s a problem now, it becomes an even bigger problem when it comes to agentic workloads, and that's heavily latency- and balance-sensitive,” she explained.

Photonics also matters because “fundamentally, the current copper-based interconnects just cannot meet that bandwidth requirement,” explained Raghunathan. He warns that “the current approach is going to break down sooner than later.” The solution is the photonics approach, where you can “squeeze a lot of bandwidth in a single strand of fiber, which is extremely small,” Raghunathan added. Kewada points out that dedicated AI data centers want to move from 200‑gigabit‑per‑second (Gb/s) links to 400 Gb/s links as AI clusters behave less like traditional IT and more like large distributed machines.

The photonics push inside AI data centres is increasingly being shaped by TSMC. Its COUPE (Compact Universal Photonic Engine) platform has become a key reference point for integrating photonic and electronic circuits on a wafer, following rumors, years beforehand, with an eventual unveiling at SEMICON in Taiwan in September 2025, and first mocked up in December. Other companies, including Marvell, Broadcom, and Nvidia, are all also engaged in the sector, with Nvidia helping define the performance requirements that become standards by default.

But Nvidia isn’t the only voice in the space. Broadcom has been leading the debate on co-packaged optics (CPO), betting that moving optics closer to silicon is the only realistic way to get past copper’s limits when scaled up. Marvell has also pushed photonics-heavy designs in bigger AI clusters, as well as spending cash on investments, including buying photonics startup Celestial AI for up to $5.5 billion.

Tackling the routing problem

Most of the focus has recently been on solving the problems of getting optics away from chip switches and onto fiber. But once the data is there, it still has to be routed around a cluster. “All billions of dollars has been spent onto the I/O, but less has been thought about of what you do once the data is there,” Kewada said.

Salience Labs is betting on optical circuit switching. “Rather than it being an OEO [optical-electrical-optical] switch, it's a purely optical switch; we're never transforming that data into the electronic domain,” Kewada explained. That matters because every optical-to-electrical-to-optical hop costs power and, crucially for AI, adds delay. The company is seeing huge interest from those trying to scale up to meet the current needs of AI.

But there’s a broader problem within the photonics sector. “I would say that it is mentally ready for it, but practically not ready for it,” Raghunathan explained.

Part of the issue is in capacity. Many photonics components rely on III-V semiconductors (compound semiconductors made from the associated groups in the periodic table), which aren’t produced in the same numbers as mainstream silicon. Raw materials supply is also tight, said Kewada. And that’s before you get to packaging. “This requires sub-micron alignment,” Raghunathan said. “They are typically glued onto that die. So now the industry has started thinking about, how do I make that interface detachable?” It’s one of many questions the industry is being asked — and asking itself — to address the challenges ahead.

The push towards photonics feels inevitable, but just because it’s inevitable, it doesn’t mean the sector is ready. Manufacturing scale, raw materials, packaging, and reliability are still unanswered issues. And if the industry doesn’t get ahead of those constraints, it risks replaying the same shortages it has already lived through with chips, copper, and power — but this time the choke point could be the network itself. “The volume here is going to be two orders of magnitude higher than what the industry has seen so far,” said Raghunathan. “The entire optics industry has never seen such a volume ever before.”

It's something on the mind of Kewada, too. “We’re in for some interesting times if we see the attention on photonics continue to grow, and especially for next-generation bandwidth,” she said, “if people look towards larger-scale deployment.”

On January 15, Taiwan and the United States of America signed a significant trade deal. On its side, Taiwan earmarked a total of $500 billion for investment in the U.S. semiconductor industry. In exchange, the U.S. dropped its tariff rate on Taiwanese goods from 20% to 15% and allowed for limited duty-free exports for chip companies investing in stateside soil, among other benefits.

The deal has been inked but is pending ratification from the Taiwanese Executive Yuan, and those $500 billion are split between $250 billion in private investment and $250 billion in lines of credit from the Taiwanese government to chipmakers wanting to invest stateside.

The documents don't make any specific mention, but the exchange is mostly about TSMC, the company that manufactures about 90% of the world's advanced chips (5 nm and below), and fabricates almost every AI and smartphone chip of relevance. The firm, and by extension its nation, is currently the only shop if you want a high-end computer chip made, particularly if said unit needs 2 nm transistors.

Tricky geopolitics

The geopolitics involved are easily described but tricky to navigate: nearby China has long had aspirations to embrace Taiwan into its fold, but North-American companies represent 75% of TSMC's revenue. Plus, it's the only company mass-producing cutting-edge chips for the entire world. This situation is thus described as Taiwan's "silicon shield," and many believe it's the only reason why China hasn't taken over.

As for the United States, the nation has long wanted to curb its nearly exclusive reliance on an external source for advanced chip manufacturing. It's not the only country in this situation; plus, it's never a good idea to have all the eggs in one basket. Many companies are building chip factories outside Taiwan, especially since the COVID crisis illustrated how tightly woven worldwide supply chains are.

The problem is, erecting fabs is an exceedingly time- and money-consuming endeavor. TSMC's Arizona three-fab facility is top-notch, but costs around $55 billion per individual factory. Samsung's Texas fab is going on over $40 billion, and the price tag for Rapidus' Japan build is over $30 billion. All these price tags are significantly higher than those from Taiwan (or South Korea), and it takes multiple years to get just one fab fully set up and ready.

Production still face numerous challenges

Right now, there are only a handful of locations worldwide actively (or about to start) producing sub-5nm class chips. To briefly sum things up, there's TSMC Arizona, Intel Ireland, and JASM's Kumamoto facility. Samsung's Texas fab will be joining them soon. However, when it comes to making 2nm-class chips outside Taiwan, you can only count on TSMC Arizona.

The AI boom has filled TSMC's coffers to the brim, but as the saying goes, heavy is the head that wears the crown. The company is now worth around $1.7 trillion, and at face value, the trade deal is a boon for both nations and would theoretically strengthen the silicon shield, but there are underlying dangers.

The first concern is that rapid expansion into the United States requires qualified personnel, leading to a potential brain drain, or "hollowing out", of TSMC. The Arizona fab is already home to many Taiwanese engineers, something that TSMC has repeatedly framed as a temporary situation meant to help the local workers get up to speed, but that seemingly turned semi-permanent and presumably made worse by the accelerated build and production schedule.

Brain drain fears

The firm previously stated that there were "insufficient skilled workers" in the region, and the Taiwanese culture of 12-hour shifts and rigid structure clashed with U.S. labor laws, and only exacerbated the shortage. Illustrating the situation, last November, 137,000 Taiwanese citizens were working in the U.S., with the increase in that figure mostly attributed to TSMC's expansion.

Both TSMC and Taiwan government representatives have repeatedly assuaged worries about the brain drain, stating that the most advanced R&D will remain in the home base. However, the U.S. administration wishes to manufacture precisely the highest-grade chips in its soil, and is reportedly offering assistance to Taiwan for "acquiring resources such as land, water, electricity, infrastructure, tax incentives and visa programs", further enticing staff exports.

Pure chip production cost is also a factor. Labor is far more expensive in the U.S. than in Taiwan, so high-end chips made there are expected to be substantially pricier than usual. This would eat into TSMC's profit margin, and/or require big shoppers like Nvidia and Apple to be willing to pay premium prices for the same goods, risking the investment. There's a fair chance that further U.S. government intervention could help remedy this, though, as the Trump administration can't help but keep twiddling the tariff knobs everywhere.

On that note, Washington's desire to essentially reshore 40% of advanced chip production is seen by many as unrealistic. Just today, Nvidia CEO Jensen Huang arrived in Taiwan and tried offering some clarification, saying that that 40% slice is meant to be taken from new chip production. He further believes that TSMC must expand beyond Taiwan to meet current needs, remarking on Taiwan's energy capabilities as one key limitation factor.

Even still, those statements appear to be at odds with those of the opposite corner, with Economics Minister Kung Ming-hsin saying that Taipei wants to keep 85% of advanced chip production capacity by 2030, a split set to increase to 80%/20% by 2036.

Moreover, since the deal has yet to be ratified by the opposition-controlled Taiwan Executive Yuan. Unsurprisingly, said opposition has been fierce in criticizing the arrangement. Several members pointed out that the government made the deal under duress of tariffs, without properly consulting all the parties, and offering insufficient info. The main opposition party, Kuomintang (KMT), called for a full legislative review of the agreement on the day after it was signed.

Opponents also remarked that Taiwan would effectively use its own money to fund U.S. investments, and that the negotiation itself was poor, as Taipei only got the same 15% general tariff reduction as other countries while offering up its most precious strategic commodity. Some could counter-argue that the duty-free chip exports could be more valuable overall, however.

TSMC and Taiwan are definitely living in interesting times, and we'll be sure to hear a lot more about this trade deal in the coming weeks. It'll be exceedingly difficult for Taiwan to keep its huge customers happy, thus keeping the silicon shield powered, without losing a technological edge to its competitors, nor moving its best goods out of the country. Either of those would turn off the shield regardless. It's definitely a balancing act on a tightrope.

Jensen Huang, chief executive of Nvidia, has rebuffed claims that the U.S. intends to shift 40% of Taiwan's semiconductor capacity to the U.S., therefore removing the island's silicon shield, reports DigiTimes. He insisted that the global fab construction represents new capacity growth rather than relocation. Haung also said that TSMC must expand worldwide to meet surging AI-driven demand for chips and keep Taiwan as its stronghold.

Huang explained that demand for wafers is now outpacing what Taiwan's power grid can physically support, making overseas production a necessity rather than a political manoeuvre. He said that while TSMC will build and expand fabs in the U.S., Europe, and Japan, a substantial share of its output will remain in Taiwan, as no other region can replace the island's manufacturing ecosystem. According to Huang, spreading production across multiple regions strengthens resilience for both Taiwan and the U.S. and prevents supply bottlenecks as AI hardware volumes rise sharply.

For Nvidia, which sells everything it can produce both in Taiwan and the U.S., vast manufacturing capacities are crucial. Meanwhile, getting enough memory — HBM, DDR5, GDDR7, LPDDR5X, or even NAND — is as crucial for the company as getting enough compute silicon. To that end, production capacities for DRAM and NAND in Japan, South Korea, Taiwan, Singapore, and eventually the U.S. are just as important to Nvidia as logic production. Huang said the company is coordinating closely with all major HBM suppliers —Samsung Electronics, SK hynix, and Micron Technology — to secure the volumes required for its next-generation AI accelerators, namely Rubin.

When it comes to geopolitics, Huang said that lawmakers must balance three competing goals: national security, technological leadership, and economic leadership. Therefore, he dismissed remarks by Anthropic CEO Dario Amodei, who compared exporting advanced AI processors to China to 'selling nuclear weapons to North Korea,' and reminded that the current U.S. government has determined that selling Nvidia's H200 to Chinese entities does not undermine national security. However, he noted that it is now up to the Chinese government to let these processors into the country, as the company is awaiting regulatory clearance from Chinese authorities.

During his Taiwan visit, Huang plans to attend internal Nvidia meetings and Lunar New Year events, as well as to meet TSMC founder Morris Chang and chairman C.C. Wei.

ASML this week posted its highest yearly result ever as demand for its chipmaking tools set records. The company's revenue for the fiscal year 2025 totaled €32.7 billion ($39 billion USD), up 15% from the previous year. As expected, sales of lithography and other wafer fab equipment to China-based entities decreased in 2025 due to export rules imposed by the U.S. and the Netherlands. When it comes to sales of lithography systems, EUV tools became the leading source of ASML's revenue.

Fewer sales in China

Driven by the Made in China 2025 program and the buildout of the Chinese semiconductor industry amid tightening export curbs by the U.S. in recent years, ASML's sales to the People's Republic set records and culminated with 41% of the company's system unit share in 2024. Last year, sales of ASML's fab tools to China dropped, but 33% of ASML's tools (in terms of units) were sold to the PRC, meaning that Chinese chipmakers kept buying dozens of lithography and other machines for their fabs that use trailing nodes. Some of those older DUV systems are reportedly being upgraded by grey-market means.

China is followed by sales of wafer fab equipment to customers in South Korea (25%) and Taiwan (22%). By contrast, only 12% of ASML-produced tools (by unit count) were shipped to the U.S.

High-end EUV

U.S.-based Intel bought the world's first High-NA EUV Twinscan EXE:5200B lithography tool with 0.55 numerical aperture optics, designed for mass production of chips using next-generation process technologies, such as Intel's 14A (1.4nm-class). Another system was assembled at SK hynix's fab M16 in Icheon, South Korea. Meanwhile, ASML has supplied eight High-NA EUV tools (including six EXE:5000 and two EXE:5200B machines) to additional partners so far.

Speaking of EUV lithography systems, it's important to note that both current-generation Low-NA EUV scanners and next-generation High-NA EUV machines accounted for 48% of ASML's system revenue in 2025 (or €11.6 billion / $13.8 billion USD), up from 38% a year earlier. For the whole year, the company shipped 48 EUV systems and 131 immersion DUV tools, up from 44 EUV scanners and 129 immersion DUV machines in 2024.

Sales of EUV and sophisticated DUV tools are primarily driven by leading-edge logic fabs that build chips for AI infrastructure as well as smartphones and PCs. In fact, logic fabs accounted for 66% of ASML's system sales, whereas memory accounted for 34%. Although both logic and memory makers strive to increase their output and procure new tools, logic producers buy more expensive EUV systems.

"In advanced Logic, our foundry customers have become more positive on the long-term sustainability of demand on a number of fronts," said Fouquet. "AI accelerators are migrating from the 4nm node to the more litho-intensive 3nm node. At the same time, customers continue to ramp the 2nm node in support of next-generation HPC and mobile applications."

However, as DRAM vendors adopt more sophisticated fabrication processes that rely on EUV, they will also intensify procuring EUV scanners, which will significantly increase demand for this type of equipment as memory makers tend to operate very large fleets to fab commodity products in the most cost-efficient way.

"In memory, our customers are reporting very strong demand for both HBM and DDR products with supply remaining very tight through at least 2026 as they ramp both their 1b and 1c nodes in support of the demand," Fouquet added. "In addition, DRAM customers continue to adopt more EUV layers on these nodes. This is expected to continue on their future nodes as they migrate more multi-patterning DUV to single-exposure EUV, resulting in an increase in litho intensity."

Record results

ASML closed 2025 with a record fourth quarter and its strongest year ever. In Q4 2025, the company's revenue totaled €9.7 billion ($11.5 billion USD), its gross margin reached 52.2%, and net income hit €2.8 billion ($3.3 billion USD).

For the full year, the company generated €32.7 billion ($39 billion USD) in net sales, up from €28.3 billion ($33.8 billion USD) in 2024, with a 52.8% gross margin and €9.6 billion ($11.4 billion) in net income.

ASML's net bookings reached €28.0 billion ($33.4 billion USD), whereas their year-end backlog grew to €38.8 billion ($46.3 billion USD), another record for the company.

During the final quarter of 2025, the company supplied 94 new photolithography systems as well as eight used lithography machines. For the whole year, ASML sold 300 new lithography tools and 27 used lithography systems.

For the first quarter of 2026, ASML expects revenue of €8.2 billion – €8.9 billion ($9.7 - $10.6 billion USD), which is up year-over-year but down sequentially. Full-year 2026 revenue is projected to be between €34 billion and €39 billion ($40 billion - 46 billion USD), this reflects growing demand for lithography tools and EUV scanners, primarily due to the wide AI infrastructure buildout. Gross margins at ASML are projected to be between 51% and 53%.

"In the last months, many of our customers have shared a notably more positive assessment of the medium-term market situation, primarily based on more robust expectations of the sustainability of AI-related demand," said Christophe Fouquet, chief executive of ASML. "This is reflected in a marked step-up in their medium-term capacity plans and in our record order intake. Therefore, we expect 2026 to be another growth year for ASML's business, largely driven by a significant increase in EUV sales and growth in our installed base business sales. We continue to invest in people and footprint to support that growth in 2026 and beyond."

Looking ahead

Being the only supplier of EUV and advanced DUV tools on the planet, ASML has every reason to expect sales of these scanners to increase in the coming years. The number of EUV layers increases with the upcoming process technologies, driving its revenue all the way to €44 billion - €60 billion ($52 billion - 71 billion USD) in 2030. Indeed, EUV tools accounted for 65% of ASML's backlog in late 2025, up from 62% a year before. If the demand for their tools continues apace, then ASML will be sitting as one of the most important companies in the ongoing AI boom, right alongside Nvidia.

The U.S. and Taiwan just settled on a new trade deal that will see Washington cut tariffs on the island from 20% to 15%. In exchange for this, Taipei committed at least $250 billion in direct investments in the U.S. on advanced semiconductor manufacturing, energy production and distribution, and artificial intelligence operations. Aside from this, the Taiwanese government also committed an additional $250 billion in credit guarantees for its companies investing in American semiconductor operations. This brings the total amount in the trade deal to $500 billion, according to Bloomberg, but already includes the $100 billion U.S. investment that TSMC announced in March 2025.

TSMC is reportedly looking to further expand its U.S. presence, with plans to build four more fabs on top of the planned, under-construction, and existing facilities in Arizona. “They just bought hundreds of acres adjacent to their property,” U.S. Commerce Sec. Howard Lutnick said in an interview with CNBC. “I’ll let them go through with their board and give them time.”

In line with this, Taiwanese chip makers constructing facilities in the U.S. are entitled to import 2.5 times their current capacity without import taxes, with the limit reducing to 1.5 times once they start stateside production. On the other hand, Taiwanese companies that refuse to play ball with the White House will receive severe penalties. “If they don’t build in America, the tariff’s likely to be 100%,” Lutnick said. “If they commit to build in America, they can bring in their semiconductors during the time they’re building in America without a tariff.”

This massive spending increase by Taiwanese companies in the U.S. is a big win for the Trump administration, especially as it targets increasing domestic cutting-edge chip production. The White House claims that the United States consumes 25% of the market for the most advanced semiconductors. However, it only produces about 10% of the global volume, meaning it’s dependent on chip imports for its most advanced technologies. Taiwan is producing the other 90%, and with China posing a significant threat to the island, the U.S. is nervous that any hostile move would cripple its ability to get the chips that it needs.

The more than $500 billion commitment will help the U.S. bring semiconductor manufacturing back within its borders, helping secure its high-tech supply chain. On the other hand, there have been concerns that this expansion will reduce the potency of the island’s “silicon shield.” Taipei addressed this by refusing to move half of U.S.-bound chip production to American shores, while also restricting TSMC from exporting its most advanced nodes outside of Taiwan.

TSMC on Thursday published its financial results for 2025, posting an annual revenue of $122.42 billion for the first time in its history. TSMC's extraordinary results were driven by sales of AI and HPC processors — which accounted for 58% of the company's 2025 revenue — as well as the company's growing market share. To support rising demand for its services as well as tooling of advanced fabs in Taiwan and Arizona, TSMC has committed to increasing its capital expenditure (CapEx) to $52 billion - $56 billion in 2026, which is more than Intel and Samsung spent in 2025 combined. When asked about the prospect of an AI bubble, TSMC's CEO warned the company was "very nervous," hence the hefty CapEx spend. He further warned, "If we did not do it carefully, that would be a disaster for TSMC for sure."

An AI bubble? What AI bubble?

Apparently, TSMC does not expect demand for AI processors to slow down in the foreseeable future, so this year the foundry plans to spend between $52 billion and $56 billion on new production capacity and fabrication/packaging tools.

More specifically, TSMC intends to spend about 10% of its CapEx on specialty technologies, between 10% and 20% of CapEx on advanced packaging, and around 70% will be used to buy sophisticated equipment (both for existing and new fabs) and build new advanced logic fabs. While TSMC certainly understands the risks of the so-called AI bubble, given the lead times for new fabs (about three years) and advanced fab tools, it does not seem to expect that bubble to pop in the coming years, at least based on C.C. Wei's answer to one of the questions.

"You essentially try to ask us whether the AI demand is real or not," C.C. Wei, chief executive of TSMC, asked rhetorically during the company's earnings conference. "I am also very nervous about it. You bet, because we have to invest about $52 billion to $56 billion for the CapEx. If we did not do it carefully, and that would be big disaster to TSMC for sure. So, I spent a lot of time in the last three – four months talking to my customer and my customer's customer, as I want to make sure that my customer's demand is real. So, I talked to those cloud service providers, all of them. […] I am quite satisfied with the answer. Actually, they showed me the evidence that the AI really helps their business. So, they grow their business successfully and healthily in their financial return. I also double checked their financial status: they are very rich […] much better than TSMC."

Indeed, out of $122.42 billion that TSMC earned in 2025, AI and HPC* processors accounted for 58%, or roughly $71 billion, a 48% year-over-year growth, and the highest result for these categories in years.

From a node perspective, advanced process technologies accounted for 74% of the foundry's wafer revenue, with 3nm accounting for 24%, 5nm responsible for 36%, and 7nm liable for 14%.

More advanced fab modules to support demand

TSMC began to ramp up production of chips using its N2 (2nm-class) fabrication process at Fab 20 and Fab 22 in Taiwan in the fourth quarter, with more N2 and A16-capable fab modules coming online in the foreseeable future to support unprecedented demand for leading-edge nodes over the coming years.

As for the $165 billion Arizona Fab 21 campus buildout, C.C. Wei confirmed that Fab 21 phase 2 shell has been constructed, with fab tool installation set to begin in 2026 and first products coming from the fab in the second half of 2027. The Fab 21 phase 3 building is in progress, and TSMC has already obtained permits for Fab 21 phase 4 and the advanced packaging facility in Arizona. Finally, the company has acquired another plot of land to support Fab 21 expansion and "provide more flexibility in response to the very strong multiyear AI-related demand."

"Our plan will enable TSMC to scale up an independent giga-fab cluster in Arizona to support the need of our leading-edge customers in smartphone, AI, and HPC applications," Wei said.

Intel Foundry? Not a competitor any time soon

Pouring in $165 billion in its Fab 21 campus near Phoenix, Arizona, is a tremendous business project full of risks and uncertainties. Competition from other players — such as Intel Foundry and Samsung Foundry — is among the risks for TSMC. Furthermore, with the U.S. government, Nvidia, and Softbank investing in Intel, the company's reputation as a formidable competitor is growing stronger in the eyes of industry observers. However, TSMC chief executive C.C. Wei does not expect Intel Foundry to actually become a competitor that might slow his company's growth any time soon.

Without any doubt, Intel's ramping up of Panther Lake on its leading-edge 18A (1.8nm-class) process technology is an impressive achievement. However, for now, only Intel can build chips on 18A. By contrast, TSMC has multiple alpha customers with its N2 node, who have worked on their chips for years. The message that C.C. Wei sent is that leading-edge foundry competition is constrained by time, not by capital. He said, "it is not money to help you to compete," pushing back against the idea that government support or large investments can instantly create competitiveness at advanced nodes.

C.C. Wei recalled that it takes between two and three years for customers to learn how to design a complex chip on a new process and work closely with the chipmaker on DTCO (design technology co-optimization), followed by another one or two years to qualify and ramp it into high-volume production.

"Today's [leading-edge] technology is so complicated [that] once you want to design [a chip], it takes two to three years to fully utilize that technology," said Wei. "After two to three years of preparation, you can design your product. Once you get your product being approved, it takes another one to two years to ramp it up."

That means even if customers like Apple or Nvidia chose today to use Intel Foundry at the leading-edge, any meaningful commercial impact would likely appear around 2028 – 2030 (both for 18A and 14A), not in the near term. Furthermore, porting a leading-edge design from one foundry to another is an extremely complex task since things like standard-cell libraries, third-party IP blocks, power-delivery techniques, timings, and yield learnings are tightly coupled to a specific manufacturing process, which means that porting equals designing and validating from scratch, something that takes years, costs millions, and there is no guarantee of success.

"So, we have a competitor, no doubt about it, that is a formidable competitor," Wei added. "But first, it takes time. Two, we do not underestimate their progress, but are we afraid of it? For 30-some years, we are always in a competition with our competitors, so no, we have confidence to keep our business grow as we estimate."

Interestingly, the timeline presented by Wei mirrors TSMC's own outlook, where the next two years are about squeezing more output from existing fabs by ramping up N2-capable capacity in Taiwan and by converting N5-capable fabs to N3-capable fabs, while several all-new fabs are set to come online only in 2028 – 2029.

Throughout its history, TSMC has had impressive rivals like IBM, UMC, and Samsung, which TSMC has managed to leave behind. But the complexity of the semiconductor industry in general and leading-edge process technologies in particular is so high today that matching TSMC is not about achieving similar transistor performance, power, and density, but about building an entire development ecosystem that spans from defining a new node with a customer (or customers in case of N2 and A16) and partners to helping them design and optimize their chip and then assisting them with volume ramp it five or six years down the road.

The bottom line about today's leading-edge nodes is that this is a long-term commitment that takes time and a lot of money, and no short-term or mid-term investments from reputable entities can change that.

Good results can only get better

TSMC earned $33.73 billion in revenue for the fourth quarter of 2025, up 20.5% year-over-year, the company's highest quarter revenue ever. The company's gross margin reached 62.3% (up from 59% in Q4 2024) amid the building of multiple manufacturing facilities and ramping up production on TSMC's all-new N2 fabrication process, which typically hurts margins significantly. The foundry's net income reached around $16.012 billion, which also happens to be a record. As for the results for the whole year, TSMC earned $122.42 billion in revenue and $55.133 billion in net income.

It is noteworthy that despite posting the company's best quarter results ever, TSMC's management is confident that the company will earn between $34.6 billion and $35.8 billion in the first quarter, which is traditionally a slow quarter for electronics in general and microelectronics specifically.

*HPC is a vague term TSMC uses to describe everything from laptop CPUs to high-end AI accelerators.

Elon Musk this week said that the chipmaking industry builds cleanrooms in the wrong way. The head of Tesla and SpaceX promised that once Tesla builds its own 2nm-capable fab, he would eat a cheeseburger and smoke a cigar in that fab.

"I think they are getting clean rooms wrong in these modern fabs," said Elon Musk in an interview with Moonshots. "I am going to make a bet here, that Tesla will have a 2nm fab, and I can eat a cheeseburger and smoke a cigar in the fab."

When asked whether Musk had sketched Tesla's fab in his mind and whether he found a way to protect silicon wafers from cheeseburger grease, he responded that all wafers should be contained at all times. "They just maintain wafer isolation the entire time," Musk said.

A modern fab is a large, integrated manufacturing facility that encompasses ultra-clean production cleanrooms where wafers are processed; sub-fab levels housing vacuum pumps, gas handling, and exhaust systems, dedicated tool service corridors for maintenance and utilities; centralized chemical delivery and waste management infrastructure; as well as office and control areas used for administrative work, engineering, and monitoring.

Meanwhile, cleanrooms are essentially buildings within fab buildings as they are completely separated from other segments of the fab shell. Cleanliness in cleanrooms is specified by ISO Class standards that define the number of particles per cubic meter of air at different particle sizes. For example, an ISO Class 1 cleanroom allows at most 10 particles ≥0.1 µm per cubic meter and 2 larger particles, whereas an ISO Class 2 cleanroom allows up to 100 particles ≥0.1 µm per cubic meter and 38 larger particles. The most critical operations — such as EUV or DUV lithography exposures or advanced gate formation are performed in ISO Class 1 and 2 environments. By contrast, an ISO Class 3 cleanroom allows up to 1,000 particles ≥0.1 µm per cubic meter, which is still vastly cleaner than typical fab environments and common in advanced fabs for less sensitive operations.

Naturally, smoking or eating a burger in ISO Class 1 – 3 environments is absolutely not allowed, as it renders hundreds of millions or billions of particles. In fact, one human breath produces millions of particles along with moisture, not to mention organic contamination with bacteria or viruses. So, even if wafer and tool isolation is perfect, human breath (not to mention smoke or food particles) can affect the environment, which will affect ultra-sensitive EUV mirrors and perhaps fab chemistry.

Eating and smoking in other areas of the fab is also prohibited due to contamination control and safety requirements. In theory, Musk could eat a burger and smoke his cigar in office areas, which is possible even today. Still, smoking is banned in most office buildings anyway.

This is not the first time that Elon Musk has blasted the foundry industry. While he admired Tesla's partners TSMC and Samsung Foundry, in recent months, he has criticized the foundry industry for slow fab buildout and insufficient capacities, which is slowing down the development of Musk's xAI artificial intelligence initiatives. Musk once mentioned that at some point, Tesla could build its own semiconductor production facility, but given the extreme complexity of such an endeavor, this is something that is unlikely to happen. Furthermore, given the comments made by Musk, it does not look like he had an expert-level understanding of how modern leading-edge semiconductor fabs work.

The U.S. Department of Commerce has issued a permit to Taiwan Semiconductor Manufacturing Company (TSMC) to import U.S.-made chip-making equipment into China for its Nanjing fab. According to Reuters, Samsung and SK hynix were also given import licenses to bring in specialized equipment that used American-made components into their Chinese factories. These three chipmakers used to enjoy validated end-user status, meaning they could freely import restricted items into China without asking for individual licenses. However, this privilege has expired at the end of 2025, meaning they now have to seek annual approval from Washington, D.C., to continue receiving advanced tools.

“The U.S. Department of Commerce has granted TSMC Nanjing an annual export license that allows U.S. export-controlled items to be supplied to TSMC Nanjing without the need for individual vendor licenses,” the company said in a statement to Reuters. It also said that this “ensures uninterrupted fab operations and product deliveries.” This move to require annual licenses for the Chinese factories of these chipmakers is a part of the White House’s effort to keep advanced chipmaking tools out of China.

Beijing has been working hard to achieve “semiconductor sovereignty,” just as the U.S. has been trying hard to prevent it from acquiring the latest chips. Aside from that, ASML, the only manufacturer of cutting-edge chipmaking tools, has been banned from exporting its products to China and servicing those that are already installed. Because of this, we’ve seen reports that the country is covertly working on reverse engineering EUV lithography tools, and that it has even come up with a “Frankenstein” EUV chipmaking tool, but has yet to produce a single chip.

The U.S. does not allow EUV lithography machines with U.S. technology to be exported to China, even to companies like TSMC and Samsung that have Chinese factories. This means that these fabs are only limited to mature nodes of 16-nm and up. The revocation of the validated end-user status for the China-based fabs of these companies shows that Washington is tightening its grip on chipmaking machines, even older DUV tech, to make it difficult for Beijing to create its own technology.

Despite this, the East Asian nation is pushing hard to develop its own equipment. The central government has even told its chipmakers to use homegrown tools for half of new capacity. And while the country is still years behind cutting-edge tech from ASML and other Western companies, it’s slowly taking steps in the right direction.

TSMC has quietly revealed that it had commenced volume production of chips using its N2 (2nm-class) fabrication process. The company did not issue a formal press release notifying about the production start, but the firm had said multiple times that N2 was on track for volume manufacturing in Q4, so the plan has been fulfilled.

"TSMC’s 2nm (N2) technology has started volume production in 4Q25 as planned," a statement at TSMC's web page dedicated to 2nm Technology reads.

From an improvement standpoint, N2 is designed to deliver a 10%–15% performance gain at the same power, a 25%–30% reduction in power at the same performance, and a 15% increase in transistor density compared to N3E for mixed designs that include logic, analog, and SRAM. For logic-only designs, transistor density is up to 20% higher than N3E.

*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same speed.
***At the same power.

TSMC's N2 is the company's first process node to adopt gate-all-around (GAA) nanosheet transistors, where the gate fully surrounds the channel formed by stacked horizontal nanosheets. This geometry improves electrostatic control, reduces leakage, and enables smaller transistors without sacrificing performance or power efficiency, ultimately increasing transistor density. In addition, N2 also adds super-high-performance metal-insulator-metal (SHPMIM) capacitors to the power delivery network. These offer more than twice the capacitance density of the prior SHDMIM design and cut both sheet resistance (Rs) and via resistance (Rc) by 50%, which improves power stability, performance, and overall energy efficiency.

"N2 is well on track for volume production later this quarter, with good yield," said C.C. Wei, chief executive of TSMC, during the company's earnings call in October. "We expect a faster ramp in 2026, fueled by both smartphone and HPC AI applications."

What is interesting is that the company began to make 2nm-class chips at its Fab 22, which is located near Kaohsiung, Taiwan. Previously it was expected that TSMC would begin ramping up N2 production at Fab 20 (near Hsinchu, Taiwan), which is adjacent to its new global R&D center, where N2-series fabrication technologies were developed. Fab 20 will likely commence mass production a bit later.

TSMC will be ramping up mass production of N2-based chips at brand-new fabs, which is always a bit tricky. What is noteworthy is that the company will ramp production of both smartphone and larger 'AI' and 'HPC' designs at new fabs (note that HPC is a vague term that describes everything from game console SoCs all the way to heavy-duty server CPUs), which will add some additional complexities. Normally, TSMC ramps new nodes with mobile and small consumer designs.

Ramping up two N2-capable fabs at once is a result of strong interest for the new process technology by a variety of TSMC partners, so it needs to offer decent capacity for all of them. Furthermore, starting late 2026, both fabs will be used to build chips on N2P, a performance-enhanced version of N2, and A16, a version of N2P with the Super Power Rail backside power delivery that is aimed at complex AI and HPC processors.

"With our strategy of continuous enhancements, we will also introduce N2P as an extension of our N2 family," Wei added. "N2P features further performance and power benefits on top of N2 and volume production scheduled for second half 2026. We also introduced A16 featuring our best-in-class Super Power Rail, or SPR. A16 is best suited for specific HPC products with complex signal routes and dense power delivery networks. Volume production is on track for second half 2026."

TSMC's average selling prices (ASPs) for its wafers have increased 15.9% annually from 2019 to 2025. Additionally, gross profit margins per wafer rose rapidly to 3.3x throughout 2025, according to SemiAnalysis. This increased margin reflects TSMC fully leveraging its market-leading position and broad ecosystem to command higher product pricing, which in turn drives downstream effects, including higher end-product pricing. The increases come after a decade during which TSMC earned minimal profit, keeping pricing low as it cornered the market and expanded its market share.

The new era of extreme ultraviolet (EUV) chipmaking began in 2019, with TSMC positioned as the top contract chipmaker. Equipped with robust production capacity and an ecosystem of partners leveraging this new technology, TSMC has seen significant ASP growth. The company is expected to maintain this momentum into 2026 and beyond, driven by several factors.

The rise of TSMC

Since its inception in 1987, through to the 2010s, TSMC was considered a leading foundry, but not a leading chipmaker. At the time, Intel was the undisputed champion of the semiconductor industry, with microelectronics pioneers like IBM also remaining competitive. However, TSMC has been consistently expanding its ecosystem over the years. In 2008, the company established its Open Innovation Platform (OIP) program — uniting TSMC with chip designers, IP providers, and EDA tool developers — essentially setting the stage for its current success.

Things changed suddenly for TSMC in the mid-2010s, when Apple outsourced production of its chips to TSMC, departing from Samsung, which had since become a significant rival to Apple in the smartphone segment. For Apple, going with TSMC guaranteed no IP theft and no plans to compete in the smartphone segment. TSMC also offered a continually evolving roadmap of process technologies and capacity availability, which, among other things, persuaded Apple to back TSMC.

Landing orders from the world's largest manufacturers of consumer electronics (including Huawei, Sony, and Panasonic) gave TSMC the financial capacity required to invest in R&D and new tools to produce chips for customers at high volumes. With Intel's hiccups with its 10nm fabrication process, TSMC entered 2019 with all of the factors needed to become a market leader.

The company was offering services that no other chipmaker could match, bagging big-name customers like Apple, Huawei, and Nvidia in the process. This offered TSMC not only informal recognition of leadership but also the financial resources to expand its turf.

Expensive tools? Even more expensive chips

As a result, after more than a decade of stagnation, TSMC's wafer pricing model fundamentally changed in 2019, as it had to buy, deploy, and depreciate ASML's Twinscan NXE tools, which cost around $235 million each. While these tools from ASML were less expensive in 2019, they steadily increased in price, as the machines became more advanced.

Since TSMC had no real competition, and an increase in the costs of machinery, these factors set the stage for market dominance. Paired with the massive OIP infrastructure, TSMC managed to expand gross profit per wafer by roughly 3.3x throughout 2025, based on data from SemiAnalysis. The report claims that quotes are rising at a far faster pace than production costs, which sets a new economic baseline for leading-edge foundry manufacturing.

EUV revolutionizes fab industry

From 2005 to 2019, TSMC's wafer ASPs remained largely flat because leading-edge foundry capacity was still relatively elastic due to competition, according to SemiAnalysis. Over those 15 years, ASPs increased by only $32 per wafer, with an annual growth rate of approximately 0.1%. Process nodes advanced rapidly using DUV lithography, so capital intensity increased gradually (i.e., in accordance with the growth of customer requirements) rather than exponentially.

During this period, the company largely operated under a cost-pass-through model, using modest pricing adjustments to offset rising manufacturing expenses. This approach limited margin expansion even as process complexity increased. Consequently, market conditions dictated wafer pricing, rather than the capital requirements of foundries.

However, customer economics limited this value-based pricing. Leading-edge demand was dominated by smartphones and consumer SoCs with tightly constrained bill-of-materials (BOM) targets, and no ballooning AI or HPC segment was generating massive gross margins. Yield learning curves were rapid; performance-per-watt gains were predictable; tool and mask costs were rising at a pace that allowed rivals to follow TSMC with capacity and competitive nodes; and there was no structural shortage of production capacity.

As a result, TSMC, just like other foundries, prioritized utilization, scale, and long-term ecosystem dominance over margin expansion. This strategy kept ASP growth near zero until TSMC began to adopt EUV for high-volume manufacturing, forcing their hand and intensifying capital expenditures. These factors coincided with the beginning of the AI and HPC megatrends we've observed in recent years.

In the six years that followed, wafer ASPs at TSMC rose by approximately 133%, equivalent to a 15.2% compound annual growth rate, while the cost of goods sold increased by only 78%. As a result, TSMC's gross profit per wafer increased sharply. Regression analysis made by SemiAnalysis illustrates the shift clearly: before 2019, every $1 increase in cost of goods sold (COGS) translated into $1.43 in ASP, yielding $0.43 in incremental profit; after 2019, the same $1 cost increase generated $2.31 in ASP, or more than $1.30 in incremental profit.

As noted above, the inflection coincided with the industry's transition to EUV-based process technologies, which dramatically altered supply dynamics, as TSMC became the only viable choice for big companies. While Samsung began using EUV tools for HVM in 2018, it used them only for its own chips, primarily due to tool scarcity and yield constraints.

The use of EUV tools at TSMC increased capital intensity and slowed capacity expansion, as EUV systems are physically larger than older DUV scanners and place their light source beneath the tool, making the addition of leading-edge output even more difficult. As a result, advanced-node wafers ceased to be interchangeable commodities and became capacity-constrained assets for tens of competing high-tech giants.

This allowed TSMC to price its output well above incremental cost without eroding demand. AI and HPC processors produced for customers like AMD, Broadcom, Google, Intel, or Nvidia carry significantly higher margins than legacy mobile or consumer chips. As a result, TSMC anchors pricing to customer value rather than manufacturing expense, which highlights the post-2019 divergence between ASP growth and COGS inflation.

In fact, big customers like AMD, Broadcom, Nvidia, and Marvell are willing to pay TSMC extra to lock in production capacity with the best process technologies to produce AI accelerators.

Advanced packaging further strengthened TSMC's position. By integrating leading-edge logic with sophisticated packaging technologies, the company increased customer lock-in and raised barriers for competitors. Notably, rising wafer costs now work in TSMC’s favor by discouraging new entrants and widening the competitive moat, rather than compressing margins as they did in earlier eras.

A new foundry model

The data published by SemiAnalysis indicates that TSMC has transitioned from a traditional foundry model focused on scale, utilization, and cost recovery to one defined by systematic undersupply, extreme capital intensity, and value-based pricing.

Leading-edge wafers are no longer commodities that can be obtained from multiple sources, but constrained assets required by trillion-dollar corporations. Given the current situation, pricing is increasingly anchored in the economic value delivered to customers rather than in incremental manufacturing costs. As a result, TSMC is thriving, and it will continue to do so until a viable challenger emerges. Neither Intel Foundry nor Samsung Foundry can currently compete against TSMC's leading-edge production capabilities, at least not yet.

It should be noted that TSMC's pricing power did not appear overnight. It emerged after decades of sustained capital investment, consistent yield leadership across successive nodes, and the gradual consolidation of the industry's most valuable supplier onto a single chip development and manufacturing platform under the OIP brand. Also, TSMC has attracted most of the world's leading chip designers, including Intel, which has its own manufacturing capacities.

These factors created both technical and economic lock-in, resulting in rising costs that reinforce competitive barriers rather than shrinking margins. This highlights a fundamental reality of advanced semiconductor manufacturing in general: TSMC's lasting pricing power has emerged from long-term structural investments along with stable performance increases and yields, and cannot be replicated in the short term.

Yesterday, the ground shook off the coast of Taiwan, slamming the country with the strongest earthquake in 27 years. The seismic wave registered 7.0 on Taiwan's scale, or 6.6 to 6.7 according to the USGS standard. Thankfully, according to reports, TSMC's factories are all intact, saving the world from yet another spike in chip prices.

The epicenter was located on the seabed in the eastern part of the country, approximately 33 km (20.5 mi) east of Yilan. The focal depth was 72.8 km deep (45 mi), deep enough for the quake not to cause too much damage when it hit the shores. Even still, it's the third earthquake of magnitude 7 or higher to hit Taiwan since 1999.

In the Hsinchu area, where most semiconductor facilities are located, the vibrations were only magnitude 4. TSMC reported that some earthquake alert systems were triggered and that some facilities were evacuated in accordance with safety protocols. Following a safety inspection, work was briefly resumed, with no apparent damage noted.

Even in the rest of the country, there was only minor damage. Taiwan's High Speed Rail temporarily stopped six trains in their tracks for a while, and the vast majority of damage reports pertained only to elevators, gas and water leaks, and minor damage to some buildings.

The fact that TSMC was, for all purposes, unaffected by the quake comes down to the company's continued investment in earthquake mitigation measures. The damage from the 1999 earthquake taught harsh lessons, and TSMC learned them all, as the company's safety systems exceed government standards.

The clean rooms are isolated from external vibrations with double-shell structures, and there are viscous dampers and hydraulic pistons installed aplenty. Floating piles absorb vibrations and protect buildings from side-to-side damage, too. Emergency power systems are widespread, as the 1999 earthquake demonstrated that fluctuating power delivery can be as financially damaging as the vibration itself. For good measure, TSMC has its own earthquake warning system.

Even in 2024, when the "0403 Earthquake" hit, TSMC had 70% of its equipment back online in 10 hours, including 80% of its newest fabs, and lost no critical tools, including the EUIV system. Even that stronger event cost the company the comparably modest sum of NT$3 billion, or around $95 million. Losing TSMC's production would be a worldwide catastrophe, so it's good to see the safety investments paying off.

TSMC has shared a super-cool digital greeting card with its trusted partners, most important customers, and other insiders. The animation cleverly mixes retro-nostalgic 8-bit style gaming visuals and mechanics, symbolic elements of TSMC’s iconic logo, and (of course) a charming seasonal scene. We aren’t on TSMC’s Christmas card list, so we are thankful to Co-Founder & Research VP at CounterPoint, Neil Shah, for sharing the festive message from the world’s most important contract chipmaker.

Click 'see more' to watch the embedded video.

No surprise, the TSMC greeting card begins with the iconic logo, which features type set above a representation of a silicon wafer containing both good (white) and defective (black) tiles. A TSMC veteran once also said this ‘wafer map’ has a second meaning, inspired by Japanese theater. Interpreting this alternative symbolism, the black dies represent ‘kurogo,’ who traditionally dress in black and work invisibly to support the success of a theatrical production.

Whatever the meaning of the pixel grid (and both explanations could be true), the animated greeting card swiftly transforms the black and white dies into festively colored pixels to begin the Christmas animation.

The festive fun begins with two very pixilated-looking youngsters enjoying a snowball fight. An enthusiastically hurled snowball whizzes way past the target and into the stratosphere. Next, we get to enjoy a little 8-bit Breakout gaming magic, as the snowball beeps and bloops, eventually carving a fully formed Christmas tree from green blocks. The tree, complete with full decorations by now, floats down, almost hitting Santa in his sleigh during its descent. Finally, the tree comes to rest alongside some presents and candy canes, all in a vibrant, blocky 8-bit art style.

Even the most advanced chipmaker felt the pull of retro in 2025

One of the themes we have perceived strengthening throughout 2025 is the increasing desire for and interest in retro computing and retro gaming topics. It seems odd that the world’s most advanced chipmaker has chosen this theme, though.

As tech enthusiasts grow tired of difficult-to-find cutting-edge tech being gobbled up to feed unwanted AI overlords, we have seen increasing interest in reviving the ‘old days.’ We note that the likes of Commodore and Atari have been making the most of this wave of interest, with products such as the C64 Ultimate and the Gamestation Go, respectively.

These retro-modern products hark back to the days of computing fun without social media, without ever-stretching system requirements, and to the days when having a 1 MHz CPU, 64KB of RAM, and no GPU at all did not stand in the way of work or play.

Being concerned that TSMC’s expansion into the United States could dilute Taiwan’s semiconductor leadership, Taiwanese authorities are mulling setting a new export rule that would only let the world’s number-one foundry export technologies that are two generations behind its leading-edge production node, reports CNA. If this happens, this could slow down TSMC’s expansion in the U.S., as it currently relies on aggressive building of advanced fabs there.

The core of this new export policy is the government’s N-2 rule, which permits offshore deployment only of process technologies that trail Taiwan’s leading-edge by two generations. Previously, Taiwanese authorities stuck to their N-1 rule, allowing TSMC to export all technologies that are at least one generation behind the leading-edge fabrication process. The new framework is much stricter; depending on how one counts generations, it means that TSMC may only be allowed to export nodes that are two or even four years behind its best technology.

Under this approach, if TSMC were to develop a 1.2nm or 1.4nm-class fabrication process domestically, then only its 1.6nm-class production would be eligible for use abroad, according to Lin Fa-cheng, Deputy Minister of the National Science and Technology Council (NSTC).

For now, TSMC's Fab 21 phase 1 in Arizona is capable of making chips on N4/N5 fabrication technologies (which belong to the same generation). Domestically, TSMC has several fully ramped fabs capable of 3nm-class manufacturing processes (N3B, N3E, N3P, etc.) and is about to begin high-volume production of chips on its N2 production nodes, which belong to its 2nm-class. Formally, TSMC's Fab 21 phase 1 already complies with the N-2 rule. However, once TSMC begins to make chips on 3nm-class technologies at Fab 21 phase 2 in 2027, the facility will not be compliant with the N2-2 rule because N3 is formally just one generation behind N2/N2P/A16. Yet, while A16 is N2P with a backside power delivery network, if one considers A16 an all-new generation, then Fab 21 phase 2 will comply with the new high-tech export framework.

Lin also emphasized that most of TSMC's research and development workforce remains in Taiwan and noted that the company's R&D footprint aligns with government requirements. In practice, this concentration of engineers and scientists ensures that future process development stays anchored domestically, even as the company builds manufacturing capacity and R&D centers overseas. Lin also emphasized that all qualified personnel employed in the semiconductor industry are subject to regulatory oversight, which extends protection of IP and hardware to human capital.

In addition, any future U.S. investments by TSMC will be examined under existing laws, and projects exceeding certain thresholds must be reviewed by the MOEA’s Investment Commission, said Chou Yu-hsin, Deputy Director-General of the Industrial Development Administration under the MOEA.

TSMC is set to start moving equipment into its Fab 21 phase 2 in Arizona next summer, according to Nikkei, which cites sources familiar with the plan. Once the supporting and production tools are installed sometimes in 2027, the company will be able to start mass production of chips using its N3 technology, several quarters ahead of schedule.

TSMC will begin installation of equipment into its Fab 21 phase 2 in Arizona in the third calendar quarter — from July to September — of 2026, with the aim to start production at the facility in calendar 2027, several quarters ahead of the original schedule of 2028, if the report from Nikkei is accurate.

Construction of TSMC's Fab 21 phase 2 in Arizona was completed this year, according to the company. After the building itself, as well as its mechanical/electrical/plumbing systems, are complete, chipmakers begin to install internal infrastructure like elevators and HVACs. Once this phase is done, chip producers perform environmental qualification, and if everything — temperature, pressure, humidity — is stable, then actual production tools are moved in.

Depending on the tool, its installation and tuning take between hours and days, though high-end DUV and EUV lithography systems take significantly longer to install and tune than other machines at the fab. But in any case, it takes months to install the first group of tools, make them work in concert, and begin small-volume mass production. That said, TSMC has a chance to initiate mass production of chips on its N3 manufacturing technology in Arizona already in 2027, though volumes will be limited.

TSMC began to build its N2/A16-capable Fab 21 phase 3 in Arizona in April, 2025. The company hopes to complete this one as fast as possible to start output of its 2nm and 1.6nm-class chips in America ahead of schedule as well.

"With the strong collaboration and support from our leading U.S. customers and the U.S. federal, state, and city government, we continue to speed up our capacity expansion in Arizona," C.C. Wei, chief executive of TSMC, said at the most recent earnings call in October. "We are making tangible progress and executing well to our plan. In addition, we are preparing to upgrade our technologies faster to N2 and more advanced process technologies in Arizona, given the strong AI-related demand from our customers."

Global sales of semiconductor manufacturing tools are set to climb through at least 2027 due to increasing demand for chips by the AI sector as well as continued growth in China that strives for semiconductor self sufficiency, reports SEMI, an organization that unites different companies across the semiconductor supply chain.

Sales of semiconductor production tools — including wafer fab equipment (WFE), test tools, and assembly and packaging (A&P) equipment — are set to reach around $133 billion in 2025, up 13.7% year-on-year, followed by $145 billion in 2026 and $156 billion in 2027, if SEMI's estimates are correct. SEMI projects both front-end and back-end segments to expand continuously through the forecast period. It is necessary to note that the organization has revised its forecast from mid-2025 due to stronger than expected sales of AI accelerators and infrastructure required to support them.

"Global semiconductor equipment sales show robust momentum, with both the front-end and back-end segments projected to see three consecutive years of growth, culminating in total sales surpassing $150 billion for the first time in 2027," said Ajit Manocha, SEMI president and CEO. "Investments to support AI demand have been stronger than anticipated since our midyear forecast, leading us to boost the outlook for all segments."

Front-end equipment

Within the whole market of semiconductor manufacturing tools, front-end wafer fab equipment remains the dominant category. After reaching $104 billion in 2024, WFE revenue is forecast to increase 11% to $115.7 billion in 2025, up from SEMI's mid-year outlook. The adjustment reflects heavier spending on DRAM, and high-bandwidth memory (HBM) in particular, as well as continued fab build-outs in China. Growth is expected to persist in the coming years as WFE sales projected to rise 9% YoY in 2026 and 7.3% YoY in 2027, when they are expected to reach $135.2 billion.

On the application side, foundry and logic equipment spending is projected to grow 9.8% year-on-year to $66.6 billion in 2025 as companies like Intel, Samsung, and TSMC continue to spend on leading-edge production capacities. SEMI expects this segment to expand further in 2026 and 2027, reaching $75.2 billion as TSMC, Samsung, and others ramp production of AI accelerators, HPC processors, and premium mobile SoCs.

Although DRAM and NAND makers express reluctance to invest significantly in expansion of their production capacity, SEMI predicts that memory will experience a particularly strong rebound in the coming years. DRAM equipment sales are projected to rise 15.4% to $22.5 billion in 2025, then continue expanding in 2026 and 2027 as suppliers scale HBM production and transition to more advanced process technologies. Spending on 3D NAND manufacturing tools is expected to surge 45.4% to $14 billion in 2025, followed by growth to $15.7 billion in 2026 and $16.9 billion in 2027, driven by higher 3D NAND layer counts and capacity additions.

Back-end equipment

Back-end tools, which began recovering in 2024, is expected to maintain strong momentum.

Chip test equipment revenue is forecast to jump 48.1% to $11.2 billion in 2025, followed by additional growth of 12% in 2026 and 7.1% in 2027. Assembly and packaging (A&P) tools are projected to grow 19.6% to $6.4 billion in 2025 and continue to expand through 2027. SEMI attributes this trend to increasingly complex device architectures, the rapid uptake of advanced and heterogeneous packaging, and higher performance requirements for AI processors and HBM stacks.

China to remain the biggest market

From a geographic standpoint, China, Taiwan, and South Korea are expected to remain the largest markets for semiconductor equipment throughout the forecast period.

Even as growth moderates after 2026, China is projected to retain its leading position as domestic manufacturers invest in mature and select advanced nodes. Taiwan's elevated spending in 2025 reflects large-scale capacity additions for leading-edge AI and HPC logic chips (and probably memory), while South Korea's increases are expected to be driven by major investments in advanced memory technologies, including HBM.

Other regions are also expected to see increased spending in 2026 and 2027, though SEMI attributes this to government incentives, onshoring, and specialty capacity expansions.