With a grand opening ceremony, Micron last week opened the latest expansion of its 3D NAND fab in Singapore. It is the third facility Micron has in Singapore, besides Fab 10N and Fab 10X which produce the majority of its flash memory output. The expansion will support the upcoming 96-layer 3D NAND and beyond.
Micron does not expect the new expansion to add any new wafer capacity, in terms of wafers starts of per month. To understand this, it’s worth realizing that the 3D NAND roadmap has drastically changed the conventional notions of semiconductor scaling.
Traditional scaling in both memory (flash and DRAM) and logic (transistors) consisted of reducing the feature sizes, hence increasing density and ultimately the capacity of a chip. 3D NAND scaling, on the other hand, started on a more relaxed process node, but scaling up in the z-dimension. Initially at 24 and 32 layers, present state of the art 3D NAND technology is moving to 96 layers and beyond.
However, increasing the number of layers is not a free lunch. While the relaxed node has reduced the importance of lithography in NAND, other steps such as etching have become more crucial and are increasing the cycle time of a wafer as the number of layers increases. With some companies opting to divide the manufacturing process in multiple stacks (for example two stacks of 32 layers each), this furthers increases the cycle time.
So in order to maintain the wafer output after moving to more advanced processes, the number of manufacturing equipment machines has to be increased, which evidently requires extra cleanroom space. Micron says that the new expansion enables the company to transition to more advanced nodes, such as its upcoming 96-layer process, and expects the first output in the second half of the year. No financial metrics about the expansion were provided.
Micron and Intel, which collaborated through the IM Flash Technologies (IMFT), are in the midst of a split. The companies announced in early 2018 that they would cease co-development of 3D NAND after their third (96L) generation. The companies’ 3D NAND is currently based on the same floating gate technology that was common in 2D NAND, with Toshiba and Samsung using the other option, called charge trapping. Micron has disclosed that it would switch to charge trapping for its fourth generation.
Hard to imagine that photolithography could now be reliable enough — with regard to bit errors — to allow or 96 overlaying layers to be patterned and etched and still result in nominally working/reliable devices. I think it is rather amazing, all and all.
The price of SSDs, whether conventional or NVMe style, certainly has dropped precipitously in the last 12 months. Huge… to the point where spinning disks hardly have any market share left. I suppose it was inevitable. Still … remarkable.
Last, if my memory (ooh!) serves me, I believe there is STILL a glut in the world nonvolatile memory market. Certainly this won't be relieved in the snort-to-mid term by 96 layer devices coming to commonplace supply chain dynamics. Also, I don't foresee ANY upcoming gotta-have-terabytes-in-one's-tablet applications. None at all. Even for the most wickedly techno users, there are darned few Must-Have-Ubiquitous uses for terabyte sized databases. On one's tablet, or in one's smart-watch (LOL).