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Russian Chipmaker Preps to Develop 32-Core Elbrus Processors

MCST
(Image credit: MCST)

The Ministry of Industry and Trade of the Russian Federation has placed a bid to develop a 32-core processor based on the Elbrus VLIW-like architecture. The CPUs will be aimed at various applications, including servers, storage systems, and high-performance computing (HPC). The chip is set to be designed by the end of 2025 and will be made using 7nm or more advanced process technology. 

Following various HPC-related restrictions that two U.S. administrations imposed on China in recent years, the development of high-performance server CPUs received major boosts in China, Europe, and Russia. China seems to have a multifaceted processor strategy that includes CPUs based on Arm, MIPS, RISC-V, x86, and even proprietary architectures. European companies mostly use Arm architecture, though they also have access to MIPS as well as RISC-V. 

There are not many CPU designers in Russia, and the best known are Baikal Electronics, which uses Arm and MIPS for its client CPUs; KM211, which builds special-purpose CPUs, controllers, and FPGAs; and Moscow Center of SPARC Technologies (MCST), which designs CPUs based on its proprietary VLIW-like Elbrus architecture for CPUs aimed at HPC and mission-critical applications.  

Since MCST is essentially a state-owned company, it is funded by the government, so the Ministry of Industry and Trade has to place formal bids before funding MCST's R&D projects. This is exactly what happened this month when the ministry placed a bid to develop a 32-core Elbrus-32C processor for about 7.4893 billion rubles ($98.7 million). MCST will have to formally submit its proposal by December 10, 2020. 

At present, MCST is developing 12- and 16-core Elbrus processors projected to debut sometime in 2021, if all goes well. The company intends to finish the development of its 32-core Elbrus CPUS by late 2025. 

Based on preliminary information about the 32-core Elbrus processor, the chip will feature at least 64 MB of cache, a six-channel DDR5 memory controller supporting at least 2 TB of memory, a bandwidth of at least 170 GB/s, and at least 64 PCIe 5.0 lanes and various AI accelerators.  

32-core Elbrus processors will be used for servers, storage devices, and HPC systems used by scientists, aerospace agencies, and energy companies. 

Sources: 3DNewsMCST