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Stretching The Limits Of Lithography: MIT Creates 25 Nm Structures

By - Source: Tom's Hardware US | B 7 comments

Cambridge (MA) - Researchers from the Massachusetts Institute of Technology (MIT) have found a way to develop 25 nm chip structures with a common lithography process, indicating that chip manufacturers will be able to push out the adoption of an expensive Extreme Ultraviolet (EUV) lithography manufacturing process by another chip generation.

The semiconductor industry has been talking about the end of the 193 nm deep-ultraviolet (DUV) lithography technique, which has been in place since 1995 for more than 10 years. In the late 1990s, it was believed that the scalability of the technology would run out of steam by 2003 and would have to be replaced by EUV with the switch to sub-100 nm structures. Today we are at 45 nm and the industry is still using DUV to print its chips. Both Intel and IBM are experimenting with EUV and indicated that a switch may now be likely in 2013 when the industry will hit 16 nm structures.

Lithography, which is the process used to print circuits onto computer chips. Chip lithography is very similar to traditional silk-screening, but semiconductor firms use light (193 nm in DUV and 13.5 nm in EUV) instead of ink to print microscopic circuits onto their products.

New research results published by the MIT now suggest that there may be even more room left in common lithography. The research team said it has created 25 nm lines using interference lithography, sometimes also referred to as holographic lithography. While IBM has come up with 22 nm chips before and Intel’s 22 nm research is running at full speed in Oregon, the MIT result is impressive because of its relatively simple manufacturing technique. According to the researchers, the control of the lithographic imaging process is no longer the limiting step. Instead, the material issues such as line sidewall roughness appear to be now the major problems that need to be solved before smaller structures can be created. However, the scientists concluded that "there’s still a lot of room left for scale shrinkage in optical lithography. We don’t see any insurmountable roadblocks just yet."

Interference lithography itself, however, has substantial downsides. The technology is limited to patterning arrayed features only, which makes the creation of more complex chips with arbitrarily shaped patterns produced with this method impossible. On the upside, patterned chip can be created very quickly without loss of focus - and lots of commodity chips in fact use periodic patterns. The MIT researchers believe that their new technique could "pave the way for next-generation computer memory and integrated-circuit chips, as well as advanced solar cells and other devices."

Smaller, cheaper chips - sounds good to us.

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  • -2 Hide
    Pei-chen , July 9, 2008 2:02 PM
    The world will end by 2012 so I find EUV pointlless. LOL, I can't believe my old Pentium 120 is a 600 nm ship.
  • 0 Hide
    Anonymous , July 9, 2008 7:46 PM
    ^ why will the world end in 2012? i'm interested to know why...

    anyway this is very fascinating to me
  • 0 Hide
    Pei-chen , July 10, 2008 12:52 AM
    thogrom^ why will the world end in 2012? i'm interested to know why...anyway this is very fascinating to me

    Some esoteric American centuries ago predicted the world will end on Dec. 12, 2012. Some idiotic American now believe their story.
  • 1 Hide
    krowbar , July 10, 2008 4:55 AM
    There is no room for religious nonsense on this website, take your superstitions elsewhere.
  • 0 Hide
    Anonymous , July 10, 2008 8:13 AM
    Not to rain on MIT's parade (I'm even a former alumn)... but a few things to put this into perspective.

    25nm features is not really very impressive. The smallest feature on the 32nm node is not much larger than this .(note: there are features smaller than 32nm on the 32nm node and this is true in all recent tech nodes).

    Lithograph dictating your design/layout? While you could potentially get around this, it would certainly cost either die space or performance.

    So basically the researches have come up with a cheap way to pattern the 32nm node with significant design restrictions (and no mention of other key lithography constraints like registration and overlay capabilities).
  • 0 Hide
    Pei-chen , July 14, 2008 4:44 AM
    krowbarThere is no room for religious nonsense on this website, take your superstitions elsewhere.

    Read of post above you'll know I don't believe in that Aztec non-sense.
  • 0 Hide
    IggyB , July 15, 2008 7:59 AM
    AMD better be a step ahead of what maybe their prototype to answer this...