Report: Sub-40 nm Processes Account for 27% of Global Wafer Capacity

At the end of 2012, sub-40 nm processes accounted for 27 percent of global wafer capacity, followed by 2.18 percent for 80 nm to 0.2µ “mature process nodes” and 18.8 percent for 40 nm to 60 nm geometries.

The increased prevalence of 40 nm or smaller geometries has been attributed to its use in high-density DRAM, which are typically built using 30 nm-class to 20 nm-class process technologies; high-density flash memory devices that are based on 20 nm-class to 10 nm-class processes; and high-performance microprocessors and advanced ASIC/ASSP/FPGA devices based on 32 nm, 28 nm or 22 nm technologies.

IC Insights further noted that Samsung Electronics was the largest supplier of ICs built using sub-40 nm geometries at the end of 2012 followed closely by Intel, Toshiba / SanDisk, SK Hynix and Micron Technology. Additionally, they noted that process technologies with geometries greater than 0.4-micron maintain "a fairly large share" of the global installed capacity due to large quantities of commodity-type devices such as standard analog and general-purpose logic ICs.