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Intel Disables TSX for More CPUs via Microcode Updates

Intel CPU
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Intel users will soon trade performance for security once again. Phoronix reported that recent microcode updates would disable Intel Transactional Synchronization Extension (TSX) by default on the company's 6th, 7th, and 8th Gen processors. Disabling the feature is supposed to make those CPUs more secure, but it's also expected to result in worse performance in tasks that benefited from using TSX.

Phoronix said these updates were prompted by a memory ordering issue in TSX. A whitepaper (PDF) suggests Intel has been aware of the issue since June 2018, and the company released microcode updates to address the flaw in October 2018. Still, it's taken almost three years to release updates that disable TSX by default. Those updates were included with Intel Platform Update 2021.1 when it debuted on June 8.

"Workloads that were benefited from Intel TSX might experience a change in performance," Intel said on June 12. It also said that "some advanced users of performance monitoring (Perfmon) may need to change their collection scripts and methodologies" due to the microcode updates. The company didn't offer more information about the performance hit to tasks affected by these changes.

But there's good news: Intel said that it "does not expect these microcode updates to affect users who do not use the [Performance Monitoring Unit], or who only use updated PMU drivers and tools," though it does "recommend that PMU driver developers and performance tool developers follow the guidance in this document." The average person is unlikely to notice significant changes in performance.

Developers have already prepared the Linux kernel for these microcode updates. Phoronix noted that patches meant for Linux 5.14 made this change: "Add support for new Intel microcode deprecating TSX on some models and do not enable kernel workarounds for those CPUs when TSX transactions always abort, as a result of that microcode update." That support might also make its way to Linux 5.13.