San Francisco (CA) - Researchers from the Massachusetts Institute of Technology (MIT) and Texas Instruments (TI) unveiled a new low-voltage concept for a system-on-a-chip (SoC), which could lead to cellphones and other portable devices that consume much less power than what is in use today.
Researchers believe that the new chip design could eventually enable portable electronics that is up to ten times more power efficient than present technology. The "proof-of-concept" discussed at ISSCC 2008 is a 65 nm chip that integrates a switched capacitor DC-DC converter with a 16-bit microcontroller and 128 kb SRAM. Capable of running at 0.3 volts, instead of the industry 1 or 0.8 volts, the chip achieves very low power levels: In standby mode, the chip consumes about 1 microwatt (μW). Joyce Kwong, a graduate student in MIT's Department of Electrical Engineering and Computer Science (EECS), told TG Daily that the prototype chip consumed about 12 μW when "executing one program" at 0.5 volts.
Simply reducing the voltage in the chip is not really a trivial task, since general semiconductors have been designed to operate at much higher voltage levels. "Memory and logic circuits have to be redesigned to operate at very low power supply voltages," said Anantha Chandrakasan, Kwong's colleague at MIT.
