Ventana's 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo

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By Matthew Connatser
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Chiplets and double the cores

The Ventana Veryon V2 RISC-V CPU.
(Image credit: Ventana Micro Systems)

The age of full-fledged RISC-V data center CPUs is nearly upon us, as Ventana's 192-core Veryon V2 is coming in 2024 (via ServeTheHome). Ventana, founded in 2018, claims the Veryon V2 edges ahead of AMD's Genoa and Bergamo Epyc CPUs. However, the company foresees much bigger victories down the line with its domain-specific accelerator (or DSA) chiplets, which Ventana forecasts will deliver large performance boosts compared to typical CPUs.

RISC-V is an open standard (previously open source) CPU architecture that has been used in many applications but is just now popping up in servers. The Veryon V2 will be Ventana's first server CPUs to market, as the Veryon V1 has seemingly been canceled and skipped over.

Compared to V1, V2 has more cores and cache per chiplet, the slightly newer 4nm node from TSMC instead of the 5nm node, and standard RISC-V RVA23 vector instructions, as Ventana originally planned on using its own instructions. However, Ventana wants its CPUs to follow RISC-V standards to improve hardware-software compatibility. To that end, it has also added RISC-V Software Ecosystem (or RISE) support to the V2.

The Veyron V2 takes a leaf out of AMD's server CPUs by using a chiplet design featuring an I/O hub chiplet and compute chiplets with CPU cores. However, Ventana also offers DSA chiplets that can accelerate specific workloads, and the company claims this will offer vastly higher performance than what is possible with a traditional CPU without hardware acceleration. Additionally, the I/O hub can also be customized with hardware acceleration, which AMD also doesn't offer.

Ventana claims its approach to CPU design in using chiplets and DSA hardware will reduce development time to less than a year and costs to less than $25 million, and that it would take twice as many x86 or ARM CPUs to match the Veryon V2. Take this all with a grain of salt, though, as Ventana's server CPU will arrive in 2024, and probably the latter half of 2024 at that, according to ServeTheHome.

Matthew Connatser
Matthew Connatser

Matthew Connatser is a freelancing writer for Tom's Hardware US. He writes articles about CPUs, GPUs, SSDs, and computers in general.

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9 Comments Comment from the forums
  • Amdlova
    Intel will show somenthing with risc V...
    The x86 server market will be mixed with P cores E cores and risc cores. maybe some Gpu multi purpose in the future...
    Reply
  • atomicWAR
    I have found Intel's interest in Risc V as rather eye opening. I can only assume they have either big plans with it or want to make sure they can counter it with x86.
    Amdlova said:
    Intel will show somenthing with risc V...
    The x86 server market will be mixed with P cores E cores and risc cores. maybe some Gpu multi purpose in the future...
    This would be neat to see but with the difference in their instruction sets I imagine some type of translation layer or emulation would need to happen unless OSes and apps directly incorporated them. Something I find unlikely but not impossible. Regardless unless they are running native code as you know emulation/translation layers slow said CPUs performance. Time will tell and I am certainly interested to see how things shake out.
    Reply
  • sygreenblum
    atomicWAR said:
    I have found Intel's interest in Risc V as rather eye opening. I can only assume they have either big plans with it or want to make sure they can counter it with x86.

    This would be neat to see but with the difference in their instruction sets I imagine some type of translation layer or emulation would need to happen unless OSes and apps directed incorporated them. Something I find unlikely but not impossible. Regardless unless they are running native code as you know emulation/translation layers slow said CPUs performance. Time will tell and I am certainly interested to see how things shake out.
    It's possible but yuck. Reminds me of Transmeta. Given Apple did a better job when they transitioned to the arm instruction set but they have control of the whole ecosystem and even then it wasn't without its problems and was always a good deal slower than native. I don't think this is Intel's plan.

    I don't know what Intel has planned with Risc V but my assumption was they'd start with infrastructure products like data center switches and routers, set-top/CMTS, cable modems, and PON/DSL, Ethernet NICs, filters and amplifiers, wireless connectivity solutions, embedded processors and low cost, low power markets. In other words point their broadside cannons at Broadcom.
    Reply
  • NinoPino
    Amdlova said:
    Intel will show somenthing with risc V...
    The x86 server market will be mixed with P cores E cores and risc cores. maybe some Gpu multi purpose in the future...
    If you mean a CPU with mixed x86-RiscV, I doubt. A CPU like this should divide total number of cores between x86 and RiscV so it would be weak on both sides.
    Reply
  • NinoPino
    sygreenblum said:
    I don't know what Intel has planned with Risc V but my assumption was they'd start with infrastructure products like data center switches and routers, set-top/CMTS, cable modems, and PON/DSL, Ethernet NICs, filters and amplifiers, wireless connectivity solutions, embedded processors and low cost, low power markets. In other words point their broadside cannons at Broadcom.
    Intel just leaved networking, storage and other markets to concentrate funds on CPUs and foundry.
    Thinking of businesses that could immediately use RiscV without hurting x86 business, my mind go to phone SOCs and GPUs for datacenters, in the style of H100/MI300.
    Reply
  • bit_user
    RISC-V is an open standard (previously open source) CPU architecture
    LOL, what??? Do you even understand what you're saying?

    No, just "open standard". Period.
    Reply
  • Amdlova
    NinoPino said:
    If you mean a CPU with mixed x86-RiscV, I doubt. A CPU like this should divide total number of cores between x86 and RiscV so it would be weak on both sides.
    With this glued tech, you can mix all cores and mix some strength and weakness... new set of instructions for mixed use... only matters it's die size :)
    Reply
  • bit_user
    Amdlova said:
    With this glued tech, you can mix all cores and mix some strength and weakness... new set of instructions for mixed use... only matters it's die size :)
    Yes, but no - it won't happen. It's too complex for the OS to span multiple ISAs for the value it provides, especially when emulation works pretty well for most purposes. I don't see it happening.

    What we could see is some SoCs having a mix of wider, slower cores and faster, narrow cores:
    https://www.tomshardware.com/pc-components/cpus/imagination-and-ventana-to-build-a-risc-v-cpu-gpu-platform
    The wider, slow ones could run GPU and AI code. Maybe also some other threads, in a pinch.
    Reply
  • Findecanor
    bit_user said:
    What we could see is some SoCs having a mix of wider, slower cores and faster, narrow cores:
    The wider, slow ones could run GPU and AI code. Maybe also some other threads, in a pinch.
    That already exists, sort of.

    The Sophgo SG2380 has 16 × SiFive P670 cores (4-issue OoO, 128-bit Vector), and 8 × SiFive X280 cores (2-issue in-order, 512-bit Vector registers) with a TPU.
    However, it does not look as if there is a cache-coherency lines between the two core clusters which would allow them to run processes as if the same system.
    Reply