San Jose (CA) - The Semiconductor Industry Association (SIA) announced that it has initiated a nanoelectronics research initiative to keep Moore's Law in force beyond limits of current microchip technology.
Nanotechnology, already a major industry trend, has caught up with the SIA, the industry organization of virtually all semiconductor manufacturers in the US. According to a statement released Wednesday, the group believes that "the laws of physics will eventually limit the implementation of CMOS scaling technology" and that nanotechnology will be key to uphold Moore's Law.
Moore's Law refers to an observation of Intel co-founder Gordon Moore in 1965 which states that the number of transistors that can be placed on a silicon chip will double approximately every 24 months. Scaling memory technology currently down to 90 nm and processors to 65 nm, several manufacturers have mentioned that they cannot be certain that semiconductors can be shrunk beyond the 20 nm level with current manufacturing processes.
"We are rapidly approaching the time when the laws of physics will limit our implementation of Moore's Law," said SIA President George Scalise. "Most scientists now agree that our ability to continue the scaling of CMOS technology - the dominant technology of the semiconductor industry for the past 20 years - will reach its ultimate limit sometime before 2020. We are now in a worldwide race to develop new technologies that will enable progress in semiconductor devices to continue at the pace we have seen for nearly 40 years."
"The Nanoelectronics Research Initiative (NRI) will attempt to link research efforts by leading universities, the federal government, and the US semiconductor industry in a mission-oriented effort to continue the rate of progress that has prevailed since the mid 1960s," Scalise said.
According to the SIA, the NRI will bring universities, the federal government and the US semiconductor industry together to conduct research on materials, device structures and assembly methods for microelectronic devices with feature sizes smaller than 10 nanometers (10/1,000,000,000ths of a meter).
"We are still in the very early stages of launching the NRI," said Scalise. "Our first order of business is to get consensus among all parties on defining and prioritizing the specific technical challenges on which to focus research. The only certainty at this point is that the existing technology, materials and production methods simply won't work when feature sizes must be smaller than 10 nanometers."
Parts of the industry still disagree on the definition on how nanotechnology actually can be defined. Most companies including Intel at this time stick to the US government definition, which states that any structures smaller than 100 nm are considered nanotechnology, whereas single manufacturers such as Infineon believe that nanotechnology goes beyond scaling and will involve a new type of design and manufacturing - such as adding building layers to chips in contrast to today's approach of shrinking existing structures.
According to SIA spokesman John Greenagel, there is apparently "no disagreement" between SIA members anymore on how nanotechnology will be defined. Instead, the members believe that anything below 10 nm is considered "nanotechnology" and will require a new development and production process: "The manufacturing facility in 2020 will look nothing like the facility in 2005," he said.
