Fast Page Mode
Fast Page mode improved upon the original page mode by eliminating the column address setup time during the page cycle. This was accomplished by activating the column address buffers on the falling edge of RAS\ (rather than CAS\). Since RAS\ remains low for the entire page cycle, this acts as a transparent latch when CAS\ is high, and allows address setup to occur as soon as the column address is valid, rather than waiting for CAS\ to fall.
Fast Page mode became the most widely used access method for DRAMs, and is still used on many systems. The benefit of FPM memory is reduced power consumption, mainly because sense and restore current is not necessary during page mode access. Though FPM was a major innovation, there are still some drawbacks. The most significant is that the output buffers turn off when CAS\ goes high. The minimum cycle time is 5ns before the output buffers turn off, which essentially adds at least 5ns to the cycle time.
Today, FPM memory is the least desirable of all available DRAM memory. You should only consider using this if it is either free, or your system does not support any of the later memory types (such as a 486 based system). Typical timings are 6-3-3-3 (initial latency of 3 clocks, with a 3-clock page access). Due to the limited demand, FPM is actually more expensive now than most of the faster memories now available.
