Apple filed a patent application that describes an approach to dynamically adjust the number of bits stored in a non-volatile NAND flash memory cell.
According to Apple, single-level cell (SLC) as well as multi-level cell (MLC) programming operations could be used to be able to allocate a different number of bits to cells.
The purpose of the invention is to enable a system to balance its mass storage for performance, reliability and storage capacity needs. Apple says that the technology would allow for a portion of a flash memory chip to be used as CLC and another as MLC chip. SLC flash memory tends to provide greater reliability and performance, while MLC offers greater capacity.
From the patent: "The host can further determine whether to access the memory location as a single-level cell location or multi-level cell location. For example, the host can make this determination based on the desired storage reliability, storage performance, or storage speed. Thus, the host can use any suitable number of bits per cell when accessing the memory location regardless or independently of the number of bits per cell previously used for the same memory location. In other words, after each erase cycle on the memory location, the host can newly assign the memory location as an SLC or MLC memory location based on current needs or preferences."
The patent was already filed by Apple on February 25, 2010, but only recently released by the US Patent and Trademark Office. The idea is not entirely new and closely resembles a paper presented by Samsung at the 2009 Usenix conference. Back then, Samsung engineers described their FlexFS as a flexible flash file system for MLC NAND flash memory, which would "takes advantage of the dynamic reconfiguration utility of MLC flash memory". As Apple's idea, FlexFS divides MLC flash memory into SLC and MLC regions -- and is able to change the size of those regions to adjust for different requirements over time.