Macworld is reporting that Intel plans to detail an eight-core Xeon processor at the International Solid-State Circuits Conference in San Francisco next month.
The information about the upcoming reveal is scarce at best, however Macworld does say that Intel executives will discuss an eight-core, 16-thread Xeon processor manufactured with a 45-nanometer process. Naturally, Intel fired back at the website, saying that although the chip manufacturer is presenting 16 papers at ISSCC, it didn't have anything further to share in regards to the Xeon rumor. If the processor indeed comes to light at the conference, this will be the company's first eight-core chip.
Macworld speculates that the impending eight-core Xeon will probably be Intel's Nehalem EP processor, an upcoming chip designed for dual-socket workstations and servers. Scheduled for a release during early 2009, the Nehalem EP processor will use Intel's Quick Path Interconnect, eliminating the front-side bus and allow more data to flow between the processor and the other components installed in the system. The Nehalem EP processor will also include an integrated memory controller as well.
Last week, Intel reported that restructuring plans included the termination of five older factories, affecting between 5,000 and 6,000 workers worldwide, although some would stay on board and shift to other facilities. The company said restructuring would begin immediately and continue until the end of 2009. The affected facilities include two assembly test facilities in Penang, Malaysia and one in Cavite, Philippines. Production will halt at Fab 20 located in Hillsboro, Oregon; wafer production operations will cease at the D2 facility in Santa Clara, California.
Wednesday the company said it planned to cut 100 to 200 additional jobs at its Rio Rancho plant in New Mexico within the next few months. However, Intel reassured that although it will consolidate and streamline older operations, the restructuring would no impact the deployment of 45-nm and 32-nm manufacturing capacity.
The International Solid-State Circuits Conference will take place on February 8-12 in San Francisco. Intel will make its presentation during Session 3 at 1:30 PM PST, Monday, February 9th, entitled "A 45nm 8-Core enterprise Xeon Processor."
"An 8-core 16-thread enterprise Xeon processor has 2.3B transistors in 9M 45nm CMOS," reads the Conference program (PDF). "The I/O links the use per-lane TX and RX compensation to enable operation up to 6.4GT/s. Vertical and horizontal splines keep the undercore clock skew under 19p before engaging the compensation. Core and cache shut-off techniques are used to minimize leakage."
Intel will also make other presentations at 2 pm (A Family of 45nm IA Processors) and 3:15pm (Dynamic Frequency-Switching Clock System on a Quad-Core Itanium Processor."
I thought the reason Nehalem has a rectangular die and not square is so Intel can fit two into LGA 1366. It is also the reason LGA 1366 being bigger than LGA 775. Also, why the 8-core Xeon has 2.3billion transistors when i7 only has 731million transistors?
3. The rest of the other stuff needed for HT,etc.
I can only speculate about the fact that processors never seem to be square. Know that song "It's hip to be square."?
The Xeon may be an LGA 1567 chip.
I don't think that Intel can do a dual-die MCM with the Nehalem-EP since it has an IMC. Nobody in the x86 world at least has made an MCM with an IMC- all MCMs have been on FSB-equipped chips since the FSB's shared-bus nature makes it easy to tack two dies together in a package. Doing so with an IMC-equipped chip requires a die-to-die bus to be run to get die-to-die I/O and I don't know if QPI can do that. AMD is slated to be the first to try an MCM with IMCs with its dual-6-core-die "Magny-Cours" in 2010.
The Nehalem-EPs are LGA1567, not LGA1366. The reason LGA1366's socket was large is that it has a lot of lands and Intel also wanted to be able to have a large IHS and heatsink to dissipate the high heat output of overclocked i7s.
The 8-core Xeon has 2.3 billion transistors because it has eight cores versus four for the Bloomfield and likely has more more than 2 MB of L3 per core that the Bloomfield does. Intel likes to tack a lot of L3 onto their Xeons, particularly the MP versions, and L3 cache can eat up a bunch of transistors.
Not always ... Core2 E8400 = Xeon E3110 ... same chip, same cache.
It's not a matter of changing the conditions under which existing code runs. Software has to be written correctly to be highly parallel-izable, and a large portion of the software out there isn't.
I'm going to stretch and say that a real answer to this question falls out of the scope of an internet message board.
unless it has a really low Vcore or is made to run really hot..