Intel boasts some of the best CPUs available, yet an even better product is coming. Hardware leaker chi11eddog, known for his solid track record, has disclosed what are rumored to be the specifications for Intel's next-generation Nova Lake desktop processors, which are expected to succeed the Core Ultra 200S (codenamed Arrow Lake) series.
Nova Lake, potentially branded as Core Ultra 300S, differs significantly from Arrow Lake. While Arrow Lake is built with Lion Cove P-cores and Skymont E-cores, Nova Lake is expected to use cutting-edge Coyote Cove P-cores along with Arctic Wolf E-cores. Intel is shaking things up with Nova Lake, reportedly launching its LPE-cores on desktops for the first time. We were first introduced to LPE-cores in Intel's mobile Core Ultra Series 1 (codenamed Meteor Lake) processors.
LPE-cores are a branch of the E-cores, meaning the LPE-cores in Nova Lake are just an optimized version of the Arctic Wolf E-cores. Nova Lake's LPE-cores are believed to be integrated within the SoC tile and represent the lowest tier in the core hierarchy. As a result, these LPE-cores are designed to manage extremely low-power workloads or background tasks. By utilizing different cores for specific workloads, Intel can enhance power efficiency in Nova Lake.
As reported by the hardware leaker, Nova Lake's flagship Core Ultra 9 chip may feature up to 52 cores, over twice the current Core Ultra 9 285K. However, this increase is due to a doubling of P-cores and E-cores and the inclusion of four more LPE-cores. Naturally, adding these cores comes at a cost, so the 52-core Nova Lake processor has a 20% higher Processor Base Power (PBP) than its predecessor.
Intel Nova Lake Processor Specifications*
Processor |
P-cores |
E-cores |
LPE-cores |
PBP (W) |
|---|---|---|---|---|
Core Ultra 9 |
16 |
32 |
4 |
150 |
Core Ultra 9 285K |
8 |
16 |
0 |
125 |
Core Ultra 7 |
14 |
24 |
4 |
150 |
Core Ultra 7 265K |
8 |
12 |
0 |
125 |
Core Ultra 5 |
8 |
16 |
4 |
125 |
Core Ultra 5 |
8 |
12 |
4 |
125 |
Core Ultra 5 245K |
6 |
8 |
0 |
125 |
Core Ultra 5 |
6 |
8 |
4 |
125 |
Core Ultra 5 225 |
6 |
4 |
0 |
65 |
Core Ultra 3 |
4 |
8 |
4 |
65 |
Core Ultra 3 |
4 |
4 |
4 |
65 |
*Specifications are unconfirmed.
The Core Ultra 7 SKU also demonstrates a significant upgrade over the existing Core Ultra 7 265K. Intel might increase the P-core count by 75%, double the E-cores, and include four additional LPE-cores. Notably, the PBP has risen by 20% to support this upgrade, now aligning with the PBP of the Core Ultra 9 SKU.
The Core Ultra 5 model, historically Intel's best-selling product, will allegedly come in three SKUs to appeal to different budgets. The top SKU seems to feature eight P-cores, 16 E-cores, and four LPE-cores. The middle SKU has two fewer E-cores, whereas the lowest SKU has two and four less P-cores and E-cores, respectively.
Get Tom's Hardware's best news and in-depth reviews, straight to your inbox.
Compared to the Core Ultra 5 245K, the Nova Lake model seems to have 33% more P-cores and 50% more E-cores, along with four LPE-cores. Intel appears to have kept the 125W PBP consistent across all three Core Ultra 5 Nova Lake variants to align with the Core Ultra 5 245K.
Intel had previously forsaken the entry-level market with Arrow Lake, leaving the void to be filled with previous-generation chips. Nova Lake sees the return of the Core i3 tier, or rather Core Ultra 3, under this new branding. The chipmaker is reportedly working on two Core Ultra 3 chips: one with four P-cores, eight E-cores, and four LPE-cores, and the other with four fewer E-cores. Only the Core Ultra 3 SKUs will have a 65W PBP, as there doesn't seem to be 65W versions of the Core Ultra 5.
Nova Lake is rumoredly to leverage Intel's Xe3 (codenamed Celestial) and Xe4 (codenamed Druid) IPs for its integrated graphics engine. Given the significant changes, Nova Lake chips reportedly require the new LGA1954 socket, while cooler compatibility appears backward compatible with LGA1851 coolers.
Earlier this year, Intel confirmed that Nova Lake is on track for a 2026 release. There is no specific date, but barring any setbacks, Nova Lake should be ready to compete with AMD's next-generation Zen 6 processors.
Follow Tom's Hardware on Google News to get our up-to-date news, analysis, and reviews in your feeds. Make sure to click the Follow button.
Zhiye Liu is a news editor, memory reviewer, and SSD tester at Tom’s Hardware. Although he loves everything that’s hardware, he has a soft spot for CPUs, GPUs, and RAM.
-
Notton I would love to see the cache size in the product stack.Reply
Core count and clock speed is only part of what makes a good CPU.
Part of the reason Ryzen 7 9800X3D performs so well in games, while Core 5 and 7 do not is their cache size. -
Neilbob Looking very hard at that comparison table.Reply
Seeing the 285K.
Wondering when they gave it 16 P-cores... -
Thunder64 ReplyNeilbob said:Looking very hard at that comparison table.
Seeing the 285K.
Wondering when they gave it 16 P-cores...
Didn't you see the note?
*Specifications are unconfirmed.
-
TerryLaze Reply
Yeah but it's also how you destroy your sales so intel won't do anything like the x3d.Notton said:I would love to see the cache size in the product stack.
Core count and clock speed is only part of what makes a good CPU.
Part of the reason Ryzen 7 9800X3D performs so well in games, while Core 5 and 7 do not is their cache size.
But if all of the e cores and p cores are still on the same chiplet, then the sheer number of cores will mean a decently higher amount of cache available, just nowhere near x3d. -
Neilbob Reply
Whoops, silly me, thinking the 285K was a known quantity! :DThunder64 said:Didn't you see the note?
Also, I noticed it got fixed already. Ah well, it was fun while it lasted. -
thestryker Reply
I'd be surprised if it was much of a divergence from current designs. I think the biggest question would be how the L3 cache functions on the top two SKUs since those are purported to use two Compute Tiles. All of the multi-die Xeon parts have used EMIB, but to my knowledge no consumer parts have utilized it. If ARL is any indication using Foveros for this likely wouldn't be viable for shared L3.Notton said:I would love to see the cache size in the product stack.
If we assume L3 cache doesn't drop from the last two generations and the Compute Tiles behave as a single unit that would put the top SKU at minimum 72MB. -
ingtar33 so if i read this right, they're downgrading the E cores to the mobile version of the E core in order to save on power, so they can up the P core count because, you know, they did away with hyperthreading so they need more physical cores to perform, and likely need to figure out how to clock it up without blowing up the ringbus like they did with the 14000 chips.Reply
I guarantee the upped core count is real. because all of intel's marketting will claim something like a 50% boost in multithread performance, all obtained with a 70% boost in core count. this has been intel's MO for years now. up the core count, claim higher performance, while pretending it's an apple to apples comparison when in reality it's an apples to oranges comparison and means nothing.
still if they can give all those core at the same price as their current flagship, that will be a tremendous value to someone out there. it's not like the E cores are trash. and when you pool enough together you get some very good results. i just hope this doesn't come with the burnt out ringbus problem they had before. -
thestryker Reply
You are not reading it right. According to current leaks NVL-S uses 8P/16E Compute Tiles just like ARL-S with the Ultra 7/9 having two Compute Tiles. They are also supposed to have 4 LPE cores in the SoC tile like the mobile parts have had.ingtar33 said:so if i read this right, they're downgrading the E cores to the mobile version of the E core in order to save on power, so they can up the P core count because, you know, they did away with hyperthreading so they need more physical cores to perform, and likely need to figure out how to clock it up without blowing up the ringbus like they did with the 14000 chips.
Preliminary silicon configs are:
52 (16+32+4)
28 (8+16+4)
16 (4+8+4)
https://nitter.poast.org/jaykihn0/status/1887830497964769515#m -
thestryker Was thinking some more about the configurations and additional details from Jaykihn.Reply
The 9950X (16c/32t) and 285K (8P/16E/24t) are largely the same (ignoring outliers) outside of gaming. Should the scaling of Zen 6 and NVL be similar and AMD moves to 12 core CCDs a dual CCD configuration (24c/48t) wouldn't be able to keep up with the full 2 Compute Tile (16P/32E/48t) NVL configuration.
Another oddity is the PCIe configuration being reported. 32x PCIe 5.0/16x PCIe 4.0 (PCIe 5.0 x4 DMI) seems like a really odd choice if it's the entire stack and not just the Ultra 7/9. ARL has 20x PCIe 5.0/4x PCIe 4.0 (PCIe 4.0 x8 DMI) though it does also have 2 Thunderbolt ports built in which can run PCIe 4.0. Even if some of those reported PCIe 4.0 lanes are being used for connectivity it's significantly more than we've seen on a client part. Assuming there are PCIe 5.0 M.2 slots that means two full x16 slots aren't necessarily available despite 32 lanes.
edit: Jaykihn released the platform information and with PCIe 5.0 lanes being available off the chipset it's unfortunate they didn't maintain 8 lanes the current ones have when upgrading to PCIe 5.0 DMI:
24 PCIe 5.0 lanes
Intel would also be enabling a 4/4/4/4 PCIe split for what I believe is the first time in a client platform.
4 PCIe 5.0 DMI lanes
16 PCIe 4.0 chipset lanes
8 PCIe 5.0 chipset lanes
https://nitter.poast.org/jaykihn0/status/1934778035611554165#m
If the connectivity is just the top two SKUs and the theoretical CPU performance are on point I could almost see this as somewhat of a return of HEDT minus the memory bus. If course this would also likely mean the Ultra 9 would be $800-1000.
If the performance scales like current Intel and AMD CPUs I could easily see the Ultra 9 going for $800-1000.