On Monday PCI-SIG, the consortium you probably know best for the PCI and PCI Express interfaces, outlined its new Mobile PCIe (or M-PCIe) specification for emerging thin laptop, tablet, and smartphone platforms. It also introduced its M.2 specification, a next-generation form factor for thin and ultra-light platforms, and detailed PCIe 3.1, PCIe 4.0, and a Thunderbolt competitor called PCIe OCuLink.
According to the PCI-SIG, the new M-PCIe spec enables PCIe architecture to operate over the MIPI Alliance M-PHY physical layer technology. That means decades of PC-oriented innovations will carry over to upcoming tablets, smartphones, and thin laptops. It also means interoperability and a consistent user experience across multiple platforms.
The M-PCIe spec provides power optimization for short channel mobile platform usage, and scalable performance using MIPI M-PHY high-speed gears 1 (1.25 to 1.45 Gb/s), 2 (2.5 to 2.9 Gb/s) and 3 (5.0 to 5.8 Gb/s). The group said that the M-PHY spec, adopted by the mobile industry, is a proven tech that meets low-power needs of handheld systems. One physical layer for multiple uses preserves investments and expedites time to market.
"Our collaboration with the PCI-SIG on the new M-PCIe specification will provide users the best of all worlds, drastically reduced product development and validation cycles, and access to a truly mobile focused physical layer interface technology," said Joel Huloux, chairman of the MIPI Alliance.
In a diagram provided on Monday (shown below), the M-PCIe/M-PHY combo is used between the SoC and the WLAN/WiGig/WirelessHD component, between the SoC and the modem, and between the SoC and companion or bridge chip. Connections using M-PHY-only reside between the SoC and camera, the SoC and display, the SoC and mass storage, and the modem and RFIC.
As for the M.2 spec, it will serve as a natural transition from the MiniCard and Half MiniCard to a smaller form factor in both size and volume. It will have the flexibility to support high-end performance and provide scalable speed to power-constrained platforms. The spec is also designed as a turnable I/O technology for developers to create a better balance between power and performance. It will support multiple technologies, including Wi-Fi, Bluetooth, SSD, and WWAN.
The M.2 specification is currently at revision 0.7a and is anticipated to be released in Q4 2013. The M-PCIe specification is now available on the PCI-SIG website. ODMs wanting to take advantage of M-PCIe technology need to be members of both PCI-SIG and MIPI Alliance to access licensing rights, membership benefits, and specification evolutions.
The PCIe OCuLink cable spec was also introduced on Monday, a small cable form factor optimized for internal (PCIe-attached storage) applications and external enclosures. Undoubtedly a Thunderbolt competitor, the spec will include a data rate starting at 8 Gb/s with headroom to scale higher, an independent reference clock with SSC technology, and one external and one internal connector support for up to four PCIe lanes.
The group said that both copper and optical cables are in development, and all cables will support 8 GT/s, providing up to 32 Gb/s in each direction within a four lane configuration. PCIe OCuLink is currently at revision 0.7, and product adoption is targeted for the first half of 2014.
Also revealed was the PCIe 3.1 spec, which consolidates numerous protocol extensions and functionality into three "buckets" including power, performance, and functionality. In the power bucket, the group combines M-PCIe and L1 power management substrates with a CLKREQ# signal. For performance, enhanced downstream port containment and lightweight notification protocol extensions are grouped together. And for functionality, the spec groups together precision time measurement, a separate refclk with independent SSC architecture, and the process address space ID. This spec will be launched later this year, the PCI-SIG said.
Finally, the group revealed the PCIe 4.0 spec, anticipated to offer a transfer rate of 16 GT/s, and address big data applications pushing for increased bandwidth at a low cost. It will be ideal for servers, workstations, and high-performance computing markets, most notably. The spec preserves backward compatibility with previous PCIe versions, and also provides an increase in clock rates thus enabling narrower link width implementations and reduced costs through pin production.
PCIe 4.0 revision 0.5 is targeted for Q1 2014 and revision 0.9 in Q1 2015.