There are dozens of solid-state drives with a PCIe 5.0 interface over at Computex 2025, and they no longer surprise us; however, we have seen a drive that features a PCIe 6.0 x4 interface and can potentially boast a 30.25 GB/s sequential read and write speed at the trade show.
Micron’s 9650 Pro SSD with a PCIe Gen6 interface will unlikely launch anytime soon, but for now, the unit is an important test vehicle for companies like Astera Labs, which plays an important role in developing next-gen AI platforms. At the show, Astera Labs used Micron’s PCIe 6.0 SSD to demonstrate its Scorpio PCIe 6.0 4x16 switch, Aries Bandwidth-matching Gearbox software, and Aries 6 timers.
Although Nvidia’s Blackwell GPUs feature PCIe 6.0 x16 connectivity, no CPU platforms formally support PCIe 6.0. Nonetheless, PCIe Gen6 SSDs like the Micron 9650 Pro can be quite useful when utilized with platforms featuring PCIe 6.0 switches. For example, PCIe 6.0 switches can enable peer-to-peer communications between AI GPUs and SSDs, bypassing the CPU. In addition, when paired with Astera’s Gearbox software and hardware, they can reduce the number of PCIe 6.0 lanes required to work with PCIe 5.0 hosts (e.g., to achieve a PCIe 5.0 x8 performance only for PCIe 6.0 lanes are needed) and therefore enable instalation of more drives into a box, which can be critical for some AI systems.
Certification of PCIe 6.0 devices by PCI-SIG was delayed from mid-2024 to the second half of 2025, so while GPUs like Nvidia’s Blackwell support the technology, they have not passed official interoperability tests. As for Micron’s 9650 Pro SSD, the unit used by Astera is marked as EVT3, so this is the third revision of the Engineering Validation Test. Generally, this means that the product has undergone at least two prior engineering validation builds (EVT1 and EVT2), and the third build is undergoing further validation and testing.
While EVT3 is still considered pre-production, by the third revision, most hardware issues should be resolved, and firmware/software should be approaching maturity. Just as a reminder, EVT1 is used for initial hardware bring up, EVT2 fixes all major hardware issues, and can be used for firmware development, and EVT3 features near-final hardware and therefore can be used for performance validation, thermals, compatibility and interoperability testing, and demonstrations at trade shows.
There are two iterations to go through: DVT (Design Validation Test) to validate the design under production conditions, and PVT (Production Validation Test) for full qualifications by customers. We do not know whether Micron will wait for the PCI-SIG to initiate interoperability tests in the second half of this year or will first start qualifications of its 9650 Pro PVT drive with select customers interested in PCIe 6.0 storage, but technically, EVT3 can be used for PCI-SIG’s compatibility validation.
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