Global Foundries Demonstrates 3D TSV Capabilities on 20 nm Processors

Global Foundries has demonstrated its first functional 20 nm silicon wafers with integrated Through-Silicon Vias (TSVs) and reached a key milestone in the company's plan to enable 3D stacking of chips for next generation mobile and consumer applications.

TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is considered to be a viable alternative to traditional technology node scaling at the transistor level.

"Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality," said David McCann, vice president of packaging R&D at GLOBAL FOUNDRIES. "Our next step is to leverage Fab 8's advanced TSV capabilities in conjunction with our OSAT partners to assemble and qualify 3D test vehicles for our open supply chain model, providing customers with the flexibility to choose their preferred back-end supply chain."

To overcome some of the technology's development challenges, Global Foundries has utilized a "via-middle" approach to TSV integration, inserting the TSVs into the silicon after the wafers have completed the Front End of the Line (FEOL) flow and prior to starting the Back End of the Line (BEOL) process. This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material. To overcome the challenges associated with the migration of TSV technology from 28 nm to 20 nm, the company has developed a proprietary contact protection scheme that enables the TSVs to be integrated with minimal disruption to the 20 nm LPM platform technology.

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