AMD Announces 64-Core 7nm Rome CPUs, 7nm MI60 GPUs, and Zen 4

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Paul Alcorn
Paul Alcorn
Editor-in-Chief

Paul Alcorn is the Editor-in-Chief for Tom's Hardware US. He also writes news and reviews on CPUs, storage, and enterprise hardware.

64 Comments Comment from the forums
  • flint4president
    Feel the hype!
    Reply
  • abheekg91
    Damnnn this is looking good!!
    Reply
  • Finstar
    Next Horizon*
    New Horizon happened nearly 2 years ago ffs.
    Reply
  • s1mon7
    Hoooollyy.....!!
    Reply
  • s1mon7
    "Zen 2 will provide up to 2X the compute power per node, improved execution pipeline, doubled core density, and use half the energy per operation. AMD has doubled floating point performance with the Zen 2 microarchitecture. "


    .....!
    Reply
  • jimmysmitty
    21463947 said:
    Feel the hype!

    Hype is never good.

    21464075 said:
    "Zen 2 will provide up to 2X the compute power per node, improved execution pipeline, doubled core density, and use half the energy per operation. AMD has doubled floating point performance with the Zen 2 microarchitecture. "


    .....!

    It seems too good to be true for a die shrink. I can see double the cores doubling performance but halving the energy use while increasing cores? Seems too good to be true.
    Reply
  • stdragon
    Now they have my full attention!!
    Reply
  • jaexyr
    Hopefully more efficient and lower TDP
    Reply
  • s1mon7
    21464092 said:
    It seems too good to be true for a die shrink. I can see double the cores doubling performance but halving the energy use while increasing cores? Seems too good to be true.

    "Half the energy per operation" (not per chip). The way I read it is "at the same frequency, now you can fully load twice as many cores as before at the same power ", or "double the number of instructions the core is capable of computing at the same power". The end result is probably a chip with double the cores AND increased processing performance per core to some extent at power per core lower to some extent, where you can in total compute twice as much per Watt, even if the complete chip would use more power than a last-gen chip with half as many cores.
    The 14nm->7nm die shrink can do that, with the architecture and IPC improvements filling the gaps of the wider architecture.

    Or at least that's what they just claimed, and if their claims are even remotely close to being true, that's probably the most exciting thing in the semiconductor industry since the Core architecture debuted in 2006, if not bigger.

    What I also understood to be confirmed, is that we will have 8 cores per CCX. That's prospects of 8-core mainstream chips with no interconnect. That would mean we would have separate dies for <8-core chips from the get-go, and interconnect used only on Threadripper-class chips, and that would be really darn perfect.
    Reply
  • Giroro
    21464092 said:

    It seems too good to be true for a die shrink. I can see double the cores doubling performance but halving the energy use while increasing cores? Seems too good to be true.

    It's halving the energy -per instruction-. That metric wouldn't increase with the number of cores, because an instruction will only execute on one core. So they calculate it using the maths.
    Also, the CPU probably has some amount of fixed overhead that will get divided by the number of cores in order to calculate the energy per instruction so I could see at least one way where increasing the number of cores could improve efficiency overall.

    So if there's two processors with the same power draw, but one manages to double the number of identical cores within that envelope, then the amount of power per instruction will be halved in the processor with double cores (because it is performing twice as many instructions).
    Which is still really good for a process shrink. If I remember correctly, the 28nm to 14nm shrink only improved efficiency by about 30% instead of the 50% AMD is claiming for 14nm to 7nm.

    Reply