AMD has been doing wonders in the CPU industry, with its well-received and high performing Zen 2 and Zen 3 based processors, but now it seems AMD wants to improve performance not just through faster cores, but through the use of FPGAs. Just a few days ago, AMD filed a patent for integrating FPGAs into a CPU, which would allow the processor to run custom instruction sets to extend the its capabilities. As a side note, this patent was made just a few months after AMD's acquisition of Xilinx, a company dedicated to making FPGAs.
FPGAs, or Field Programmable Gate Arrays, are simple yet powerful devices that can run specific instruction sets very quickly. This is different from a standard x86 CPU core that's designed to run a near-infinite variety of instruction sequences, albeit sometimes slowly. If there's a specific task (graphics, physics, encryption, etc.) that's used regularly, it might be beneficial to create a custom instruction on an FPGA that will process the code much more quickly. Plus, FPGAs aren't limited to a single instruction set; they can be re-programmed to run another instruction set if necessary.
This seems to be what AMD is going for, and AMD's implementation would allow the FPGA unit to share registers with the CPU itself. Simply put, this allows the CPU to very quickly offload instructions to the FPGA unit when necessary. We don't know what specific tasks AMD is looking at, but presumably anything currently using dedicated FPGAs could see support. We also don't know where this FPGA (or FPGAs) would be located. If we're talking about a Zen 2 or Zen 3 based design, the FPGA could be installed on its own separate die (chiplet) connected via the infinity fabric. Alternatively, it could be integrated directly onto the CPU chiplet, sharing a die with the cores. This would be the most optimal setup as far as performance goes, but it would require new compute chiplets.
AMD has yet to announce any new processors that take advantage of an FPGA unit. Still, this technology could be very beneficial in the future for improving processor performance as CPU architectures continue to become more difficult to shrink.