Yesterday AMD announced its upcoming AM5 platform powering its Ryzen 7000 series CPUs, along with three new chipsets featuring more I/O connectivity. The biggest surprise is AMD’s introduction of a multi-chip design for its flagship X670E and X670 chipset models. This isn't something we’ve seen before on a consumer-focused platform, but AMD’s choice to go multi-chiplet on its flagship chipsets could pay off.
According to a report by Angstronomics.com, AMD’s multi-chip approach for X670 and X670E has similar advantages to AMD’s current chiplet architecture on Ryzen CPUs. With this approach, AMD can increase I/O expansion drastically while at the same time significantly reducing manufacturing costs. This would be impossible if AMD built single monolithic dies for X670 and X670E.
Here's how AMD’s new chipset architecture works. The base chiplet for X670 and X670E is known as the Promontory 21 (PROM21) chipset, which is built by 3rd party supplier ASMedia. One of these chips comes in a 19x19mm FCBGA package featuring a maximum power rating of 7W.
That chip provides one PCIe 4.0 uplink connection to the CPU and two PCIe 4.0 x4 downlink controllers, for a maximum of eight PCIe 4.0 lane. It also supports four PCIe 3.0 x1/SATA 6Gpbs ports, six USB 3.2 Gen 2 10Gbps ports (two of which can be fused into a single 20Gbps port), and six additional USB 2.0 ports. For the SATA/PCIe 3.0 ports and USB 3.2 ports, the motherboard manufacturer can choose whether to opt for more SATA ports over PCIe ports or vice versa.
A single PROM21 chipset functions as AMD’s midrange B650 chipset. A trimmed down (harvested) version can also be used as an A600-series chipset, presumably A620. However, X670 and X670E take a different approach.
For X670 and X670E, a single PROM21 chiplet is only half of the equation, with two PROM21 chiplets linked together via daisy-chaining, effectively doubling the connectivity: double the USB ports, and double the PCIe 3.0/SATA 6Gbps ports. The exception is the downlink controller capabilities, which go from two PCIe 4.0 x4 downlink controllers on a single chiplet to three downlink controllers — one of the downlink controllers on the first chiplet connects to the uplink of the second chiplet.
While the broader connectivity options are great, one of the biggest benefits is likely to be production cost. It's more cost effective to produce a single SKU that can be scaled up or down to meet the demands of other tiers, rather than trying to build two or more entirely separate chips. Like the Zen CPU chiplets in Ryzen 3000 and later processors, each with eight CPU cores that can be disabled in clusters of two, AMD can focus on mass producing PROM21 and using it across the entire suite of motherboard offerings. There's no need to waste additional design and manufacturing resources, trying to predetermine the appropriate ratios of production.
Another positive side effect of daisy-chaining chipsets is that you can spread out cooling over a wider area. Instead of a single chipset that can draw a 15W or more, you get two 7.5W chips that are separated by perhaps several centimeters. This can save motherboard makers a lot of headaches when it comes to cooling X670 and X670E, and it should result in most X670 and X670E motherboards having passive cooling despite the PCIe 5.0 requirements, a great improvement from the actively cooled X570 chipset. However, we expect mini-ITX form factors to still have active cooling due to the physical constraints of such motherboards.
Another bonus is the reduction of signal repeaters required for PCIe 4.0 and PCIe 5.0. One of the biggest hurdles in supporting these super high bandwidth technologies is conquering the side effect of reduced signal integrity at longer distances. This forces motherboard manufacturers to build PCIe “repeaters” to boost PCIe signals so they reach their final destinations. This problem will only get worse and worse as PCIe evolves and bandwidth continues to double per generation. With a multi-chiplet design, the second chip acts like a repeater and boosts PCIe signal integrity.
Angstronomics does mention potential issues with virtualization, where there are inherently higher risks when trying to split up and assign USB ports and PCIe slots through virtualization. That shouldn't impact most users, however.
Overall, AMD’s decision to spread its multi-chip strategy from CPUs to chipsets appears to be a brilliant idea. We’ll have to see how this strategy works in practice once AMD releases Ryzen 7000 and the AM5 platform to the public, which is set to happen by the end of 2022. If it's a big success, AMD could potentially start pushing this multi-chipset strategy into other platforms, including EPYC and perhaps Threadripper motherboards.
