Filed in April 2007, the patent describes a replication of entire processors by creating point-to-point link logic between the multi-core processors. Specifically, the patent describes a design approach that delivers a much faster time to market and less complexity as this patent does not rely on modified processing protocols or significant hardware design changes.
Illustrations included in the patent reveal that Intel's multi-chip package can be created simply by using an intra-package interconnect as point-to-point link with short trace length that allows for a shorter and wider bus as well as higher clock speeds to achieve substantial bandwidth between the two processors. According to Intel, that link can be established via interconnects that are already available on the substrate.
Additionally, Intel is using a "protocol joining method" to figure out the number of necessary caching agents and home agents in the system. Additional caching agents are treated as independent caching domains and the burden of managing coherence between the two caches relies on the point-to-point cache coherency domain.
