On a recent trip to Intel's labs in Israel, Gregory M Bryant, the executive vice president & GM of Intel's Client Computing Group, took some photos and later shared them on Twitter. According to Anandtech, one of the tweets (which was later deleted) appears to show a poster on the office wall with information about the as-yet-unannounced Thunderbolt 5 protocol.
The poster says that Intel is targeted "80G PHY Technology," which implies that it is going for an 80 Gbps connection, which would be double the bandwidth of today's Thunderbolt 4 and USB 4 connections. This also falls in line with what Intel told us during The Tom's Hardware Show in March.
The poster also says "USB 80G is targeted to support the existing USB-C ecosystem," which strongly implies that Thunderbolt 5, like its predecessors, will use a USB-C connector. In March, Intel told us it was "pretty confident" this would be the case.
First released in 2011, Thunderbolt is Intel's high-speed connection standard. The standard is currently on Thunderbolt 4, though it was offering the same 40 Gbps of bandwidth and feature set in Thunderbolt 3. By doubling the bandwidth to 80 Gbps, Thunderbolt 5 could potentially offer higher refresh rates for 4K and 8K monitors, which it now supports at up to 120 and 60 Hz respectively.
To achieve the higher bandwidth on Thunderbolt 5, it looks like the protocol will use PAM-3 modulation, which is an uncommon approach. So far, in protocols like USB, PCIe, etc., we have seen non-return-to-zero (NRZ) and PAM-4 (Pulse Amplitude Modulation) implementations. The NRZ signals are binary, meaning only 0s and 1s, while the PAM-4 signals are represented in two-bit formats, which are combinations of 0s and 1s (for example 01, 11, 11, 00). For a more detailed explanation, please check out this blog (opens in new tab).
The novel PAM-3 uses -1, 0, and +1 states. This approach sits right between NRZ and PAM-4, but it allows the implementation of this signaling technique to be much simpler than PAM-4 while maintaining high bandwidth. With PAM-3, implementation is supposed to be easier and much more efficient, leading to Intel calling it a "novel PAM-3" approach.
The leaked slide also notes that "...N6 test-chip focusing on the new PHY technology is working in... showing promising results". While we can't see the full slide, it means that the Thunderbolt 5 PHY (physical layer) is already working in the fabs and it is producing desired results. As we know that N6 is TSMC's 6 nm manufacturing node, we can assume that Intel tapped TSMC's foundries to manufacture Thunderbolt 5 test chips.