To maximize the clock rate of its 32 nm Saltwell-based core, Intel employed a feature that opportunistically exposed additional P-states based on available thermal headroom. Silvermont’s implementation of this is apparently more similar to Turbo Boost in that the burst frequency is managed in hardware according to thermal, electrical, and power measurements. More important than the extra speed you get from this burst mode, though, is how it handles the ride back down.
Presently, there are mobile devices that will run at full-speed until they’re thermally overwhelmed, at which point they throttle back dramatically to recover. It’s jarring enough to affect the user experience. Intel is saying that Silvermont will handle those situations more elegantly, stepping back clock rate naturally before a thermal event is triggered.
The SoC’s power budget can be shared between the cores and other IP on the die, including third-party IP. Graphics is probably the most notable. The illustration below describes this behavior pretty clearly: cores can share power, cores can borrow budget from the graphics (which spins down), and cores can burst up dynamically, even with graphics active, if the thermal situation is favorable enough. Intel says the concepts come from Turbo Boost, but the algorithms and implementation mechanisms are different.
Coming back the other direction, Intel enables a lot of familiar core power state functionality, with the addition that cores can drop into C6 independently, whereas they couldn’t before. And because Silvermont is module-based, Intel introduced sub-states allowing software policy-based control of the L2 cache’s contents, too. Building on the S0ix connected standby system states introduced back in 2010 with the Moorsetown platform, Silvermont can now retain the state of the core through SoC standby mode transitions. This means you can resume from those modes faster, though Intel wasn’t clear on how much faster.