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The first generation of Atoms is the Z5x0, previously known by the code name Silverthorne. The Atom Z500s are dedicated to MIDs (the famous Mobile Internet Devices) and are coupled to a new chipset, the Poulsbo SCH (System Controller Hub).
With the MID orientation, it’s clear to see who Intel’s target is – ARM processors. This very popular architecture (it’s used in the great majority of telephones, PDAs, and GPS devices) is offered by many manufacturers (ARM licenses its instruction set) and offers good performance while keeping power consumption low. In the mobility arena, except for a few rare devices using MIPS architecture (the PSP, for example), ARM processors are in the majority. Intel, incidentally, once produced ARM CPUs for consumer applications (the XScale, since sold to Marvell) and still has a line of products used, for example in RAID cards (the IOP333, for example). In practice, moving from an ARM architecture to x86 poses no real problems – Linux is obviously compatible, as are Windows CE (used in many GPSs) and the Windows Mobile OS layer (at least in the older versions). In addition, the x86 can also make use of the latest Windows versions and so benefit from broader software (and technical) support than with ARM CPUs.
Before we analyze the architecture of the Atom, let’s look at the Z500 series. These processors are very small, delivered in a package only 13 x 14 mm. The processors are made up of approximately 47 million transistors (more than the original Pentium 4) and have 56 kB of Level-1 cache (24 kB for data and 32 kB for instructions) and 512 kB of Level-2 cache. They operate on a standard Intel bus, the same one used since the Pentium 4. The frequency of the bus is 400 MHz (QDR) or 533 MHz (QDR). There is also support for SIMD instructions, from MMX to SSSE3, EIST, and HyperThreading (making its comeback). Note that the latter technology is available only on certain models (with the 533 MHz QDR bus).
The SCH (System Controller Hub) is a chipset that includes the Northbridge and Southbridge in the same chip. Dedicated to Atom processors, it is the only one compatible with certain functions such as using the bus in CMOS mode (we’ll talk about that later). The SCH is complete – it includes a GMA graphics circuit (based on a PowerVR architecture), an HD Audio circuit (simplified, capable of operating only in two channels), a P-ATA controller (Ultra DMA 5, 100 MB/s), and supports two PCI-Express lanes (for a Wi-Fi card, for example). There are also three SDIO/MMC controllers and support for 8 USB ports (with the possibility of using one in client mode). The choice of P-ATA is logical: The controllers used in flash memory are often in this format (used by Compact Flash cards). Three SD controllers might seem strange, but certain types of memory use that connectivity (OneNAND, for example). Also, the DDR2 controller of the SCH supports memory with a voltage of 1.5 V (as opposed to 1.8 V for the JEDEC specifications). This little detail is a way of further reducing power consumption.
On the graphics side there’s a new GMA, the GMA 500. It uses a unified architecture and supports 3.0+ Shaders. An interesting point is that it has hardware support for decoding of the H.264, MPEG2, MPEG4, VC1, and WMV9 formats. The frequency of the GMA 500 is 200 MHz or 100 MHz, depending on the chipset version, and it’s DirectX 10 compatible (not really useful, but worth mentioning), even though the drivers only support DirectX 9. Note that the graphics end is not of Intel origin, but uses a PowerVR technology, unlike other GMA models.
The Atom Z500 has a TDP that varies between 0.85 W (for the 800 MHz version without HyperThreading) and 2.64 W (for the 1.86 GHz model with HyperThreading enabled). The SCH consumes approximately 2.3 W in its most evolved version, which brings the SCH + CPU together to under 5 W. By comparison with existing solutions, that’s obviously a big step forward – the Via Nano, for example, is announced at 25 W for the 1.8 GHz version and a Celeron-M ULV at 5 W at 900 MHz.