Ascenium Wants to Reinvent the CPU and Kill Instruction Sets Altogether

Ascenium is one of the startup companies making waves in the CPU and general purpose computing design space. The company is helmed by Peter Foley, CEO and co-founder, who previously worked on Apple's Apple I and Apple II computers as well as a long list of hardware-design focused companies. Ascenium has recently secured $16 million in funding via a Series A raise, which clearly signals a belief in the company's mission. And what is that mission, exactly?

To outdo existing CPU architectures in both performance and power efficiency via the first software-defined processor.

Ascenium hopes to do this via the perfect marrying of software and hardware achieved in its Aptos processor by killing the deep pipelines associated with the best-performing CPUs of today and creating a true, compiler-powered parallel-processing CPU based on the LLVM compiler architecture. The Aptos processor the company is currently developing is based on a 64-bit capable 128-core array of general-purpose, simple cores. If you remember Intel's efforts on the (now cancelled)  Xeon Phi architecture, Ascenium's Aptos is essentially that same many-core design paradigm, but eschewing the x86 instruction set (and its limitations and requirements on core design) while deploying a high-performance compiler that parallelizes workloads across its hardware resources. 

Ascenium has already secured nine patents related to its architecture and software designs, which will offer the company a much-needed defence against entrenched computing giants who won't/can't abandon their current instruction sets, such as x86 and Arm, and would likely go after an emerging player that had a product good enough to threaten the established, 50-year-in-the-making ISAs we currently know.

A deep pipeline (which is essentially the route instructions take inside the CPU architecture until a solution for the current problem is produced) allows for increased performance in workload serialization but negates many scenarios where parallelization (and thus higher performance) could be achieved. And with deep pipelines and the specialized hardware registers and stages which make up a modern CPU's processing, Ascenium estimates that around 50% of instructions are related to the movement of data through the pipeline — instructions and moves which take up both processing time and power budget. The idea of a compiler-based software solution embedded in an architecture would theoretically allow the Aptos processor to interpret workload instructions and distribute them across processing resources in such a way that the amount of work being parallelized is as close as possible to the theoretical maximum, whilst taking advantage of having much lesser architectural inefficiencies than instruction-based processors. Ascenium plans to push for higher power/performance ratios, and even savings of 10% in that equation are gold to hyperscalers and the type of data centre client that Ascenium hopes to lure into its ecosystem first. They are the ones to benefit the most from such an architecture.

Naturally, if one could create an architecture that reduces the need to shuffle data around, it'd find itself with a relevant power efficiency advantage. And then there's also the matter of x86's structural weaknesses, requiring an inordinate amount of transistors to be thrown at a given problem to achieve even small amounts of performance improvements. Ascenium CEO Peter Foley places it in the order of billions of additional transistors to achieve performance increases that sometimes don't even enter the two-digit realm.

So Ascenium plans to do away with instruction sets, create the world's first homogeneous, instruction set and architecture-free processor, and usher in a new processing architecture built from the ground-up. These are lofty aims and the risk is immense. But then again, so is the reward.