RISC-V (pronounced risc-five) is a brand-new instruction set architecture (ISA) that’s open to customize and free to use by anyone. The ISA is only a few years old, but both large and small companies, such as Nvidia, Western Digital, and Esperanto, are now planning to use RISC-V chips to power their products.
Why RISC-V Was Created
The initial version of the RISC-V ISA started development at the University of California, Berkeley, in 2010. The academics there wanted to develop a more modern and more efficient ISA for the 21st century that removes the legacy cruft and many mistakes built into multi-decade old instruction sets such as x86 and ARM. The researchers also wanted an ISA that is fully open and free for anyone to use for any purpose without having to pay any royalties to anyone.
In 2014, version 2.0 of the ISA was released, and that’s when many of the big players in the technology industry started becoming interested in it. If 1.0 was more of a research curiosity, 2.0 showed that the ISA could actually be used in production by large players who wanted to save money on royalties or simply wanted a much larger degree of freedom when designing their own CPUs.
In 2015, the RISC-V Foundation was created with more than 100 members and a board of directors that included companies such as Google, Nvidia, Western Digital, NXP, Microsemi, and Bluespec, as well as a representative from UC Berkeley. Since then, chip companies such as AMD, Qualcomm, and IBM have also joined the members list.
The foundation released version 2.2 of the RISC-V ISA specification earlier this year. Mozilla also recently announced that the memory safe Rust programming language, which the organization is now using to rewrite core components of the Firefox browser, supports the RISC-V ISA as a compilation target.
Western Digital Commits To Shipping “Billions” Of RiSC-V Cores
At the a recent RISC-V Workshop event, Western Digital, one of the largest manufacturers of storage devices, announced that it’s going to lead the industry in the switch to the more open RISC-V ISA by committing to ship over one billion RISC-V cores per year in its devices.
WD said that the purpose for implementing more powerful RISC-V cores into its products is that this will bring computation closer to data. The movement of the data will be minimized, which should bring increased performance and efficiency to its customers.
WD hopes that after switching all of its product lineups to using RISC-V microcontrollers, it will be able to ship over two billion RISC-V cores across its product categories.
Esperanto Promises “AI At The Edge” With RISC-V Cores
Esperanto Technologies a chip designer from Mountain View, California, also announced at the latest workshop that it will start developing energy-efficient AI chips using the RISC-V ISA.
"Esperanto's goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications which will drive computing innovation for the next decade," said Esperanto CEO Dave Ditzel.“RISC-V is so simple and extensible that we can deliver world class TeraFlop levels of computing without needing to resort to proprietary instruction sets, thereby greatly increasing software availability,” he noted.
He also added that the company will build a 16-core "ET-Maxion" 64-bit chip, which will have single-thread performance, as well as a 4,096-core "ET-Minion" energy-efficient chip, with each core having its own floating point unit.
Dave Ditzel has a long history of supporting RISC instruction sets. He was founder of Transmeta, a company that tried to build RISC chips that could emulate x86 programs on them, and he worked on the SPARC architecture at Sun Microsystems. Ditzel also worked at Intel for six years, working on various high-performance chip projects.
Western Digital CTO Martin Fink also announced at the RISC-V workshop that they’ve made a strategic investment in Esperanto in order to help build the RISC-V ecosystem.
Nvidia Quietly Adopting RISC-V, Too
Last year, Nvidia quietly revealed that it’s going to build its next-generation GPU microcontroller on the RISC-V ISA. The new RISC-V microcontroller is expected to improve performance by more than three times compared to its existing Falcon microcontroller. The RISC-V microcontroller will also include some significant security features that the current microcontroller is lacking, which could be of use in the autonomous driving industry, for instance.
We’re not going to see RISC-V take the market by storm and compete with Intel and ARM in high-end smartphones, PCs, and servers for at least a few more years. However, RISC-V’s modern ISA, which brings high efficiency, better security, as well as the openness of the architecture combined with the royalty-free license, may prove irresistible to many companies.
I wonder how the RISC-V ISA compares to ARM's ISA.
I wouldn't mind paying for the implementation of this ISA as a CPU or micro controller, but it's nice to know that you can develop for something like this without proprietary restrictions.
I like to think about a utopian future 50 years from now where free and efficient technologies like this reign supreme. What I want to hear is, "Today is better than yesterday". What we seem to get, unfortunately, is, "We're worse off than yesterday."
Gosh. That's really cool. Like I said earlier, I've only hard o this ISA today so I'm not well informed about it. Do you remember where that statistic came from?
An ISA that's supposed to compete with x86 and ARM could belong to a CPU. I don't think x86 is used in simple micro contollers.
It's apparently being backed by Nvidia, IBM, and AMD. Each of these companies has it's own instruction set it develops already and I don't seem them building new flagship CPUs around RISC-V any time soon. In this case, RISC-V seems like it's more suited to integrated into a small, simple device.
At any rate, I plan to keep an eye on it in the future.
edit: changed wording for clarity
Nvidia has so far used RISC-V to replace the proprietary microcontroller integrated into their GPUs. I'm not aware of any plans for it to replace ARM in their Tegra SoC, but I think they'd probably prefer not to pay royalties to ARM if they could avoid it.
ARMv8-A also requires things like NEON 128-bit SIMD support. That actually highlights one potential down-side of a completely open ISA, which is that you could start to have implementations appearing with different, incompatible extensions. ARM is very strict about which instructions all implementations must support. I'm sure the RISC-V foundation is aware of this hazard, and it'll be interesting to see how they manage it.
RISC-V gets a clean sheet design, allowing its instruction decoder to be simpler. Over time, the cruft will probably build up, but certain embedded applications might not need to provide binary compatibility with earlier generations.
Now, ARM has a different family of ISAs that's targeted specifically at microcontrollers. I don't know as much about it, but if we're talking about that market, then it should be the basis for comparison:
"The renewed need in the post-PC
era for simpler ISAs led to the RISC-V.
(This is pronounced “RISC five” since
it the fifth RISC architecture from UC
Berkeley.) Keeping with its heritage,
the RISC-V is a minimalist ISA; in fact,
the base ISA is remarkably similar to
its great-great-grandparent RISC-I.
One indication of complexity is the
size of the documentation. The ISA
manual for x86-32 is 2,198 pages or
2,186,259 words. The RISC-V equivalents
are 236 pages or 76,702 words.
If someone were to read manuals as
an (incredibly boring) full-time job—
eight hours a day for five days a week—
it would take a month to read the x86-
32 manual but less than a day to read
the RISC-V manual.
Because it’s new, the RISC-V avoids
the mistakes of past ISAs.
For example, it’s modular: a small base ISA runs a full
software stack (OS, libraries, debuggers,
and compilers). The base is frozen and
will never change, giving programmers
a stable target. The modularity comes
from optional standard extensions:
multiply and divide, floating-point
arithmetic, atomic operations, compact
code, and vector instructions.
To achieve the software-desirable
goal of a single ISA that works from
the smallest to the largest computers,
it needs to lead to efficient designs for
both edge devices and the cloud. To
empower large-scale computers, the
RISC-V offers 64-bit as well as 32-bit
address versions. Minimalism and
modularity enable small and lowenergy
implementations of the RISC-V,
which helps embedded applications.
While some argue that ISA complexity
doesn’t matter for high-end processors,
it does matter for low-cost
applications, which the lack of success
of the 80x86 illustrates. A universal
ISA must work well everywhere. To
support domain-specific architectures
(DSAs), such as Google’s tensor
processing unit (TPU), the RISC-V
reserves opcode space to allow tight
coupling of custom accelerators.
However, the RISC-V’s most unconventional
feature is that it’s open. Its
future is free from the fate or decisions
of a single corporation, which have
doomed numerous ISAs in the past.8
Instead, it belongs to a nonprofit foundation
with more than 75 corporate
members (riscv.org). Its goal is to maintain
the stability of the RISC-V; evolve
the ISA slowly and carefully, keeping
technological changes in mind; and to
try to make it as popular as software
open source projects like Linux. This
openness enables any organization to
develop and share implementations of
the RISC-V. Competition, a free market,
and open implementations might
lower costs and increase innovation,
similar to the benefits of open source
software. Open designs also reduce
the odds of unwanted malicious secrets
being hidden in a processor."