Here at Hot Chips 31 Intel is unveiling more details about Lakefield processors using its new Foveros (Greek for "awesome") tech, a new 3D packaging technology that Intel uses to build new processors stacked atop one another. This is live coverage, so refresh your browser or return to the article for as-it-happens updates.
The concept behind 3D chip stacking is a well-traveled topic that has been under development for decades, but the industry hasn't been able to circumvent the power and thermal challenges, not to mention poor yields.
Chip stacking allows mixing and matching different types of dies, such as CPUs, GPUs, and AI processors, to build custom SOCs. It also allows Intel to combine several different components with different processes onto the same package. That lets the company use larger nodes for the harder-to-shrink or purpose-built components. That's a key advantage as shrinking chips becomes more difficult.
Intel says it built Foveros upon the lessons it learned with its innovative EMIB (Embedded Multi-Die Interconnect Bridge) technology, which is a complicated name for a technique that provides high-speed communication between several chips. That technique allowed the company to connect multiple dies together with a high-speed pathway that provides nearly the same performance as a single large processor. Now Intel has expanded on the concept to allow for stacking die atop each other, thus improving density.
Lakefield processors are the first to come to market with Intel's new 3D chip-stacking technology. The current design consists of two dies. The lower die houses all of the typical southbridge features, like I/O connections, and is fabbed on the 22FFL process. The upper die is a 10nm CPU that features one large compute core and four smaller Atom-based 'efficiency' cores, similar to an ARM big.LITTLE processor. Intel calls this a "hybrid x86 architecture," and it could denote a fundamental shift in the company's strategy. Finally, the company stacks DRAM atop the 3D processor in a PoP (package-on-Package) implementation.
Lakefield enables new converged mobility form factors that are smaller than traditional PCs. Think super-thin, fanless, and low standby power in the 2 or 3 milliwatt range. Standby power had to go down 1/10th, and graphics power had to go up 50%. The motherboard area had to go down 40%, and thickness needed to be reduced by 40%. That required a profound change in the approach.
The speaker displayed a real Lakefield chip with three die: memory, CPU, and I/O dies. He also presented a full compute platform on a single-sided PCB that is incredibly small. That's the entire computer on a slim stick.
Here we can see the key enablers to creating the smallest motherboard Intel has ever made.
The board area of Lakefield is smaller than half the size of previous-gen boards, largely because of the smaller chip package. Instead of using FIVR for power delivery, Intel used PMIC. Actually two, one for the bottom die, and one for the top.
Here we see both die and their components. The top die has the CPU with one large core and four small Atom cores. This is called the compute die.
The bottom die is the base die. This has several I/O blocks.
Different types of transistors offer different advantages for certain use cases. You can't build a single transistor to meet all these needs, so it's best to use two packages.
The low-leakage P1222 process was used for the base die, and 10nm for the compute die. Stacking the two die together behaves like a monolithic die. Intel will use 7nm for the compute die and 1274.FV for the base die in future models.
Everything that is not needed for compute goes on the bottom, then there is a die to die interlink, a thermal shield, and then a compute die. Finally, the DRAM is mounted to the top of the package.
Hybrid architectures combine a big core for compute-heavy cores, while smaller cores handle light tasks. Sunny Cove is used for the big core, while Atom Tremont is used for the small cores.
Blue is Tremont power consumption, and yellow is Sunny Cove power consumption. Both are plotted over single-threaded performance. This provides a broader range of both performance and efficiency. That gives a 50% gain in performance at higher TDP ranges, while Tremont is better in the lower ranges.
The second chart (left) plots the same metrics in multi-threaded workloads.
Here we can see how Intel moves the heavy and light workloads between the two types of cores. This requires some interaction from the software and operating system. Naturally, performance workloads go to the Sunny Cove cores, while background and light workloads go to Tremont.
Reducing standby power was a big goal of the design. Here we can see that Lakefield uses 1/10th the power of 6th-gen Core chips when in standby.
The chips use Gen11 graphics with 64 Eus. Here we can see big performance gains.
Lakefield is the first chips to deliver on all these design goals. The chips are targeted for the end of Q4 for production samples.
Intel is using 10nm+, the same process as Ice Lake. In terms of interconnects, Intel uses a 50 micron pitch for connections and a 20 micron pitch for microbumbs. Relaxed pitch improves yields on the first device.
