Die shots of Intel’s Arrow Lake architecture have been published, revealing Intel’s chiplet (tile) infused design in all of its glory. Andreas Schiling on X shared several images of Arrow Lake up close, revealing the layout of Arrow Lake’s individual tiles and the layout of the cores inside the compute tile.
The first photo exposes the full die of Intel’s desktop Core Ultra 200S series CPUs, with the compute tile on the upper left, the IO tile on the bottom, and the SoC tile and GPU tile on the right. To the bottom left and top right are two filler dies designed to provide structural rigidity.
A few highlights from the deep analysis of #ArrowLake by @highyieldYT pic.twitter.com/WFUG0xVaFEMay 5, 2025
The compute die is fabbed on TSMC’s bleeding-edge N3B node, with a total area of 117.241 mm². The IO tile and SoC tile are fabbed on TSMC’s older N6 node, with the IO tile measuring 24.475mm squared and the SoC tile 86.648mm squared. All of the tiles rest on an underlying base tile fabbed on Intel’s 22nm FinFET node. Arrow Lake is the first Intel architecture that is fabricated entirely using nodes from a competitor, except for the base tile.
The next image shows all of the sub-components for the secondary tiles in Arrow Lake. The I/O die houses the Thunderbolt 4 controller/display PHY, PCIe Express buffers/PHYs, and TBT4 PHYs. The SoC tile houses the display engines, media engine, more PCIe PHYs, buffers, and the DDR5 memory controllers. The GPU tile houses four Xe GPU cores and an Xe LPG (Arc Alchemist) render slice.
The final image shows off Intel’s latest core configuration for Arrow Lake, which differs from previous hybrid Intel architectures. For Arrow Lake, Intel opted to sandwich the E-cores between the P-cores rather than putting them all in their own cluster, allegedly to reduce thermal hotspots. Four of the eight P-cores reside on the borders of the die with the other four residing in the middle of the die. The four E-core clusters (which house four cores each) are sandwiched between the outer and inner P-cores.
Schilling’s die shot also exposes the cache layout for Arrow Lake, comprised of 3MB of L3 cache per P-core (36MB in total) and 3MB of L2 cache per E-core cluster, with 1.5MB shared between two cores directly. An interconnect bridges the two L2 cache clusters (and their associated cores) together, which is also responsible for connecting each core cluster to the ring agent. One major upgrade Intel made with Arrow Lake is connecting the E-core clusters to L3 cache shared by the P-cores, effectively giving the E-cores an L3 cache.
Arrow Lake is one of Intel’s most complex architectures to date and the first from the company to bring a chiplet-style design to the desktop market. That said, Intel’s first attempt at a desktop chiplet-based competitor has not been well received, due to latency issues from the interconnect, which is responsible for connecting all the tiles together. Intel is attempting to rectify the issue through firmware updates. Still, its current implementation can’t touch AMD’s competing Ryzen 9000 CPUs (such as the 9800X3D), nor is it enough to even beat its own previous-generation 14th-generation processors in gaming (such as the 14900K).
All that said, moving to a chiplet approach will afford Intel more ways to optimize its architectures down the road, in a more efficient manner. Each tile can be developed independently of others and built with different nodes to improve yields, optimize development, and reduce production costs.
