Sparc64 processor aims at dual-core transition in 2006

San Jose (CA) - Fujitsu, one of the development forces behind the Sparc processor, used the currently held Microprocessor Forum to provide some details of the next-generation of Sparc processors. To keep up with Intel's Xeon and Itanium roadmap, the Sparc64 chip will continue its evolutionary route and bring speed increases, multithreading and enhancements in power efficiency with two new product generations that are due in late 2006 and early 2008.

The Olympus processor, which will be named Sparc64 VI, will be built in a 90 nm manufacturing process and transition to dual-core technology. According to Takumi Maruyama from Fujitsu, the new processor will upgrade the clock speed from currently maximum of 2.08 GHz in the Sparc64 V to 2.4 GHz and integrate two cores. With 6 MByte of L2 cache, Olympus checks in with 540 million transistors - significantly less than the 1.7 billion transistors of Intel's dual-core Itanium 2 - and a die size of approximately 410 mm2.

Fujitsu expects the 2.4 GHz Sparc64 VI to deliver roughly twice the speed of a single-core Sparc64 V 1.35 GHz processor. Fujitsu did not provide power consumption data for the Sparc64 V, but said that the new dual-core chip will consume about 120 watts, which is in line with Intel's current single-core Itanium 2 chip.

For 2008, Maruyama outlined a few details about the Sparc64 VI successor "Sparc64 VI+". The chip will be manufactured in 65 nm technology and run 4 cores at least 2.7 GHz. The die size of the processor will increase to about 464 mm2.