AMD teases its first 2nm chip, EPYC 'Venice' fabbed on TSMC N2 node — also announces USA production of current-gen chips

AMD
(Image credit: AMD)

In a rather unexpected turn of events, AMD announced late on Monday that it had obtained its first 2nm-class silicon, a core complex die (CCD) for its 6th Generation EPYC 'Venice' processor, which is expected to launch next year. The Venice CCD is the industry's first HPC CPU design to be taped out on TSMC's N2 process technology, highlighting AMD's aggressive roadmap and the readiness of TSMC's production node. 

AMD's 6th Generation EPYC 'Venice' is expected to be based on the company's Zen 6 microarchitecture and is expected to be launched sometime in 2026. The CPU will rely on CCDs to be made on TSMC's N2 (2nm-class) fabrication process, so it is about time for the company to get the first Venice CCDs out of the fab. Yet, the fact that AMD already has chips it can talk about highlights the long-standing collaboration between AMD and TSMC as well as the culmination of joint efforts to build chips on one the most advanced process technologies that TSMC has ever developed to date. 

Anton Shilov
Contributing Writer

Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

  • jackt
    And they are stilll selling 4nm...
    Reply
  • Pemalite
    Be interesting to see what kind of impacts Tariffs does to AMD's next-gen chips in regards to pricing.
    They have been fairly consistent gen-on-gen thus far.
    Reply
  • thestryker
    I wonder if the Epyc CPUs on N2 will be all of them or just the high density ones like the current N4/N3 split. This is also our first official confirmation that Apple didn't buy out the first run of N2.
    Reply
  • hannibal
    jackt said:
    And they are stilll selling 4nm...
    Consumer and pro stuff are different thing totally.
    Reply
  • Neilbob
    The whole 2nm thing aside, I find it interesting that they're pulling out the 'Venice' code name again after 20 or so years.

    It was used for the 90nm Athlon 64 that, at the time, turned out to be vastly superior to the truly awful Intel Prescott Pentium 4 space-heaters.
    Reply
  • bit_user
    jackt said:
    And they are stilll selling 4nm...
    TSMC's 2 nm doesn't hit volume production until the end of this year.
    https://www.tomshardware.com/tech-industry/tsmcs-1-6nm-node-to-be-production-ready-in-late-2026-roadmap-remains-on-track
    Yeah, it's a little disappointing Zen 5 used a N4 node, but there are a few benefits:
    TMSC has N4 production currently in its Arizona fabs and AMD is a customer. This is good for US sales of these chips and resilient supply if Taiwan gets cut off.
    N4 is cheaper, giving AMD more flexibility with pricing.
    Considering how competitive Zen 5 has been on N4, that bodes quite well for further reductions.
    Honestly, the biggest complaint I have about Zen 5 isn't the CCDs, but rather the N6 IO die that they reused from Zen 4. Because of that, it has higher idle power and worse memory performance. I sort of wish they'd do a refresh with a newer IO die and then I might even be tempted to take the plunge.
    Reply
  • bit_user
    Neilbob said:
    The whole 2nm thing aside, I find it interesting that they're pulling out the 'Venice' code name again after 20 or so years.
    All of the AMD Epyc CPUs have been named after cities in Italy.
    Zen 1 = Naples
    Zen 2 = Rome
    Zen 3 = Milan
    Zen 4 = Genoa; Zen 4C = Siena
    Zen 5 = Turin
    Neilbob said:
    It was used for the 90nm Athlon 64 that, at the time, turned out to be vastly superior to the truly awful Intel Prescott Pentium 4 space-heaters.
    You can see here that their naming convention was much looser, just picking an assortment of big cities from all over the place:
    https://en.wikipedia.org/wiki/List_of_AMD_processors#K8_core_architecture_(2003%E2%80%932014)
    I think it's okay for them to reuse Venice, by now. Nobody is going to be confused by this.
    Reply
  • ottonis
    With an expected launch date "somwhere in 2026" , these N2-based chips from AMD will probably hit the market around the same time as Intel's 18A chips (first half of 2026), or maybe even a few months later than Intel. So, that's nothing I would call "aggressive strategy", as both AMD and Intel are moving along toe to toe, as it seems.
    Reply
  • TerryLaze
    ottonis said:
    So, that's nothing I would call "aggressive strategy", as both AMD and Intel are moving along toe to toe, as it seems.
    How isn't being toe to toe aggressive?!
    I mean sure, it's just normal pace and that's what amd would do even without intel being there but as far as sensationalism this is like very low.
    Reply
  • ottonis
    TerryLaze said:
    How isn't being toe to toe aggressive?!
    I mean sure, it's just normal pace and that's what amd would do even without intel being there but as far as sensationalism this is like very low.
    Well, depends on what one associates with the term "aggressive". For me, aggressive means that a company is really pushing forward and taking the lead. So, if AMD were to bring their N2-based chips to market subsantially earlier than Intel their own 18A chips - now that would indeed be "agressive" in the best sense of this word.
    Reply