AMD 16-core Zen 5c die shots show long, narrow CCX, all 16 cores sharing a single L3 cache

Die shots of AMD's 16-core Zen 5c CCD used in its latest EPYC 9005 series server processors have been exposed, revealing clear differences compared to AMD's previous-generation Zen 4c CCDs. Posted by HXL on X, photos of AMD's 16-core 3nm Zen 5c CCD expose a long row of two banks of cores flanking a 32MB layer of L3 cache in the middle of the die.

AMD's Zen 5c dies are substantially longer than its vanilla Zen 5 CCD, measuring 5.7 mm by 14.83 mm. Zen 5, by contrast, measures 7.4mm by 11.26mm. The extra length was added to accommodate the additional cores each Zen 5c CCD contains, while simultaneously enabling all cores to share a single unified L3 cache, making Zen 5c AMD's first compact core architecture to sport a single-CCX design.

Latest Videos FromTom's Hardware

Watch full video here:

Single-CCX designs are a philosophy that is now commonplace on AMD's regular Zen cores, but was not implemented on Zen 4c. Moving from a dual-CCX design to a single-CCX design improves core-to-core communication latency and L3 cache latency. Dual-CCX dies require cores on one CCX to use the Infinity Fabric to communicate with cores and L3 cache on the other CCX, despite both CCXs being housed on the same die. On a single CCX die, all cores can communicate with each other directly through one unified L3 cache.

Zen 5c, AMD's second generation of compact cores, features the same IPC performance and feature set as vanilla Zen 5 but in a 25% smaller package. They are AMD's equivalent to Intel's E-cores, but take advantage of the same architecture as their larger sibling. Intel, by contrast, uses two completely different architectures for its P-cores and E-cores.

Follow Tom's Hardware on Google News to get our up-to-date news, analysis, and reviews in your feeds. Make sure to click the Follow button.

TOPICS

Aaron Klotz is a contributing writer for Tom’s Hardware, covering news related to computer hardware such as CPUs, and graphics cards.

8 Comments Comment from the forums

Elusive Ruse

I would definitely consider upgrading next generation if that’s the case.
Reply
drajitsh

I thought zen "c" cores had reduced cache and execution resources.
Can someone clarify the exact differences between zen 5 and zen 5c cores @tomshardware
Reply
drajitsh

drajitsh said:
I thought zen "c" cores had reduced cache and execution resources.
Can someone clarify the exact differences between zen 5 and zen 5c cores @tomshardware
I thought zen 5c cores had only a 1 MB/core L3 cache
Reply
Gillerer

"C" stands for cloud-optimized; improved efficiency for die area and power, as well as increased core counts.

Cache takes up lots of space, so "C" CCDs have less of it per core.

While the architecture is exactly the same as regular Zen 5, the cores are build denser, so can't clock as high. But lower clocks mean better efficiency. (They're also guaranteed to run at that set speed 24/7, so cloud providers can be secure in selling that performance level to their customers.)

Having more cores, but at reduced performance per core may also alleviate any bottlenecks from the Infinity Fabric link to the CCD, and 12-channel DDR5. You probably couldn't realize much improvement from having 16 Zen 5 (non-C) cores on a CCD, since they'd end up being bandwidth starved.

The C-core CCDs end up being smaller enough that you can cram 1.33 to 1.5 times as many C cores per socket. Then a cloud provider gets cost savings from being able to serve more customers per rack; each running a virtual server utilizing just 1 or a few cores.
Reply
AI Jedi

I don't see how calling the C cores the equivalent of Intel's E-cores's is applicable. Also note that the E-Cores in Intel's new Arrow Lake CPU's and Lunar Lake mobile CPU's are much better than those in Intel's 13th and 14th Gen chips.

https://chipsandcheese.com/p/skymont-intels-e-cores-reach-for-the-skyhttps://chipsandcheese.com/p/lion-cove-intels-p-core-roars
Zen5c cores have much better floating point performance then the new e-cores
Reply
Rob1C

They'll need to make the processor skinnier, as there's barely enough room for 24 DIMMs in a dual socket 19" rack; unless they plan on returning to 23".

Reply
usertests

Elusive Ruse said:
I would definitely consider upgrading next generation if that’s the case.
'C' chiplets have been used only in Epyc so far. We now know that Zen 6 will use 12-core chiplets for up to 24 (main) cores.

drajitsh said:
I thought zen 5c cores had only a 1 MB/core L3 cache
While the 8 Zen 5c cores in Strix Point only had 8 MiB, there is no rule saying that they can't use more cache.

'C' cores are smaller than regular cores even if you take L3 cache out of the equation. They use different cell libraries and other tricks to shrink the core.

The Zen 4c chiplet also has 16 cores and 32 MiB of L3 cache, same as this chiplet. The difference was that it was divided into two core complexes with 8 cores and 16 MiB each. Though that is still 2 MiB/core.
Reply
reflex25

The cache needs to be shared to ensure coherence.
Reply

Show more comments