Xilinx today announced the Virtex UltraScale+ VU19P. This 16nm device with 35 billion transistors, consisting of four chips on an interposer, is the world’s largest field-programmable gate array (FPGA) and contains 9 million logic cells.
Aside from the 9 million logic cells, the Virtex VU19P also features 1.5Tb/s of DDR4 memory bandwidth, up to 4.5Tb/s of transceiver bandwidth and over 2,000 user I/Os. Xilinx says the FPGA is 1.6x larger than the 20nm Virtex UltraScale 440, its predecessor and up to now previously the industry’s largest FPGA. That one has 5.5 million logic cells.
Xilinx is targeting ASIC or SoC creators that use FPGAs for emulation, prototyping and validation. That enables developers to begin software integration before the silicon is available. Other applications include test, measurement, compute, networking, aerospace and defense. Xilinx also provides accompanying tool flows and IP to support it.
With 35 billion transistors, it definitely one of the biggest (16nm) chips around. From third-party images, it is clear that the die consist of four rectangular slices (which together span the length of the chip), on top of an interposer. This is similar to the Virtex-7 2000T that the company announced in 2011, of which the VU19P is the third of this kind of ultra big chiplet FPGAs. A very rough estimate yields that the VU19P has a die size of ~900mm2, making it larger than the reticle size limit for monolithic dies.
While no recent disclosures are available, an old comment from Altera (now part of Intel) had Stratix 10 also at 35 billion transistors, but that includes the transceivers which are connected via EMIB to the base die. Intel just announced another big chip on 16nm, the Nervana Spring Crest NNP-T with 28 billion transistors. Although at 688mm2, it is not as big (in die size) as the 21 billion transistor Nvidia V100 that is over 800mm2.
It will be a while until the VU19P is available, as its general launch is planned for the fall of 2020. Xilinx also recently launched a new, small form factor Alveo U50 card for data center acceleration based on its UltraScale+ architecture and started shipping its 7nm Versal ACAP to early customers.