Phison PS5008-E8 Technical Preview
NVMe SSDs are on track to outsell SATA models by the end of 2017. It's difficult to imagine that happening in the current aftermarket climate where the products with the fastest protocol demand a price premium, but there's plenty of value in the NVMe market. The Intel 600p and MyDigitalSSD BPX already set the tone with the speedy NVMe interface at close-to-SATA pricing. These products currently contend with high-performance SATA SSDs, like the Samsung 850 Pro. In October we will begin to see NVMe SSDs matching mainstream SATA SSD pricing, and many of those value-optimized SSDs will ship with the upcoming Phison PS5008-E8 controller. That's what we have in for testing today.
Phison isn't the only company targeting the entry-level and mainstream NVMe markets. We've seen controller designs from Toshiba, SMI, and Marvell. Other companies have controllers tucked away from the public eye, as well. Maxiotek, Realtek, VIA, and others, play show and tell behind closed doors. NVMe is clearly poised to gain market share through volume, so all the controller vendors want to have a product ready.
Phison has two solutions in the final stages of development. The PS5008-E8T is a DRAMless design that uses Host Memory Buffer (HMB) technology to cache the physical-to-logical address map in your system's memory. This E8T will be a very low-cost option for system builders and people shopping for an affordable NVMe performance upgrade.
The PS5008-E8 is the mainstream model in the E8 series. This controller increases performance by using local DRAM on the SSD. With the DRAM memory closer to the controller, the latency hop is lower than reaching out over the PCI Express bus to the system memory. We've yet to test an HMB device to measure latency, but the common claim is a 2x increase in retrieving and updating the address map.
Phison plans to release the mainstream E8 NVMe controller before the E8T, but both will ship in retail products before the end of the year. If the current schedule holds true, Phison's partners should have products on store shelves by the end of October.
We're focusing on the E8 mainstream controller, but we want to compare it with the DRAMless E8T. These two parts are very close to each other in specifications and features--they even share similar silicon. The DRAMless E8T will only scale to 1TB using Toshiba's new BiCS 3 TLC flash, but the E8 will scale to 2TB with the same NAND. It's important to remember that larger drives require a larger address map, so adding extra room for the map allows Host Memory Buffer technology to double the capacity of these entry-level products.
Phison is the only company using the PCI Express 3.0 x2 strategy. This is a very bold move, but one that the company hopes will pay off in overall value for the SSD manufacturers and lower power consumption for end users. The x2 design reduces R&D complexity and is cheaper to manufacture. Normal SSDs use a x4 connection, but in this case, two of the lanes are disabled. That allows notebooks to turn off two PCI Express lanes and the hardware associated with them, like PCIe switches. That reduces the system's overall power consumption.
Both the E8 and E8T should deliver around the same sequential read performance. The 1,600 MB/s of sequential read throughput is very close to the maximum performance you can achieve over the PCIe 3.0 x2 bus after accounting for encoding overhead. Sequential write performance benefits from the onboard DRAM buffer. The E8 delivers up to 1,100 MB/s of sequential write speed, but the E8T will only deliver up to 880 MB/s.
Random performance is all about latency, and that's where the local DRAM provides an advantage. The E8 delivers up to 280,000/225,000 random read/write IOPS. The DRAMlesss E8T delivers up to 125,000/115,000 read/write IOPS. The E8T is significantly slower than the E8, but it is still much faster than the best SATA SSD on the market.
Phison provided a breakdown of a few key differentiating features:
End to End Data Path Protection - There is a risk of losing data through every data transition process. The PS5008-E8 implements this enterprise feature to protect the entire data path within the SSD by utilizing CRC/ECC.
- Designed to fight against internal soft errors between SRAMs
- Error detection/correction between controller and DRAM
- Error detection/correction between controller and NAND flash
StrongECC - StrongECC is Phison's proprietary error correction code algorithm. Compared to conventional ECC algorithms such as BCH and LDPC, StrongECC delivers sustained performance and low power consumption while performing data correction activities.
SmartECC - Errors are unavoidable because of the physical characteristics of NAND. Data recovery methodology plays an important role in the storage industry. SmartECC is Phison's proprietary RAID ECC algorithm that can recover user data from uncorrectable errors. Whenever the PS5008 detects any uncorrectable errors in a page, the data stored within this defective page can still be reconstructed by the SmartECC engine.
Pyrite - The PS5008 uses TCG's Pyrite to enhance the security level of data access. Pyrite supports logical locking of the storage device interface and enables interoperability between multiple storage device vendors.
A Closer Look
Phison's new M.2 2280 design allows for up to six NAND emplacements on a single side of the PCB. Our 512GB sample features four NAND flash packages, the E8 controller, and a Nanya DRAM package.
This drive uses Toshiba's new 256Gbit TLC from the BiCS (Bit-Cost Scalable) NAND product line, which is the fancy trademark name for the company's 3D flash. We've also seen the E8 in an add-in card form factor.
- Compatible with PCI Express Revision 3.1
- Compatible with NVMe 1.2
- Compatible with PCIe I/II/III Interface
- Configurable with 2Gb/4Gb/8Gb DDR3/DDR3L Cache (E8)
- DRAMless HMB (E8T)
- Upgradable Firmware
- 40nm CMOS Processing Node
- Dual Core
- 324-Pin TFBGA (E8)
- 252-Pin TFBGA (E8T)
- Operating Voltage: 1.1V (Controller Core), 3.3V Controller I/O
- Built-In Regulator Supporting 1.2V/1.8V Flash I/O
- Supports 1z nm MLC/TLC and 3D Flash
- Supports Interleaving Operation: Up to 128-Plane and 4-Channel Flash Access
- Supports MLC/TLC Large Block (8KB/16KB Page Sizes)
- Built-in Static And Dynamic Wear-Leveling
- Power Savings Implemented
- End-To-End Data Path Protection
- Host Memory Buffer (E8T)
- Single Root I/O Virtualization
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Oooooh. Tell me more.
Does this mean that both the E8 and E8T use HMB but the E8 uses it to double the capacity of the E8T? Because otherwise this is confusing as the E8T (using HMB) has half the max capacity of the E8, not double.
"The E8 delivers up to 1,100 MB/s of sequential write speed, but the E8T will only deliver up to 880 MB/s. The E8 delivers up to 280,000/225,000 random read/write IOPS. The DRAMlesss E8T delivers up to 125,000/115,000 read/write IOPS. The E8 is significantly slower than the E8T"
This part has to be a mix up. The E8T is slower than the E8, not the other way around.
As for the speed, yes that was flipped around and we will get it fixed asap.