AMD Files Patent for big.LITTLE-esque Hybrid Computing Technique

Big performance, low power

(Image credit: AMD)

As spotted by patent sleuth @Underfox3, AMD has field a patent for a technique that speeds the transfer of threads between high-performance cores and smaller low-performance cores in a big.LITTLE-esque hybrid computing architecture. As with all patent filings, this doesn't assure that AMD will bring a hybrid computing device to market, but it certainly shows the company is busy researching hybrid architectures. 

(Image credit: freepatentsonline.com)

The patent outlines a new instruction set subset implementation for low power operation. AMD's patent describes an implementation that allows for one subset of instructions to execute on larger full-featured processing cores optimized for higher performance, while a second subset of instructions run on smaller simplified cores designed for power efficiency. The patent outlines a method for the cores to use a shared memory location to speed the transfer of threads, based upon certain variables, between the two types of cores.

(Image credit: freepatentsonline.com)
(Image credit: freepatentsonline.com)
(Image credit: freepatentsonline.com)
(Image credit: freepatentsonline.com)
(Image credit: freepatentsonline.com)

In practice, the big cores would execute heavy performance-sensitive workloads, while the smaller cores would execute light tasks. When a core isn't busy, it could be shut off, thus improving power consumption further.

Intel has already forged ahead with a hybrid design with its Lakefield chips (half-heartedly branded as Big-Bigger), but unlocking maximum efficiency requires the operating system and applications to be aware of the architecture so they can target threads to the correct cores. There's already plenty of work underway to support that technique.

The method described in AMD's patent appears to allow the processor to independently sort out which type of thread should run on each cluster based on the instructions supported by the cores within. The threads could also shift between the cores based on utilization. For example, if the large core is underutilized, the processor would shift the thread to the small core (provided it supports the instructions). If the small core is over-utilized, the thread would shift to the larger core (again, provided it supports the instructions).

The approach appears to reduce or negate the need for OS intervention for some types of thread movements. The patent also explains an example wherein the clusters of cores could be CPUs, GPUs, or DSPs, meaning there's a dizzying array of possible combinations.

Intel uses multiple stacked dies that it ties together with its Foveros 3D stacking die-to-die interface, but that type of advanced packaging tech isn't necessarily required for a hybrid design. If AMD releases a hybrid computing design, it could come as one large die or an MCM design that leverages many of the fundamental concepts behind its existing architectures, among other possibilities. 

However, as with all patents, AMD's filing doesn't guarantee that we will see new products based on the technique. Underfox also cautions that the patent is still in the adjustment phase, so it is subject to change. Regardless, the filing certainly shows that AMD is actively researching its own type of hybrid implementations.

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