Report: Intels Haswell-E Processor to Support DDR4 Memory
According to Fudzilla, the Haswell-E will have from 12 to 16 cores, a TDP of 130 W, and support for DDR4 memory that promises to deliver exponentially more bandwidth than previous generations of processors.
Given that none of these details have been finalized and that DDR4 memory is still far from being finalized or produced, we're somewhat skeptical of this report and are interested in seeing how much of it actually turns out to be true.
What just happened? oO
Do they wanted to write 6 cores and 8 cores (so 12 threads and 16 threads)? This is a serious jump from 6 cores to 12-16 if this is true...
Intel's current Xeon E7 lineup has 10 models featuring 10 cores and 20 threads: http://www.intel.com/content/www/us/en/processor-comparison/compare-intel-processors.html?select=server
The lowest-end 10-core Xeon (E7-2850) had a $2558 launch price tag; roughly 8X the price of an i7-3770.
And there is the Xeon Phi which has up to 60 cores and 240 threads.
That stuff was produced before the DDR4 specification was finalized (which happened in September 2012). There doesn't have to be a specification for people to produce some prototypes, indeed the specification probably takes lessons learned from prototypes into account.
Sigh... the GDDR5 used in graphics card is a modified version of DDR3 memory. DDR4 is newer and more advanced than GDDR5. Most likely they'll later develop a GDDR6 based on DDR4.
Actually, GDDR5 is based on GDDR4 and GDDR3, which were based on DDR2.
RE this "report", we've known this for ages...
All of the details have been finalized, they just haven't been made public yet. Fudzilla is wrong in implying that "consumers" will get 12-16 cores. That'll be the higher end versions of the chip. -E will still be 6 cores...maybe 8 depending on what business decision the higher ups make.
Neither is really more "advanced" than the other. The fundamental DRAM structure has not changed in 20+ years and all SDR/DDR/GDDR 1/2/3/4/5/etc. do is tweak the front-end and addressing structure that manages access to the storage matrix. This is a large part of the reason why you can buy DIMMs that pack over 65 billion transistors (8GB) for less than $60.
Most improvements in DRAM are closely related to silicon process improvements and new DRAM standards simply tweak things some more to account for that... one extra register here, another one there, trading extra latency cycles for higher bandwidth. None of the "new standards" make any major technical improvements on previous versions of the same. What are the differences between DDR1 and DDR4? Minimum clock rates and chip densities have been increased by 8X, min/max latency has been increased by ~7 cycles, operating voltages have dropped to follow process shrinks... nothing particularly noteworthy.
Since the first step of designing a GDDR5 DRAM is ripping out just about everything that made the DRAM matrix comply with the DDR2/3 spec to replace it with GDDR5-specific variants, GDDR5 cannot really be called a "derivative" from DDR2/3... it does not reuse anything that specifically belonged to DDR2/3, just the generic DRAM matrix that can be turned into anything (DDR1/2/3/4, GDDR1/3/5, eDRAM, XDR, etc.) depending on what you wrap it with.
If I had to say DDRx/GDDRx were derived from something, I would say they are derived from PC66 SDRAM: PC66 introduced synchronous logic in DRAM's internal structures along with synchronous IO and nearly all changes since then have been about adding more of that for pipelining to accommodate faster clocks; more aggressively so on the GDDR front. DDR and GDDR are relatively minor tweaks by comparison.