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AMD Confirms Twelve DDR5 Memory Channels For Zen 4 EPYC CPUs

(Image credit: Samsung)

AMD has published a set of patches for the company's EDAC (Error Detection and Correction) driver code for the next-generation EPYC processors based on the Zen 4 microarchitecture. The new patches indicate that the upcoming CPUs will support unprecedented memory bandwidth and capacity per socket.

The patches (found by Phoronix) bring in support for DDR5 registered DIMMs (RDIMMs) and DDR5 load-reduced DIMMs (LRDIMMs) for the fourth-generation EPYC processors codenamed Genoa (Family 19h Models 10h-1Fh and A0h-AFh CPUs).

The patches also confirm that the upcoming EPYC 7004-series will support up to 12 memory controllers per socket, up from eight for AMD's existing server parts. Unfortunately, we do not know how many DIMMs per channel (DPC) the chips will support.

Twelve 64-bit DDR5 memory channels would theoretically increase the memory bandwidth available to Genoa processors to a whopping 460.8 GB/s per socket, a significant increase compared to the 204.8 GB/s available to current-generation EPYC CPUs with DDR4-3200. 

Memory bandwidth alone will not be the only improvement on next-generation EPYC 'Genoa' CPUs. Twelve memory channels will also enable higher memory capacities for the new processors. Samsung has already demonstrated 512GB DDR5 RDIMMs and confirmed that 768GB DDR5 RDIMMs were possible. Even using 12 512GB modules, AMD's next-generation server processors could support up to 6TB of memory (up from 4TB today). 

However, if Genoa supports two RDIMMs per channel, that capacity will stretch up to 12TB of DDR5. AMD could increase the capacity per memory channel and per socket further With LRDIMMs (due to octal-ranked module architecture), albeit at the cost of performance.

AMD's EPYC 7004-series 'Genoa' processors will bring tangible memory improvements compared to existing server processors, which will naturally improve their real-world performance.