Researchers with the Peking University and other institutes in China have managed to miniaturize carbon nanotubes towards a 90nm FET (Field-Effect Transistor) scale — the densest ever achieved — therefore charting a course to an equivalent density as today's 10nm semiconductor nodes. Originally published in Nature Electronics, the research marks the furthest miniaturization of a carbon-tube-based FET up to now and could help China modernize its manufacturing technology in ways that shield it from the US and its allies' technological sanctions.
Carbon nanotubes have long (read: really long) been one of the most promising candidates for an updated transistor design that's capable of faster switching speeds (higher operating frequencies) with lower leakage (less wasted electricity) and, ultimately, greater efficiency and performance.
"Recent progress in achieving wafer-scale high density semiconducting carbon nanotube arrays brought us one step closer to the practical use of carbon nanotubes in CMOS circuits," Zhiyong Zhang, one of the researchers who carried out the study, told Phys.org. "However, previous research efforts have mainly focused on the scaling of channel or gate length of carbon nanotube transistors while keeping large contact dimensions, which cannot be accepted for high density CMOS circuits in practical applications," he added.
The problem referenced by Zhiyong Zhang is a known one for us tech enthusiasts: long has the nanometer race become more of a marketing push rather than an actual description of the size of the transistors embedded in the design. We've recently seen an admission of this exact issue within Intel's rebranding efforts for its 10nm SuperFin process (now just Intel 7, with the offending and mostly useless "nm" element being shown the easy way out). But why sell your product as a "real" 12nm process when 10nm is smaller and, therefore, better?
Marketing chest-thumping aside, the semiconductor industry does have a standard for characterizing transistors at the nanometre level: contacted gate pitch and the 6T SRAM cell area.
The researchers took a fine-tune approach to their design, scaling down from easier, less dense designs until they reached the 10nm-equivalent breakout point. Initial carbon nanotube FET designs achieved by the team featured a "nm density" at 175nm but showcased density, switching, and thermal characteristics surpassing those achieved with 45 nm CMOS processes. They then moved on to a 90nm-tier carbon nanotube design, which once again proved functional.
"Our work experimentally demonstrated a true 90nm node technology using carbon nanotubes, which could be made geometrically smaller and offer electronic performance outperforming silicon 90nm node transistors."
To allow for this impressive scaling, the researchers had to devise a new way to cut the carbon nanotubes (whose length typically defines the tube's electrical resistance) to be able to create shorter tubes that still displayed the required electrical characteristics. In the end, they expect their carbon nanotube FET design to be scalable down to sizes comparable to those found in 10nm node silicon transistors.
There's something to be said about China's recent victories in the research and academic fields as the country looks for a way out of US-imposed chip and technology import restrictions that gut China's ability to achieve its goal of being a self-sufficient producer of chips that are competitive with their Western counterparts. One way for China to circumvent restrictions is for the country to simply do the research itself. The more leading-edge the research, the better: China will need more time to procure the materials, patents, and technology that'll allow it to then pursue and manufacture these products without being hampered by trading restrictions.
