AMD Outsources To TSMC For CPUs

Chicago (IL) - News that AMD has taken a big step to outsource its manufacturing to TSMC and that wafer testing for SOI mass production has begun mad waves yesterday. The speculated background is AMD’s upcoming Fusion processor, but there are clearly many more implications: Not only will TSMC turn into a CPU manufacturing giant, but we could see a completely new direction GPUs as well.

The closer relationship between AMD and TSMC isn’t a surprise as the two companies last year signed a Memorandum of Understanding (MOU) with AMD with the explicit goal to outsource the manufacturing of AMD processors. According to the information we had last year, the ramp into volume production was supposed to happen in Q2 2008). We now know that the two companies are on track to deliver on that promise.

However, the simple fact that TSMC is jumping on the SOI train, as opposed to simply remain a bulk production facility, is probably the most significant between AMD and TSMC so far. Intel has been beating the "SOI-is-dead" drum ever since IBM came up with the technology, and many Intel-centric analysts have been nagging AMD why to keep the more expensive SOI manufacturing technology in place. And yet, even Intel used SOI wafer for a demonstration of its silicon laser interconnect.

Today, almost 10 years after IBM’s introduction paper describing the SOI manufacturing process, published on August 3, 1998, SOI has expanded its reach dramatically. If you buy a game console today, you are getting SOI chips from Microsoft, Sony or Nintendo. You can argue that this is because of the fact that all those chips are IBM-based, but they are not manufactured by a single fab and company: They come from IBM, Chartered Semiconductor and Toshiba. The indication is that those contracts were not won because IBM is IBM: The power envelope and power/performance ratio is always a key part of any chassis deal and SOI technology apparently delivered.

If you wonder what that AMD/TSMC deal will mean for you, the effects of this tie-up are very simple: TSMC has a massive output capacity. TSMC manufactures more than two thirds of all chips sold by ATI, Nvidia, VIA, Conexant, Marvell, FPGA manufacturers and FPU accelerators. TSMC is considered the world’s largest foundry today.

Even if AMD puts restrictions on the use of SOI, TSMC is likely to gain experience to develop and enhance its manufacturing technologies with SOI wafers, including lucrative "half-node die shrinks". One of the potential cash cows is the scaling of 45 nm SOI to 40 nm SOI. This also applies to the 32 nm process and its half-node shrink.

The main benefactors of TSMC taking the FD-SOI/PD-SOI/SiGe/High-K routes could be GPU manufacturers, who are now dangerously close to hitting a thermal wall. The upcoming part from Nvidia features a TDP well in excess of 220 watts, while we still remember the power issues that ATI encountered with its R600 chip and ill-fated 80 nm and 65 nm decisions, which resulted in a current-bleeding chips.

Fusion is really nothing else than a R7xx derivative GPU and AMD’s Shanghai core, manufactured in a 45 nm SOI process. But this will also be world’s first GPU manufactured using SOI. The second manufacturer that might be lured into this technology may be Microsoft, who is looking for a foundry partner to manufacture its "Valhalla" chip. As previously reported, Valhalla is a 45 nm SOI chip that combines IBM’s triple-core Xenon CPU with ATI’s Xenos GPU. IBM/Chartered already manufactured CPUs using 90 nm and 65 nm SOI processes. A shrink to 45 nm should not be a big deal. The ATI Xenos part could be the second GPU that may take the 45 nm SOI route (after Fusion). In fall of 2009, we could see the world’s first discrete GPUs using 45 nm, 40 nm or even 32 nm SOI nodes.

According to our sources at TSMC, the company expects several challenges with the new wafer processing technology, and according to an industry source, TSMC "wants to explore all options that would lead to expanding the manufacturing base and offering the best performance/watt characteristics".

If TSMC ends up with contracts for both Fusion and Valhalla, TSMC would become a huge CPU manufacturer.

  • Why does everyone keep saying SOI = low power? People naturally associated this when AMD had significantly lower power chips vs Intel P4's - but this was primarily a DESIGN, not SOI improvement. Funny how when you look at either the 90 and 65nm mobile chips or the 65nm Core based chips, suddenly the 'high power' bare Si process was more than holding it's own vs SOI? Wonder why that is...

    SOI simply reduces junction leakage... in the grand scheme of things this is rather small compared to the gate and subthreshold leakages (which SOI does not address). As a result you would see minimal improvement for graphic chips moving to SOI (unless of course they implement high K - though you don't need SOI for that)

    "The power envelope and power/performance ratio is always a key part of any chassis deal and SOI technology apparently delivered."

    Complete Bunk...