IDF 2008: Gelsinger Acts Cool, Reveals Little

San Francisco (CA) - A sunglass-wearing Pat Gelsinger acted cool, but revealed little during his keynote speech at the Intel Developers Forum in San Francisco. Intel’s senior vice president and co-general manager of the Digital Enterprise Group did talk about the upcoming power saving features in the Nehalem processor and boasted about recent supercomputing records broken by the company’s Xeon processors.

Gelsinger said Nehalem processors will commercially be available in the fourth quarter for desktops and servers. During his keynote, he added that Nehalem will eventually come to laptops and showed off a validation motherboard. Sure this is a desktop-sized board, but within the coming months this will surely be shrunk down to notebook proportions.

Nehalem will debut as a multi-threaded quad-core processor (welcome back Hyperthreading) capable of running eight threads. Like AMD processors, the chip will feature an on-die memory controller and built on a monolithic die - no more "gluing" processors together. Power users requiring lots of memory bandwidth and capacity will love the processor because of its triple-channel DDR3 and Gelsinger teased the audience with sticks of memory with 8 and 16 gigabytes each. You can do the math with 3 slots. Server machines will have even more slots for hundreds of gigabytes of RAM.

But won’t such a chip use a lot of power? Gelsinger explained that the "Turbo Mode" power saving feature should keep power consumption in check. Just the mere mention of turbo mode probably brings back memories from the 286/386 days of pushing a case button to increase your computer’s speed. However, Nehalem’s turbo mode is nothing of the sort and can move thinly threaded applications to run on fewer cores, something which effectively disables and cuts power to the unneeded cores. An Intel engineer said the power control unit that makes all this magic happen is more than one million transistors. Something which Gelsinger said is more than the 486 processor that he helped design.

Intel is already testing six-core server versions of the Nehalem. These monsters have 16 MB of cache and run at 2.66 MHz. Gelsinger announced that these chips have broken several supercomputing records including achieving 634,824 tpmC on a C-SQL benchmark and 1.2 million transactions per minute on a DB2 database benchmark.

While Gelsinger didn’t reveal too much we didn’t already know, we were shown Intel’s latest quad-core mobile chip in the press room. We’ll have more details later after we wipe our drool from our mouths.