Chicago (IL) - Intel will delay the introduction of a new processor package that is designed to integrate silicon inside the package instead of attaching a chip and package. The technology originally was scheduled to become available by 2006.
Bumpless Build-Up Layer (BBUL) packaging was first presented to the public in October 2001 and considered a key component to scale processor speeds to eight GHz by 2005 and to beyond 15 GHz by 2007.
The approach is based on the idea to integrate silicon completely into the processor package instead of building the die on top of it. Advantages of the BBUL technology include small electrical loop inductance and reduced thermo-mechanical strain imposed on interconnects. Prototypes of BBUL packages in 2001 showed just about one third the height of a common processor package, required only 20 to 30 percent the supply voltage of their counterparts. Shorter C4 interconnects were believed to significantly contribute to higher processor speeds.
"Itanium chips already offer up to nine MByte of cache in the current package. And these processors are manufactured are built in 130 nm. We are looking already to introducing 65 nm processors by the end of this year," Vara said.
He called it unlikely that BBUL will be introduced until such scaling steps remains possible. The technology however is likely to appear commercially when "different pieces of silicon with different functions" need to be combined in one package. Such functions for example include chipsets and SDRAM. Vara declined to comment on when such a chip could be become available. However the "first few" generations of multicore processors would not make the move to BBUL, he said.