When Micron officially announced first generation 3D NAND flash technology, the company claimed this would lead to 3.5 TB gum stick-sized SSDs and more than 10 TB standard 2.5-inch SSDs. In our latest briefing, we learned more about the technology that will bring these products to reality.
Most flash sold today is planar (2D), like a single story home. The technology progressed by fitting more bits in the same amount of space. To do so, the size and the distance between each bit needed to shrink. 3D technology increases density by building layers of cells vertically, like a skyscraper. The vertical skyscraper holds more data in the same footprint than a single story structure.
Micron's first generation 3D flash technology uses 32 layers to build a single die. In multi-level cell (MLC) mode, the die density comes to 256 Gbit. Competing technology shipping today needs 48 layers to achieve the same density. In 3-bit per cell mode (TLC), the same die holds 384 Gbit of data. The new cells double the bit density compared to Micron's 16nm planar NAND. The block sizes increase to 16 MB for MLC and 24 MB for TLC modes.
The increased density comes, in part, from Micron's CMOS Under the Array technology. In planar NAND, the logic cells that control the flash makes up as much as 20% of the overall size. With the logic control tucked under the storage portion of the die, like a basement or parking garage, more storage capacity can fit in the same footprint.
The CMOS also handles special functions like FortisFlash, used to deliver advanced ECC solutions on die, and SLC areas used to increase write performance.
The new storage structure uses floating gate technology. Micron claimed this combats charge loss better than charge trap technology used by its competitors. With less loss, Micron's 3D flash will require less error correct technology that consumes more power over time. In theory, floating gates will also allow Micron to be much more aggressive with the vertical stack from generation to generation. SK Hynix attempted to build 3D NAND flash with floating gates but eventually scrapped the project to build on charge trap technology. It's our understanding that floating gates are much more difficult to build vertically, but at the same time, it's the technology Micron and Intel mastered long ago.
The new 3D flash moves to Open NAND Flash Interface (ONFi) 4.0, a specification built and maintained by Intel, Micron, Phison, SanDisk, SK Hynix and others to build a common interface for flash. The fourth revision increases performance up to 800 MT/s with a quad plane path and reduced power to just 1.2 volts.
Endurance is often a subject that NAND flash manufacturers try to avoid, but not this time. Paired with Low Density Parity Check (LDPC) error correction technology, MLC 3D flash from Micron can deliver up to 30,000 program / erase (P/E) cycles. The high endurance also enables TLC in the enterprise (eTLC).
The change in power means Micron's new 3D 32-layer flash can move up to 30% more data with the same amount of power used today with planar NAND. This will increase notebook battery life and reduce datacenter power consumption.
The new density will double die capacity in end products, effectively making 256 GB models the new 128 GB drives of today. Without any special configurations, 2 TB SSDs will be possible at the time of retail availability and shouldn't have a large price premium over existing 1 TB SSDs sold today. The increase in endurance will also take us back to a time when it was an afterthought and rarely discussed outside of the enterprise market.
At CES, we saw client SSDs in the R&D stage armed with Micron 3D MLC. Micron told us the first retail products should arrive in June, around the Computex time frame. Client SSDs paired with 3D MLC should arrive first with TLC products soon after. Eventually, TLC will dominate the client market -- even high-performance PCIe based models.
Micron has worked closely with Silicon Motion, Inc. on a client solution, and with PMC Sierra for an enterprise product. The time frame lines up with what we've heard from other companies eager to tap into the vertical pipeline.
We pressed Micron about a potential 3D TLC / 3D XPoint pairing wherein XPoint acts as a large, high performance buffer for slower TLC NAND. we were told, "We can't talk about that, but it would make a very good cache or buffer."
The combination is obvious but would require an advanced controller and programming. We will have to wait on a XPoint update to learn more.