In the past few years, we've seen rising demand for 64-bit mobile CPUs, as smartphones and tablets become more PC-like in terms of the performance they provide. We've seen 64-bit mobile CPUs from ARM chip makers and Intel, and today, Imagination launched its own MIPS64 mobile CPU design, called the P6600. Imagination also announced two new mid-range M6200 and M6250 CPUs.
The 64-bit P6600 is the next-generation CPU core from Imagination, and the successor to the 32-bit P5600. The new core is based on the MIPS64 Release 6 architecture, and it will target a broad range of applications, including mobile, but also home entertainment, networking, HPC, and industrial and embedded computing.
The P6600 is a high-performance core that combines a multi-issue 16-stage pipeline and out-of-order execution to deliver high computational throughput for modern mobile applications. Imagination also claimed that the P6600 includes "best-in-class branch prediction" and a load/store instruction bonding mechanism, which provide a "clear boost in real-world workloads" while keeping die size and power consumption low.
The P6600 is OmniShield-ready, while supporting more than twice as many (15) guest operating systems as its predecessor, the P5600. The guest operating systems can all run simultaneously in "fully isolated and trusted environments."
This is one of the features that sets Imagination's CPUs apart from the competition, as security starts to play a bigger role in mobile, with billions of users owning a smartphone, but also in IoT, the automotive industry, and so on.
System builders can include up to six P6600 cores in their designs. Imagination's new chip comes with a SIMD engine, which is utilized for fast media acceleration such as VP9 decoding.
The company also introduced the M6200 and M6250, which have 30 percent higher clock speeds compared to their predecessors, the microAptiv UC and UP. They both also include:
Tightly coupled memory (TCM) for high-performance applicationsAn interrupt controller supporting up to 256 interruptsThe MIPS DSP Module Revision 3 as a configurable option, providing a high level of digital signal processing capabilities and SIMD support.ECC and parity on instruction and data memories as a configurable option for increased reliabilityA new APB interface enabling JTAG, multicore and mixed core debugging
The new M-class CPU cores have 6-stage pipeline designs and are built on the MIPS32 Release 6 architecture. They also include support for the microMIPS32 ISA, which contains a set of optimized 16-bit and 32-bit instructions that significantly reduce the code size.
The M6200 CPU targets mainly the embedded market and will run a real-time operating system, while the M6250 will be able to run full Linux distros.
The M6250 comes with a high-speed 64-bit AXI bus interface, a Memory Management Unit (MMU), data and instruction cache controllers, and support for eXtended Memory Addressing (XPA) to 40-bit physical address space (up to 1 TB of system memory).
Imagination said that it will remain committed to expanding its range of CPUs in the future, based on Release 6 of its MIPS architecture, on which cores such as the I6400, M6200, M6250 and the P6600 have already been designed. However, it will be up to chip makers and OEMs to want to adopt MIPS CPUs in a greater number of devices before most consumers can see them on the market as a real alternative to ARM-based and x86-based chips.
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Lucian Armasu joined Tom’s Hardware in early 2014. He writes news stories on mobile, chipsets, security, privacy, and anything else that might be of interest to him from the technology world. Outside of Tom’s Hardware, he dreams of becoming an entrepreneur.
You can follow him at @lucian_armasu. Follow us on Facebook, Google+, RSS, Twitter and YouTube.
