The University of Rochester has created the first true stacked 3D processor running at 1.4 GHz.
As processors continue to head in the direction of miniaturization, with an ever increasing number of cores, some design engineers believe miniaturization will eventually hit a limit and the only direction left to go will be upwards. One such engineer is Eby Friedman of the University of Rochester, co-creator of a new 3D chip technology, and he believes his new processor is unique to previous 3D chip designs.
Unlike past 3D chips that were simply stacks of regular processors, this new chip, or "cube" as Friedman calls it, has its layers flush against one another, with millions of tiny holes drilled through the layers to connect them, giving the 3D chip abilities unachievable by single layer processors. The new 3-D processor was designed specifically for optimized vertical processing between layers, much like how traditional processors have been designed for horizontal processing.
Currently the design of the processor Friedman and his students have created clocks in at 1.4 GHz and it is the first 3D chip to ever feature such tasks as synchronicity, power distribution and long-distance signaling. With limits of miniaturization facing the integrated circuit industry, stacking of transistors is believed by some designers to be an eventual direction for processor designs, but such a direction will introduce many new challenges of its own.
Friedman says that one difficulty will be having all the layers interact together as a single system, where accomplishing such harmony in a 3D chip would be much like stacking the traffic systems of the United States, China and India on top of one another. Each traffic system will have its own different set of traffic laws and having to allow drivers at any point move between layers while still simultaneously managing all the other traffic.
A while back we saw IBM looking ahead to 3D chip stacks as well, but the company quickly realized that it would have to overcome a major obstacle -– heat. Conventional cooling methods do not scale well with 3D chip stacks and IBM’s solution to this future problem was designing the chip stacks to allow water to flow between the layers, providing for a scalable cooling solution. Interconnects between the layers would be insulated, protecting them from the water and allowing for the layers to still communicate at high-speeds. Whether or not the new 3D processors that the University of Rochester have designed would be able to integrate similar technologies, has yet to be seen.