The IEEE today announced that it has ratified the SystemC 2.1 language for system-level chip design which the organization believes will accelerate system-on-chip (SoC) design processes. Officially called IEEE 1666, the description of SystemC 2.1 addresses the increasing complexity of system-on-chip (SoC) design at the systems level. "It lets engineers architect entire systems from the start, which speeds design, and allows for the sharing and reuse of intellectual property," the IEEE said.
"As we approach chip features at 65 nm or less, the need for high-level design that addresses both hardware and software together is a driving force in realizing complex SoCs," said Victor Berman, chair of the P1666 Working Group at IEEE and director of Language Standards at Cadence Design Systems. "The sheer complexity of today's SoCs and the significant rise in the demand for IP reuse has made the move to high-level system design a necessity."
